CN1905145A - 制造层叠芯片封装的方法 - Google Patents

制造层叠芯片封装的方法 Download PDF

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Publication number
CN1905145A
CN1905145A CNA2006100940722A CN200610094072A CN1905145A CN 1905145 A CN1905145 A CN 1905145A CN A2006100940722 A CNA2006100940722 A CN A2006100940722A CN 200610094072 A CN200610094072 A CN 200610094072A CN 1905145 A CN1905145 A CN 1905145A
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China
Prior art keywords
chip
bottom base
stacked die
encapsulation
chips
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CNA2006100940722A
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English (en)
Inventor
阿米努丁·伊斯梅尔
卢威耀
张光美
杨清才
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NXP USA Inc
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Freescale Semiconductor Inc
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Publication of CN1905145A publication Critical patent/CN1905145A/zh
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Abstract

一种制造层叠芯片封装(50)的方法，所述方法包括：将第一集成电路(IC)芯片(52)与底部基座(56)相连并电连接。在第一芯片(52)上形成多个依次相叠的粘合材料(54)层(54A、54B和54C)。利用粘合材料(54)使第二芯片(72)连接在第一芯片(52)上，使得依次相叠的粘合材料层(54A、54B和54C)在第一芯片(52)和第二芯片(72)之间保持预定的间距(H)。第二芯片(72)与底部基座电连接(56)。

Description

制造层叠芯片封装的方法
发明背景
本发明总体涉及集成电路(IC)的封装，更具体地说涉及一种制造层叠的芯片封装(stacked die package)的方法。
层叠的芯片封装的特征在于具有层叠在单个封装内的两个或多个芯片。两个或多个芯片层叠在单个封装内提高了封装的功能集成，而无需提高其尺寸。图1表示常规的层叠的芯片封装10。封装10包括下芯片12、底部基座14以及上芯片16。底部芯片12利用第一粘合层18连接在底部基座14上。在下芯片12和上芯片16上的结合片(未示出)分别利用第一导线20和第二导线22通过引线接合与底部基座14电连接。利用树脂24对下芯片12和上芯片16以及第一和第二导线20、22进行密封，由此形成层叠的芯片封装10。从图1中可以看到，当上芯片16连接到下芯片12上时，在下芯片和上芯片12、16之间需要有足够大的间距以防止对第一导线20产生破坏。因此，常规的做法一直是采用隔离件26，其通常是一个空白硅芯片，从而可以在下芯片和上芯片12和16之间有足够的间距。隔离件26利用第二粘合层28连接在下芯片12上，并且随后上芯片16利用第三粘合层30连接在隔离件26上。在层叠芯片封装中采用空白硅芯片以解决在层叠上芯片16时对第一导线20产生破坏的问题的同时，其提高了加工准备时间以及制造成本。
鉴于以上所述，需要提供一种廉价的制造层叠芯片封装的方法，该方法不需要空白硅芯片。
附图说明
当结合附图阅读时将会更清楚地理解以下对本发明的优选实施方式的详细描述。本发明以举例方式示意说明并且不受附图限定，在附图中相同的附图标记表示相似的构件。将会理解到为了便于理解本发明，附图不是依比例绘制并被简化。
图1是常规的层叠芯片封装的放大横截面视图；
图2是根据本发明的实施方式在其上形成有多个粘合材料层的第一或下芯片的放大横截面视图；
图3是包括第二或上芯片的图2所示的下芯片的放大横截面视图；
图4是根据本发明的另一实施方式通过反向结合连接到底部基座的下芯片的放大横截面视图；
图5是具有在其上形成的多个粘合材料层的图4所示的下芯片的放大横截面视图；以及
图6是具有在其上层叠的上芯片的图5所示的下芯片和粘合材料层的放大横截面视图。
具体实施方式
下文结合附图提出的详细描述被作为是对本发明当前优选实施方式的描述，而不是要代表实施本发明的唯一形式。将会理解到相同或等效功能可以由包含在本发明的精神和范围内的不同的实施方式实现。为了简化，被用于说明本发明的实例仅涉及具有两个层叠芯片的封装。但是，实际上同样的发明可被应用在具有多于两个层叠芯片的封装上。在附图中，相同的附图标记被用于表示各视图中的同一构件。
本发明提供了一种制造层叠的芯片封装的方法，所述方法包括以下步骤：将第一集成电路(IC)芯片与底部基座相连并电连接。在第一芯片上形成多个依次相叠的粘合材料层。第二芯片利用粘合材料连接在第一芯片上，使得依次相叠的粘合材料层在第一芯片和第二芯片之间保持预定的间距。第二芯片与底部基座电连接。
本发明还提供了一种制造层叠芯片封装的方法，所述方法包括以下步骤：将第一IC芯片连接在底部基座上，第一芯片具有下表面和上表面。上表面具有中心区和外围区。外围区包括多个第一芯片结合片。第一芯片的下表面连接在底部基座的顶面。第一芯片通过将第一导线与第一芯片结合片引线接合并与底部基座的顶面引线接合而与底部基座电连接。在第一芯片上表面的中心区上形成多个依次相叠的粘合材料层。第二芯片的下表面利用粘合材料连接在第一芯片的上表面上，使得依次相叠的粘合材料层在第一芯片和第二芯片之间保持预定的间距。第二芯片包括位于其上表面上的多个第二芯片结合片。通过将第二导线与第二芯片结合片引线接合并与底部基座的顶面引线接合而使第二芯片与底部基座电连接。最后，第一和第二芯片、第一和第二导线、以及底部基座的至少一部分被封装。
本发明还提供了一种制造层叠芯片封装的方法，所述方法包括以下步骤：将第一IC芯片连接在底部基座上，第一芯片具有下表面和上表面。上表面具有中心区和外围区。外围区包括多个第一芯片结合片。第一芯片的下表面连接在底部基座的顶面上。在各个第一芯片结合片上形成多个第一突耳。通过将来自底部基座顶面的第一导线反向连接在第一芯片结合片上的第一突耳上而使第一芯片与底部基座电连接，使得在第一突耳上形成多个针脚连接。在针脚连接上形成多个第二突耳。在第一芯片上表面的中心区上形成多个依次相叠的粘合材料层。第一和第二突耳形成了环绕第一芯片外围区的壁以包含粘合材料。第二芯片的下表面利用粘合材料连接在第一芯片的上表面上，使得依次相叠的粘合材料层在第一芯片和第二芯片之间保持预定的间距。第二芯片包括位于其上表面上的多个第二芯片结合片。通过将第二导线与第二芯片结合片引线接合并与底部基座的顶面引线接合而使第二芯片与底部基座电连接。最后，第一和第二芯片、第一和第二导线、以及底部基座的至少一部分被封装。
图2和3是表示制造根据本发明一个实施方式的层叠芯片封装50的方法的放大横截面视图。
现在参照图2，示出了具有在其上形成的多个粘合材料54的依次相叠的层54A、54B和54C的第一或下集成电路(IC)芯片52。第一芯片52与底部基座或基底56相连并电连接。
第一芯片52具有下表面58和上表面60。上表面60包括中心区(未示出)和外围区(未示出)。第一芯片52的下表面58利用粘合剂(未示出)连接在底部基座56的顶面62上。粘合剂可以是任意适当的粘合材料，例如胶粘带、热塑性粘合剂、环氧树脂材料等等。用于将IC芯片连接在底部基座上的这种粘合剂对本领域的技术人员是众所周知的。
第一芯片52利用第一导线64与底部基座56电连接。在这一特定实例中，第一导线64与第一芯片52外围区上的多个第一芯片结合片66引线连接并与底部基座58的顶面62引线连接。适当的接合导线通常包括导电金属线，其通常由铜或金构成。
通过将粘合材料54以多次施加的方式分配在第一芯片52中心区上而形成依次相叠的粘合材料层54A、54B和54C。在这一特定实例中，粘合材料54以未固化或软化状态在多次施加中被分配在第一芯片52上表面60的中心区上。在每次施加后，粘合材料54通过暴露和/或加热规定的时限而被固化。当在前的层54A和54B分别基本上固化，也就是当组成在前的层54A、54B的粘合材料54处于胶状可变形状态时，用于每个后续的层54B和54C的粘合材料54被分配。固化程度可通过调节加热部件(未示出)的温度来控制，这是本领域的技术人员公知的。
当完全固化时，依次相叠的粘合材料层54A、54B和54C提供所需的将第二或上芯片固定在第一芯片52上的机械强度，如下文所述。依次相叠的粘合材料层54A、54B和54C可以多种方式在第一芯片52上形成，例如利用针68和注射器(未示出)或环氧树脂溢流记录器，这是本领域的技术人员公知的。在这一特定实例中，每个粘合材料层54A、54B和54C的厚度在大约1.5密耳-大约2.0密耳之间。但是，应该理解，本发明并不受每个层54A、54B和54C的厚度的限制。每个层54A、54B和54C的厚度可通过改变分配粘合材料54的针68的尺寸而变化。
尽管在这一特定实例中的粘合材料54不与第一导线64接触，但本领域技术人员将会理解到，粘合材料54在备选实施方式中可接触或封盖在第一导线64和第一芯片52的第一结合片66之间形成的引线接合70，由此加强它们之间的接合。粘合材料54可包括被用于将一个芯片连接在另一个芯片上的任何通常的粘合剂。通常的粘合剂包括环氧树脂、氰酸酯以及聚酰亚胺。粘合材料54优选是搭扣固化(snapcure)材料，这是本领域技术人员公知的。
现在参照图3，示出了层叠芯片封装50，其中第二或上芯片72层叠在第一芯片52上。更具体地说，利用粘合材料54第二或上芯片72的下表面连接在第一芯片52的上表面60上。第二芯片72的下表面粘合在粘合材料54的最上层，在这里是层54C。粘合材料层54A、54B和54C保证在第一和第二芯片52和72之间有足够的间距以确保第二芯片72不会破坏第一导线64与结合片66的电连接(引线接合)。
第二芯片72与底部基座56电连接，其提供了用于使第一和第二芯片52和72相互电连接并与其它部件或装置电连接的互连网。在这一特定实例中，第二芯片72利用第二导线74与底部基座56电连接，第二导线74与位于第二芯片72上表面上的多个第二芯片结合片76引线接合并与底部基座56的顶面62上的对应结合片引线接合。第二导线74优选与第一导线64是同一类型的。
最后，第一和第二芯片52和70、第一和第二导线66和74、以及底部基座56的至少一部分利用密封剂78例如树脂被封装。可通过执行模压操作来完成所述封装步骤，这对本领域技术人员是公知的。
如上所述，依次相叠的粘合材料层54A、54B和54C在第一和第二芯片52和72之间保持预定间距H。预定间距H足以保护第一芯片52和底部基座56，在这里是第一导线64之间的电连接不受第二芯片72与第一芯片52连接的破坏。在这一特定实例中，预定间距H至少是大约5密耳。尽管如此，本领域技术人员将理解到本发明并不受间距H大小的限制。而是，间距H的大小取决于由第一导线64延伸超出第一芯片52的上表面60而形成的线圈的高度HL。具体地说，间距H必须比线圈的高度HL更大。例如，大约6密耳的间距H要求由大约4密耳的线圈高度HL。尽管在图2和3中仅示出了三个(3)依次相叠的粘合材料层54A、54B和54C，但本领域技术人员将理解到本发明并不受第一芯片52上形成的依次相叠的粘合层的数量的限制，根据所需的间距H和每层的厚度可以有更多或更少的层。
第一芯片52和第二芯片72优选具有基本上相同的长度和宽度尺寸。但是，第二芯片72可以比第一芯片52略微更大或略微更小。例如，通常第一和第二芯片的尺寸范围可从4毫米×4毫米-12毫米×12毫米。第一和第二芯片52、72还可具有相同的厚度，但是，这不是必需的。根据所需的最终封装的外形厚度，第一和第二芯片52、72可具有从大约6密耳到大约21密耳的厚度范围。底部基座56、第一芯片52、以及第二芯片72中的每个都是本领域普通技术人员公知的类型，为了完整的理解本发明并不需要对这些部件进行进一步的描述。
现在参照图4-6对本发明的另一实施方式进行描述，图4-6是表示制造层叠芯片封装100的方法的放大横截面视图。
现在参照图4，第一或下芯片102通过反向接合与底部基座或基底104相连并电连接，如图所示。第一芯片102具有下表面106和上表面108。上表面108包括中心区(未示出)和外围区(未示出)。第一芯片102的下表面106利用粘合剂(未示出)连接到底部基座104的顶面110上。粘合剂可以是任何适当的粘合材料，例如胶粘带、热塑性粘合剂、环氧树脂材料等等。用于将IC芯片连接在底部基座上的这种粘合剂对本领域的技术人员是众所周知的。
在第一芯片102外围区上各个第一芯片结合片114上形成多个第一突耳112。第一芯片102利用第一导线116与底部基座104电连接。在这一特定实例中，第一导线116从底部基座104的顶面110反向连接到第一芯片结合片114上的第一突耳112，使得在第一突耳112上形成多个针脚连接。适用的结合线一般包括金属线，如铜或金线。在针脚连接上形成多个第二突耳118。第一和第二突耳112和118形成环绕第一芯片102外围区的壁。
现在参照图5，在第一芯片102上形成多个依次相叠的粘合材料120的层120A、120B、120C和120D。通过将粘合材料120以多次施加的方式分配在第一芯片102上而形成依次相叠的粘合材料层120A、120B、120C和120D。在这一特定实例中，粘合材料120以未固化或软化状态在多次施加中被分配在第一芯片102上表面108的中心区上。在每次施加后，粘合材料120通过暴露和/或加热规定的时限而至少局部被固化。当在前的层120A、120B和120C分别基本上固化，也就是当组成在前的层120A、120B、120C的粘合材料120处于胶状可变形状态时，用于每个后续的层120B、120C和120D的粘合材料120被分配。如上所述，固化程度可通过调节加热部件(未示出)的温度来控制，这是本领域的技术人员公知的。
当完全固化时，依次相叠的粘合材料层120A、120B、120C和120D提供所需的将第二或上芯片固定在第一芯片102上的机械强度，如下文所述。依次相叠的粘合材料层120A、120B、120C和120D可以多种方式在第一芯片102上形成，例如利用针122和注射器(未示出)或环氧树脂溢流记录器，这是本领域的技术人员公知的。在这一特定实例中，每个粘合材料层120A-120D的厚度在大约1.5密耳-大约2.0密耳之间。但是，应该理解，本发明并不受每层厚度的限制，每个层的厚度可通过改变分配粘合材料120的针122的尺寸而变化。
环绕第一芯片102外围区形成的第一和第二突耳112和118的壁用于包含粘合材料120，所述粘合材料被分配在第一芯片102的中心区上。尽管壁中在第一和第二突耳112和118之间有间隙，粘合材料仍借助毛细作用容纳在壁内，这是由于壁所形成的容器具有很小的横截面积的缘故。粘合材料120优选是搭扣固化材料，这对本领域技术人员是公知的。
现在参照图6，示出了层叠芯片封装100。第二或上芯片124的下表面利用粘合材料120连接在第一芯片102的上表面108上。更具体地说，第二芯片124粘附在粘合材料120的最上层120D。第二芯片124随后与底部基座104电连接，其提供了用于使第一和第二芯片102和124相互电连接并与其它部件或装置电连接的互连网。在这一特定实例中，第二芯片124利用第二导线126与底部基座104电连接，第二导线与第二芯片124上表面128上的多个第二芯片结合片(未示出)引线接合并与底部基座104的顶面引线接合。最后，第一和第二芯片102和124、第一和第二导线116和126、以及底部基座104的至少一部分利用密封剂130例如树脂被封装。焊球(未示出)可连接在基底104的下表面上，由此形成BGA封装，这在本领域内是公知的。备选地是，基底104可包括引线框标记区，从而形成QFN型封装。例如可通过阵列也就是模制阵列过程(MAP)一次形成一个或一次形成多个封装装置100。
如上所述，依次相叠的粘合材料层120A-120D在第一和第二芯片102和124之间保持预定间距H。预定间距H足以保护第一芯片102和底部基座104，在这里是第一导线116之间的电连接不受第二芯片124与第一芯片102连接的破坏。在这一特定实例中，预定间距H至少是大约5密耳。尽管如此，本领域技术人员将理解到本发明并不受间距H大小的限制。如上所述，间距H的大小必须比由第一导线114延伸超出第一芯片102的上表面108而形成的线圈的高度HL更大。另外，尽管在图4-6中仅示出了四个(4)依次相叠的粘合材料层120A、120B、120C和120D，但本领域技术人员将理解到本发明并不受第一芯片102上形成的依次相叠的粘合层的数量的限制，根据所需的间距H和每层的厚度可以有更多或更少的层。
而且，如上所述，第一和第二芯片102和124优选具有基本上相同的长度和宽度尺寸。但是，第二芯片124可以比第一芯片102略微更大或略微更小。例如，通常第一和第二芯片的尺寸范围可从4毫米×4毫米-12毫米×12毫米。第一和第二芯片102、124还可具有相同的厚度，但是，这不是必需的。根据所需的最终封装的外形厚度，第一和第二芯片102、124可具有从大约6密耳到大约21密耳的厚度范围。底部基座104、第一芯片102、以及第二芯片124中的每个都是本领域普通技术人员公知的类型，为了完整的理解本发明并不需要对这些部件进行进一步的描述。
尽管已经对制造层叠芯片封装的方法进行了描述，但本发明还提出了一种层叠芯片封装，其包括具有顶面和底面的底部基座、与底部基座相连并电连接的第一集成电路(IC)芯片，第一芯片具有下表面和上表面，上表面具有中心区和外围区，其中第一芯片的下表面与底部基座的顶面相连；在第一芯片上表面的中心区上形成多个依次相叠的粘合材料层；第二IC芯片具有利用粘合材料连接到第一芯片上表面的下表面，其中依次相叠的粘合材料层在第一芯片和第二芯片之间保持预定距离并且第二芯片与底部基座电连接。
粘合材料可以是环氧树脂、氰酸酯以及聚酰亚胺。粘合材料优选是搭扣固化材料。预定的间距足以保护第一芯片和底部基座之间的电连接不受第二芯片与第一芯片连接的破坏。每个粘合材料层的厚度在大约1.5密耳-大约2.0密耳之间，而预定的间距至少是大约5密耳。
第一芯片利用第一导线与底部基座电连接。第一导线可与第一芯片外围区上的多个第一芯片结合片引线接合并与底部基座的顶面引线接合。在备选的实施方式中，层叠芯片封装包括在第一芯片外围区的第一芯片结合片上形成的多个第一突耳。第一导线从底部基座的顶面与第一芯片上的第一突耳反向接合，使得在第一突耳上形成多个针脚连接。层叠芯片封装包括在针脚连接上形成的多个第二突耳。第一和第二突耳形成了环绕第一芯片外围区的壁以包含粘合材料。
第二芯片利用第二导线与底部基座电连接，第二导线与第二芯片的上表面上的多个第二芯片结合片引线接合并与底部基座的顶面引线接合。第一和第二芯片、第一和第二导线、以及底部基座的至少一部分利用密封剂例如树脂被封装。
第一和第二芯片可具有基本上相同的长度和基本上相同的宽度。在备选的实施方式中，第二芯片可比第一芯片更大。
从以上描述中清楚可见，本发明通过从封装过程中消除采用空白硅芯片或特殊制造的带而提供了一种制造层叠芯片封装廉价的方法。由于不需要有连接空白硅芯片或特殊制造的带的步骤，因此还降低了过程准备时间。
已经为了示意和描述提出了本发明优选实施方式的说明，但这一说明并不是要详尽或将本发明限制在所公开的形式。本领域的技术人员将会认识到，在不脱离本发明的宽泛的发明构思的前提下可以对以上所述的实施方式做出改变。例如，本发明并不局限于具有两个层叠芯片的封装，而是可以被应用在具有多个层叠芯片的封装。此外，本发明并不局限于任何单个引线接合技术或具体的封装。也就是说，本发明可被应用于所有的引线接合的封装类型，包括但不局限于BGA、QFN、QFP、PLCC、CUEBGA、TBGA、以及TSOP。另外，芯片尺寸和步骤多少可以变化以适应所需的封装设计。因此，可以理解到本发明并不局限于所公开的具体实施方式，而是覆盖了在由附加权利要求限定的本发明的精神和范围内的所有变化。

Claims (20)

1.一种制造层叠芯片封装的方法，其包括：
将第一集成电路(IC)芯片连接在底部基座上；
使第一芯片与底部基座电连接；
在第一芯片上形成多个依次相叠的粘合材料层；
利用粘合材料将第二芯片连接在第一芯片上，其中，所述依次相叠的粘合材料层在第一芯片和第二芯片之间保持预定的间距；以及
使第二芯片与底部基座电连接。
2.如权利要求1所述的制造层叠芯片封装的方法，其特征在于，通过将粘合材料以多次施加的方式分配在第一芯片上而形成依次相叠的粘合材料层。
3.如权利要求2所述的制造层叠芯片封装的方法，其特征在于，当在前的层基本上固化时对用于每个后续层的粘合材料进行分配。
4.如权利要求3所述的制造层叠芯片封装的方法，其特征在于，所述粘合材料是环氧树脂、氰酸酯以及聚酰亚胺中的一种。
5.如权利要求4所述的制造层叠芯片封装的方法，其特征在于，所述粘合材料包括搭扣固化材料。
6.如权利要求1所述的制造层叠芯片封装的方法，其特征在于，预定的间距足以保护第一芯片和底部基座之间的电连接不受第二芯片与第一芯片连接的破坏。
7.如权利要求6所述的制造层叠芯片封装的方法，其特征在于，预定的间距至少是大约5密耳。
8.如权利要求7所述的制造层叠芯片封装的方法，其特征在于，每个粘合材料层的厚度在大约1.5密耳-大约2.0密耳之间。
9.如权利要求1所述的制造层叠芯片封装的方法，其特征在于，所述第一芯片利用第一导线与底部基座电连接。
10.如权利要求9所述的制造层叠芯片封装的方法，其特征在于，所述第一导线与第一芯片上表面的外围区上的多个第一芯片结合片引线结合并与底部基座的顶面引线结合。
11.如权利要求9所述的制造层叠芯片封装的方法，其特征在于，还包括在第一芯片上表面的外围区的各个第一芯片结合片上形成多个第一突耳的步骤。
12.如权利要求11所述的制造层叠芯片封装的方法，其特征在于，所述第一导线从底部基座的顶面与第一芯片结合片上的第一突耳反向接合，使得在第一突耳上形成多个针脚连接。
13.如权利要求12所述的制造层叠芯片封装的方法，其特征在于，还包括在针脚连接上形成第二突耳的步骤。
14.如权利要求13所述的制造层叠芯片封装的方法，其特征在于，第一和第二突耳形成了环绕第一芯片的外围区的壁以包含粘合材料。
15.如权利要求9所述的制造层叠芯片封装的方法，其特征在于，第二芯片利用第二导线与底部基座电连接，第二导线与第二芯片上表面上的多个第二芯片结合片引线接合并与底部基座的顶面引线接合。
16.如权利要求15所述的制造层叠芯片封装的方法，其特征在于，还包括封装第一和第二芯片、第一和第二导线、以及底部基座的至少一部分的步骤。
17.一种制造层叠芯片封装的方法，其包括：
将第一IC芯片连接在底部基座上，第一芯片具有下表面和上表面，上表面具有中心区和外围区，外围区包括多个第一芯片结合片，第一芯片的下表面连接在底部基座的顶面上；
第一芯片通过将第一导线与第一芯片结合片引线接合并与底部基座顶面上的第一对应结合片引线接合而与底部基座电连接；
在第一芯片上表面的中心区上形成多个依次相叠的粘合材料层；
通过依次相叠的粘合材料层将第二芯片的下表面连接在第一芯片的上表面上，其中第二芯片包括位于其上表面上的多个第二芯片结合片，并且依次相叠的粘合材料层保持在第一芯片和第二芯片之间预定的间距；
通过将第二导线与第二芯片结合片引线接合并与底部基座上的第二对应结合片引线接合而使第二芯片与底部基座电连接；以及
对第一和第二芯片、第一和第二导线、以及底部基座的至少一部分进行封装。
18.如权利要求17所述的制造层叠芯片封装的方法，其特征在于，还包括以下步骤：
在各个第一芯片结合片上形成多个第一突耳，第一导线从底部基座顶面上的第一对应结合片反向连接在第一芯片结合片上的第一突耳上，使得在第一突耳上形成多个针脚连接；以及
在针脚连接上形成第二突耳，第一和第二突耳形成了环绕第一芯片外围区的壁以包含粘合层。
19.一种制造层叠芯片封装的方法，其包括：
将第一IC芯片连接在底部基座上，第一芯片具有下表面和上表面，上表面具有中心区和外围区，外围区包括多个第一芯片结合片，第一芯片的下表面连接在底部基座的顶面上；
在各个第一芯片结合片上形成多个第一突耳；
通过将来自底部基座顶面上第一结合片的第一导线反向连接在第一芯片结合片上的第一突耳上而使第一芯片与底部基座电连接，使得在第一突耳上形成多个针脚连接；
在针脚连接上形成多个第二突耳；
在第一芯片上表面的中心区上形成多个依次相叠的粘合材料层，第一和第二突耳形成了环绕第一芯片外围区的壁以包含粘合材料；
利用粘合材料将第二芯片的下表面连接在第一芯片的上表面上，第二芯片具有位于其上表面上的多个第二芯片结合片，依次相叠的粘合材料层保持在第一芯片和第二芯片之间预定的间距；
通过将第二导线与第二芯片结合片引线接合并与底部基座顶面上的对应第二结合片引线接合而使第二芯片与底部基座电连接；以及
对第一和第二芯片、第一和第二导线、以及底部基座的至少一部分进行封装。
20.如权利要求19所述的制造层叠芯片封装的方法，其特征在于，通过将粘合材料以多次施加的方式分配在第一芯片上而形成依次相叠的粘合材料层，并且当在前的层基本上固化时对用于每个后续层的粘合材料进行分配。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7750449B2 (en) * 2007-03-13 2010-07-06 Micron Technology, Inc. Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components
TWI326914B (en) * 2007-03-13 2010-07-01 Siliconware Precision Industries Co Ltd Multi-chip stack structure and fabrication method thereof
KR20100016327A (ko) * 2007-05-08 2010-02-12 오컴 포트폴리오 엘엘씨 무솔더 전자 어셈블리 및 그 제조 방법
EP2220678A4 (en) * 2007-05-29 2012-04-25 Occam Portfolio Llc LOTFREIE ELECTRONIC ARRANGEMENTS AND MANUFACTURING METHOD THEREFOR
JP5205867B2 (ja) * 2007-08-27 2013-06-05 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP5665511B2 (ja) * 2010-12-10 2015-02-04 株式会社東芝 半導体装置の製造方法、製造プログラム、および製造装置
TWI608564B (zh) 2013-12-10 2017-12-11 艾馬克科技公司 半導體裝置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5770706A (en) * 1995-06-07 1998-06-23 National Starch And Chemical Investment Holding Corporation Snap-cure epoxy adhesives
JP4251421B2 (ja) * 2000-01-13 2009-04-08 新光電気工業株式会社 半導体装置の製造方法
TW465064B (en) * 2000-12-22 2001-11-21 Advanced Semiconductor Eng Bonding process and the structure thereof
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
TW536764B (en) * 2002-04-30 2003-06-11 Walsin Advanced Electronics Method for multi-chip package and structure thereof
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US6861288B2 (en) * 2003-01-23 2005-03-01 St Assembly Test Services, Ltd. Stacked semiconductor packages and method for the fabrication thereof
US7166924B2 (en) * 2004-08-17 2007-01-23 Intel Corporation Electronic packages with dice landed on wire bonds
JP4964780B2 (ja) * 2004-11-12 2012-07-04 スタッツ・チップパック・インコーポレイテッド ワイヤボンド相互接続、半導体パッケージ、および、ワイヤボンド相互接続の形成方法
US8278751B2 (en) * 2005-02-08 2012-10-02 Micron Technology, Inc. Methods of adhering microfeature workpieces, including a chip, to a support member

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