DE102004004026A1 - Circuitry for data storage, especially dynamic random access memory (DRAM) with flexibly arranged circuit chips for memory cell units and data transmission units, without faults in units causing total breakdown of entire circuitry - Google Patents

Abstract

Circuitry comprises memory cell unit (101), e.g. DRAM, with memory cell field for storage of electric charges, data transmission unit (102) for data transmission between memory cell unit and external circuit units. Connector units (104a-n) provide electric link for external circuit units to data transmission unit. Memory cell unit and data transmission unit are arranged on separate chips, with their electric connection escured by coupling unit (103).

Description

The The present invention generally relates to a circuit arrangement for data storage, and more particularly relates to a dynamic random access memory with flexibly arranged circuit chips for memory cell units and Data transmission units.

Especially The present invention relates to a circuit arrangement for Data storage with a memory cell unit comprising a memory cell array having memory cells in which electrical charge storable is; a data transmission unit for data transmission between the memory cell unit and external circuit units; and terminal units for electrically connecting the external circuit units the data transmission unit.

circuitry for data storage, in particular DRAM memory units (DRAM: Dynamic random access memory, dynamic random access memory) in different embodiments manufactured, wherein the individual embodiments substantially by distinguish their operating behavior.

Around To save data in the dynamic read-write memory and / or Data from these read out are usually on the circuit chip the data storage units arranged in the storage unit are used, which differ by their data rate, i. for example a simple data rate (SDR: Single Data Rate) or a double Data rate (DDR: Double Data Rate) such as DDR, DDR2, DDR3.

The for data transmission used data transmission units are also called "interface units or interfaces " and indicate the data transfer rate, such as: SDR SDRAM, DDR SDRAM and DDR2 SDRAM. The memory cell units are essentially of the same size Memory cell array labeled, i. the size of the memory cell array is for example, 128 MB, 256 MB, 512 MB, 1 GB, 4 GB, etc. To the individual To be able to differentiate memory cell units in terms of circuitry is for each memory cell unit at least one data transmission unit required at the periphery of the memory cell unit forming circuit chip is arranged.

One significant disadvantage of conventional circuit arrangements for data storage, comprising memory cell units comprising include a memory cell array with memory cells, is that if one of the circuit parts, i. the memory cell unit or the data transmission unit, is defective, then the entire circuitry is no longer used can be.

conventional Circuit arrangements for data storage have the memory cell unit and the data transmission unit (the "interface") together on one single circuit chip arranged on. The common arrangement from storage cell unit and data transfer unit for provision a data storage circuit is further impractical in that that in the development of the circuit chip due to long development times high costs arise. This is touching therefore, that the memory cell unit and the data transmission unit must always be developed as a common circuit chip.

One in the data transmission unit occurring error leads to a total failure of the circuit chip, since an error in the Data transmission unit usually can not be eliminated. An error in the memory cell unit may be under circumstances using redundant memory cells of the memory cell array be eliminated. This method drive to repair faulty memory cells however, in the memory cell array is not for a larger number of errors more usable, i. the entire memory cell unit (the DRAM) becomes inappropriate way unusable.

The common arrangement of the memory cell unit and the data transmission unit on a common circuit chip further leads to the disadvantage that for the production of the memory cell unit and the data transmission unit always the same manufacturing technology as CMOS, bipolar, BiCMOS etc. for both circuit units must be used. Inappropriately This is a compromise in the production of both circuit units required, thereby reducing mutual operational behavior results.

Farther it is inappropriate that for different Sizes of Memory cell fields in the memory cell unit different Data transmission units, for example, in terms of bit width, are required.

It is therefore an object of the present invention to provide an improved yield in a manufacturing of a data storage circuit, wherein errors which occur in the Memory cell unit and / or the data transmission unit occur, do not lead to a total failure of the entire circuit.

These The object is achieved by a Circuit arrangement solved with the features of claim 1.

Further Embodiments of the invention will become apparent from the dependent claims.

One essential idea of the invention is the circuit arrangement to divide for data storage such that the memory cell unit and the Datenübertragungsein unit are arranged on separate circuit chips, wherein a connection unit for electrically connecting the memory cell unit to the data transmission unit is provided.

By Such a division of memory cell unit and data transmission unit a data storage arrangement results in the further advantage that the two circuit units are tested separately can.

Farther it is advantageous that for the preparation of the memory cell unit and for the production of the data transmission unit different technologies, such as CMOS (Complementary Metal Oxides silicon), bipolar, BiCMOS (bipolar CMOS), etc., respectively can be. For example It is advantageous to have a DRAM technology for the memory cell array and a logic technology for the data transmission unit use. The circuit arrangement according to the invention allows appropriate way such use of different technologies for training the entire circuit for data storage.

The inventive circuit arrangement also offers the advantage of being flexible to different market needs to react. Thus, the circuit arrangement according to the invention provides a adaptability an unchanged memory cell unit by means of modified data transmission units to different external circuit designs. Consequently There is the advantage that the memory cell unit to be produced consuming independently manufactured by the market needs can be.

One A significant advantage of the present invention is that the circuit chip yield on a wafer is increased. If one of the two Circuit units, i. either the memory cell unit or the data transmission unit, defective is, only the defective scarf processing unit must be replaced, while the other circuit unit can continue to be used.

It is appropriate, one Connection unit between the two circuit units, i. the memory cell unit and the data transmission unit to be interpreted in such a way that these are independent of the size of the memory cell array the memory cell unit is. It is expedient, the Data transfer unit to a maximum size of the memory cell array the memory cell unit interpreted. This gives the advantage that for different, possibly in the future to be developed memory cell units always the same data transmission unit a desired one Platform (SDR, DDR, DDR2, DDR3, etc.) can be used.

• a) eine Speicherzelleneinheit, die ein Speicherzellenfeld mit Speicherzellen aufweist, in welchen elektrische Ladung speicherbar ist;
• b) eine Datenübertragungseinheit zur Datenübertragung zwischen der Speicherzelleneinheit und externen Schaltungseinheiten; und
• c) Anschlusseinheiten zum elektrischen Anschluss der externen Schaltungseinheiten an die Datenübertragungseinheit, wobei
• d) die Speicherzelleneinheit und die Datenübertragungseinheit auf separaten Schaltungschips angeordnet sind, wobei
• e) eine Verbindungseinheit zur elektrischen Verbindung der Speicherzelleneinheit mit der Datenübertragungseinheit bereitgestellt ist.

The data storage circuit according to the invention essentially comprises:

• a) a memory cell unit having a memory cell array with memory cells in which electrical charge can be stored;
• b) a data transmission unit for data transmission between the memory cell unit and external circuit units; and
• c) connection units for electrically connecting the external circuit units to the data transmission unit, wherein
• d) the memory cell unit and the data transmission unit are arranged on separate circuit chips, wherein
• e) a connection unit for electrical connection of the memory cell unit is provided with the data transmission unit.

In the dependent claims find advantageous developments and improvements of respective subject of the invention.

According to one preferred embodiment of the present invention is the memory cell unit as a dynamic random access memory (DRAM) is formed.

According to one Another preferred embodiment of the present invention the data transmission unit for easy Data rate or double data rate designed.

According to one more further preferred embodiment of the present invention has the memory cell array of the memory cell unit has a memory depth 128 MB, 256 MB, 512 MB or 1 GB.

According to yet another preferred development of the present invention, the memory cell unit and the data transmission unit are common in a single multiple chip arranged housing.

According to one more Another preferred embodiment of the present invention the data transmission unit in a data transmission width to a maximum size of the memory cell array adapted to the memory cell unit.

According to one more Another preferred embodiment of the present invention at least two data transmission units combined with the memory cell unit in the multi-chip package, such that advantageously a redundancy of the data transmission units provided. Furthermore, it is expedient that data transmission units a different bit width provided in a single multi-chip package can be.

According to one more Another preferred embodiment of the present invention at least two data transmission units combined with at least two memory cell units in the multi-chip package. In this way there is the advantage that different circuit arrangements can be specified flexibly for data storage.

According to one more Another preferred embodiment of the present invention the at least one memory cell unit and the at least one Data transfer unit designed using different technologies (CMOS, bipolar, BiC-MOS).

According to one more Another preferred embodiment of the present invention the at least one memory cell unit optionally with different Data transmission units operated.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

In show the drawings:

1 a schematic view of a multi-chip package containing a memory cell unit and a data transmission unit connected by a connection unit, according to a preferred embodiment of the present invention; and

2 a schematic block diagram illustrating the arrangement of the essential circuit components according to a preferred embodiment of the present invention.

In the same reference numerals designate the same or functionally identical Components or steps.

1 shows a schematic arrangement of a memory cell unit 101 and a data transmission unit 102 in a common multiple chip package 100 , For connecting external circuit units to the data transmission unit 102 are connection units 104a . 104b , ..., 104n provided, wherein a connection between the terminal units 104a - 104n with the data transmission unit 102 via connecting cables 201 . 201b , ..., 201n is provided. The connecting cables 201a-201n For example, they can be made as bonding wires.

For electrical connection of the memory cell unit 101 with the data transmission unit 102 serves a connection unit 103 , The connection of the memory cell unit 101 and the data transmission unit 102 over the connection unit 103 can be provided, for example, in a multi-chip package type FBGA MultiDie. Methods are known to the person skilled in the art, such as different circuit units, for example different memory cell units and different data transmission units in a multiple chip housing 100 can be accommodated, so that such a method is not described here.

The memory cell unit 101 can according to the invention have different memory depths, such as 128 MB DDR, 256 MB DDR, 512 MB DDR and 1 GB DDR (DDR: Double Date Rate, double data rate). Since according to the invention both the memory cell unit 101 as well as the data transmission unit 102 For example, if an error occurs in one of the two units, it may be advantageous to replace the data transmission unit 102 for a maximum size of a memory cell array of the memory cell unit 101 interpreted.

The data transmission units used according to the invention 102 differ essentially by different addressing areas. Such different addressing ranges may be defined by a number of the addressing lines.

2 illustrates in a schematic block diagram how the essential circuit components for driving the memory cell unit 101 and connecting the memory cell unit 101 with the data transmission unit 102 interact.

As in 2 is a memory cell unit 101 with a data transmission unit 102 via a connection unit 103 connected. The data transmission unit 102 is via connection lines 201a-201n as described above with reference to 1 explained, with a connection unit 104 connected via which external circuit units to the memory cell unit 101 can be connected. The data transmission unit 102 is shown as a universal interface chip over which all circuit chips of memory cell units of a size of a memory cell array 105 from 128 MB to 1 GB can be addressed.

It should be noted that the schematic block diagram in FIG 2 only illustrates the essential circuit blocks required for understanding the invention. The data transmission unit 102 thus essentially comprises a read logic unit 202 and a write logic unit 203 on that over the connection unit 103 with a memory cell array 105 the memory cell unit 101 are connected. When reading out data stored in the memory cell array 105 the memory cell unit 101 are stored, these are first through the connection unit 103 to the reading logic unit 202 and from this via connecting cables 201 - 201n to the connection unit 104 which then provides a connection to external circuit units. When writing data to the memory cell array 105 the memory cell unit 101 Data from external scarf processing units (not shown) via the connection unit 104 into the writing logic unit 203 entered, from which the data about the connection unit 103 to the memory cell array 105 the memory cell unit 101 to get redirected.

For addressing the individual, usually in matrix form arranged memory cells of the memory cell array 105 the memory cell unit 101 contains the memory cell unit 101 a row address decoder 106 and a column address decoder 107 , In 2 is an example of a memory cell unit 101 with a memory depth of 128MB, with a wordline decoder 108 with an input bit width of 14 only twelve output lines for the 128 MB memory depth of the memory cell array 105 must provide. Similarly, a bitline decoder provides 109 eleven lines for the memory depth of 128 MB of the memory cell array 105 the memory cell unit 101 ready.

The wordline decoder 108 is 12-bit wide connected to the row address decoder, while the bit line decoder 109 11-bit wide connected to the column address decoder. A control logic unit 111 is on the one hand both with the word line decoder 108 (14-bit wide) and the bitline decoder 109 (12-bit wide), as well as an address register 110 in which addresses can be stored, which are 14-bit-wide predetermined by an external circuit unit.

The circuit arrangement according to the invention for data storage now advantageously allows the individual circuit chips, ie the memory cell unit and the data transmission unit, to be tested individually on the silicon level. Through the use of a multi-chip housing 100 in which the memory cell unit 101 and the data transmission unit 102 integrated, external circuitry is provided with an original functionality of the data storage device.

In the event of errors in one of the two circuit units, memory cell unit 101 or data transmission unit 102 , It is easily possible to replace the defective unit, whereby the other unit can be used on. This results in significant economic benefits, ie, a cost reduction in the production of circuit arrangements for data storage is achieved.

Even though the present invention above based on preferred embodiments It is not limited to this, but in many ways modifiable.

Also the invention is not limited to the aforementioned applications limited.

In the same reference numerals designate the same or functionally identical Components or steps.

100

Multi-chip package

101

Memory cell unit

102

Data transfer unit

103

connecting unit

104

connection unit

104a,

104b,

..., 104n

105

Memory cell array

106

Row address decoder

107

Column address decoder

108

Word line decoder

109

bit line decoder

110

address register

111

Control logic unit

201a,

connecting cable

201b,

..., 201n

202

Read logic unit

203

Write logic unit

Claims (10)

Circuit arrangement for data storage, comprising: a) a memory cell unit ( 101 ), which is a memory cell array ( 105 ) having memory cells in which electrical charge can be stored; b) a data transmission unit ( 102 ) for data transmission between the memory cell unit ( 101 ) and external circuit units; and c) connection units ( 104a-104n ) for the electrical connection of the external circuit units to the data transmission unit ( 102 ); characterized in that d) the memory cell unit ( 101 ) and the data transmission unit ( 102 ) are arranged on separate circuit chips, wherein e) a connection unit ( 103 ) for the electrical connection of the memory cell unit ( 101 ) with the data transmission unit ( 102 ). Circuit arrangement according to Claim 1, characterized in that the memory cell unit ( 101 ) is designed as a dynamic random access memory (DRAM). Circuit arrangement according to Claim 1, characterized in that the data transmission unit ( 102 ) is designed for simple data rate (SDR) or double data rate (DDR). Circuit arrangement according to Claim 1 or 2, characterized in that the memory cell array ( 105 ) of the memory cell unit ( 101 ) has a memory depth of 128 megabytes (MB), 256 megabytes (MB), 512 megabytes (MB), or 1 gigabyte (GB). Circuit arrangement according to Claim 1, characterized in that the memory cell unit ( 101 ) and the data transmission unit ( 102 ) together in a multi-chip package ( 100 ) are arranged. Circuit arrangement according to Claim 1, characterized in that the data transmission unit ( 102 ) in a data transmission width to a maximum size of the memory cell array ( 105 ) of the memory cell unit ( 101 ) is adjusted. Circuit arrangement according to Claim 5, characterized in that at least two data transmission units ( 102 ) with the memory cell unit ( 101 ) in the multi-chip package ( 100 ) are combined. Circuit arrangement according to Claim 5, characterized in that at least two data transmission units ( 102 ) with at least two memory cell units ( 101 ) are combined in the multi-chip package. Circuit arrangement according to one or more of the preceding claims, characterized in that the at least one memory cell unit ( 101 ) and the at least one data transmission unit ( 102 ) are designed by means of different technologies (CMOS, bipolar, BiCMOS). Circuit arrangement according to Claim 1, characterized in that the at least one memory cell unit ( 101 ) optionally with different data transmission units ( 102 ) is operable.