DE102004049249B4 - Electronics module, wafer product and manufacturing process - Google Patents
Electronics module, wafer product and manufacturing process Download PDFInfo
- Publication number
- DE102004049249B4 DE102004049249B4 DE102004049249A DE102004049249A DE102004049249B4 DE 102004049249 B4 DE102004049249 B4 DE 102004049249B4 DE 102004049249 A DE102004049249 A DE 102004049249A DE 102004049249 A DE102004049249 A DE 102004049249A DE 102004049249 B4 DE102004049249 B4 DE 102004049249B4
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- Prior art keywords
- integrated circuit
- redistribution structure
- substrate
- module according
- circuit dies
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- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Elektronikmodul mit einem monolithischen mikroelektronischen Substrat (401), das mehrere integrierte Schaltkreiseinzelchips (110a bis 110h) und eine Umverteilungsstruktur (510) beinhaltet, die einen mit wenigstens einem der integrierten Schaltkreischips (110a bis 110h) gekoppelten, an einer Kante des monolithischen Substrats angeordneten, externen Katenverbinderkontakt (230a) bereitstellt und sich über die integrierten Schaltkreiseinzelchips hinweg erstreckt.electronic module with a monolithic microelectronic substrate (401), the a plurality of integrated circuit dies (110a to 110h) and a redistribution structure (510), one with at least one of the integrated ones Circuit chips (110a to 110h) coupled to one edge of the arranged monolithic substrate, external Katenverbinderkontakt (230a) provides and moves over extends the integrated circuit dies.
Description
Die Erfindung bezieht sich auf ein Elektronikmodul, ein Waferprodukt und auf ein zugehöriges Herstellungsverfahren.The The invention relates to an electronic module, a wafer product and an associated manufacturing process.
Ein typisches herkömmliches Elektronikmodul, wie ein Speichermodul, kann eine Mehrzahl von gepackten integrierten Schaltkreisbauelementen beinhalten, die an einer Leiterplatte (PCB) angebracht sind. Die integrierten Schaltkreisbauelemente können in verschiedenen Formen gepackt sein, wie einer herkömmlichen Durchkontaktlochpackung oder Oberflächenmontagepackung (SMT-Packung), die sich für manuelle und/oder Schwall-Löttechniken eignen, ebenso wie einer Packung mit Chipabmessung (Chip-Scale-Packung (CSP)) und einer Chip-Scale-Packung auf Waferniveau bzw. Waferebene (Waferlevel-CSP (WLCSP)), die für eine PCB-Montage unter Verwendung von Lotkugeltechniken konfiguriert sind.One typical conventional Electronic module, such as a memory module, can be a plurality of packed integrated circuit components that on a circuit board (PCB) are mounted. The integrated circuit devices can be used in be packed in different shapes, like a conventional one Through-hole or surface mount package (SMT package), for themselves manual and / or wave soldering techniques as well as a chip-sized package (chip-scale package (CSP)) and a chip-scale package at the wafer level or wafer level (Wafer Level CSP (WLCSP)) required for PCB mounting Use of soldering techniques are configured.
Es
zeigt sich, dass sich herkömmliche
Bauelementpackungs- und Bauelementzwischenverbindungstechnologien
einer Grenze minimaler Merkmalsabmessung nähern, welche die Möglichkeit
des Designers zu einer weiteren Reduzierung der Abmessung von Modulen
beschränkt.
Außerdem
können
Techniken, die gelötete
Verbindungen verwenden, Zuverlässigkeits-
und Umweltprobleme aufweisen. Für
das in den
Die
Offenlegungsschrift
Die
Patentschrift
In
der Offenlegungsschrift
Die
Offenlegungsschrift
Der Erfindung liegt als technisches Problem die Bereitstellung eines Elektronikmoduls, eines Waferproduktes sowie eines zugehörigen Herstellungsverfahrens zugrunde, mit denen sich die oben genannten Schwierigkeiten des Standes der Technik wenigstens teilweise vermeiden lassen.Of the Invention is the technical problem of providing a Electronic module, a wafer product and an associated manufacturing process underlying the difficulties mentioned above At least partially avoided prior art.
Die Erfindung löst dieses Problem durch die Bereitstellung eines Elektronikmoduls mit den Merkmalen des Anspruchs 1, eines Waferproduktes mit den Merkmalen des Anspruchs 17 sowie eines Elektronikmodul-Herstellungsverfahrens mit den Merkmalen des Anspruchs 20.The Invention solves this problem by providing an electronic module with the features of claim 1, a wafer product with the features of claim 17 and an electronic module manufacturing method with the features of claim 20.
Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben.advantageous Further developments of the invention are specified in the subclaims.
Vorteilhafte, nachfolgend beschriebene Ausführungsformen der Erfindung sowie das zu deren besserem Verständnis oben erläuterte herkömmliche Ausführungsbeispiel sind in den Zeichnungen dargestellt. Hierbei zeigen:Advantageous, Embodiments described below of the invention and the conventional embodiment explained above for better understanding thereof are shown in the drawings. Hereby show:
Nachstehend wird die Erfindung detaillierter unter Bezugnahme auf die begleitenden Zeichnungen beschrieben, in denen exemplarische Ausführungsformen der Erfindung gezeigt sind. In den Zeichnungen ist die Dicke von Schichten und Bereichen zwecks Klarheit übertrieben dargestellt. Es versteht sich, dass wenn ein Element, wie eine Schicht, ein Bereich oder Substrat als "auf" einem anderen Element liegend bezeichnet wird, es direkt auf dem anderen Element liegen kann oder auch zwischenliegende Elemente vorhanden sein können. Des Weiteren können relative Ausdrücke, wie "unterhalb", hierin verwendet werden, um Beziehungen zwischen Elementen zu beschreiben, wie sie in den Zeichnungen dargestellt sind. Es versteht sich, dass relative Ausdrücke dieser Art dazu gedacht sind, auch andere als die in den Zeichnungen gezeigte Orientierung des Bauelements zu umfassen. Wenn das Bauelement in den Zeichnungen zum Beispiel umgedreht ist, dann sind Elemente, die als "unterhalb" von anderen Elementen beschrieben sind, "über" den anderen Elementen orientiert. Es versteht sich, dass Ausdrücke wie "erste", "zweite" etc. hierin lediglich verwendet sind, um verschiedene Bereiche, Schichten und/oder Abschnitte voneinander zu unterscheiden. Gleiche Bezugszeichen bezeichnen durchgehend gleiche Elemente.below The invention will be explained in more detail with reference to the accompanying drawings Drawings are described in which exemplary embodiments of the invention are shown. In the drawings, the thickness of Layers and areas exaggerated for clarity. It It is understood that when an element, such as a layer, an area or substrate as "on" another element lying lying directly on the other element or intervening elements may be present. Of Further can relative expressions, as "below", used herein be used to describe relationships between elements, like them are shown in the drawings. It is understood that relative expressions of this Are meant to be, other than those shown in the drawings To include orientation of the device. If the device is in For example, if the drawings are turned over, then there are elements as "below" other elements are described "above" the other elements oriented. It should be understood that terms such as "first," "second," etc. are merely herein are used to different areas, layers and / or sections to distinguish from each other. The same reference numerals designate the same throughout Elements.
Die
Gemäß weiteren
Ausführungsformen
der Erfindung kann ein monolithisches Substrat mit einem oder mehreren
integralen Verbinderkontakten, wie durch die
Gemäß weiteren
Ausführungsformen
der Erfindung können
elektronische Bauelemente, wie Widerstände, Kondensatoren und/oder
Induktivitäten,
in eine Umverteilungsstruktur eines monolithischen Substrats eingebaut
sein, wie jene in den
Nunmehr
bezugnehmend auf
Der
jeweilige Einzelchip
Die
strukturierten leitfähigen
Schichten der Umverteilungsstruktur
Weiterhin
bezugnehmend auf die
Eine
Unterseite des Wafers
Die
zweite und die dritte Schutzschicht
Gemäß Ausführungsformen der Erfindung kann eine weitere Reduktion der Abmessung von elektronischen Modulen durch Bilden eines monolithischen mikroelektronischen Substrats erzielt werden, das einen oder mehrere integrierte Schaltkreiseinzelchips gleichen Typs oder unterschiedlicher Typen und eine Umverteilungsstruktur darauf beinhaltet, die einen Verbinderkontakt umfasst, der mit dem einen oder den mehreren integrierten Schaltkreiseinzelchips gekoppelt ist. Da die Umverteilungsstruktur über dem Einzelchip ausgebildet sein kann, kann das Oberflächengebiet, das zur Zwischenverbindung der Einzelchips und zur Bereitstellung eines Kantenverbinders benötigt wird, signifikant reduziert werden. Außerdem kann ein Modul hergestellt werden, ohne die Verwendung von gelöteten Verbindungen zu erfordern, oder mit einer reduzierten Anzahl von gelöteten Verbindungen.According to embodiments The invention may further reduce the dimension of electronic Modules by forming a monolithic microelectronic substrate achieved, the one or more integrated circuit chips same type or different types and a redistribution structure on it, which includes a connector contact associated with the coupled to one or more integrated circuit dies is. Because the redistribution structure is formed over the single chip can be the surface area, for the interconnection of the individual chips and for the provision an edge connector needed will be significantly reduced. In addition, a module can be made without requiring the use of soldered connections, or with a reduced number of soldered connections.
Claims (28)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0088055 | 2003-12-05 | ||
KR1020030088055A KR100609011B1 (en) | 2003-12-05 | 2003-12-05 | Wafer level module and fabricating method thereof |
US10/824,111 US7307340B2 (en) | 2003-12-05 | 2004-04-14 | Wafer-level electronic modules with integral connector contacts |
US10/824,111 | 2004-04-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102004049249A1 DE102004049249A1 (en) | 2005-07-07 |
DE102004049249B4 true DE102004049249B4 (en) | 2008-08-28 |
Family
ID=34656330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102004049249A Expired - Fee Related DE102004049249B4 (en) | 2003-12-05 | 2004-09-30 | Electronics module, wafer product and manufacturing process |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2005175471A (en) |
CN (1) | CN1624919A (en) |
DE (1) | DE102004049249B4 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102577265B1 (en) * | 2018-12-06 | 2023-09-11 | 삼성전자주식회사 | Semiconductor package |
GB2597179B (en) * | 2019-04-04 | 2023-07-05 | Rockley Photonics Ltd | Optical engine |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4685998A (en) * | 1984-03-22 | 1987-08-11 | Thomson Components - Mostek Corp. | Process of forming integrated circuits with contact pads in a standard array |
US5910640A (en) * | 1993-07-10 | 1999-06-08 | Micron Technology, Inc. | Electrical contact assembly for use in a multi-die encapsulation device |
US6210993B1 (en) * | 1998-05-20 | 2001-04-03 | Micron Technology, Inc. | High density semiconductor package and method of fabrication |
US20020031858A1 (en) * | 1998-09-01 | 2002-03-14 | Larry Kinsman | Semiconductor device comprising a socket and method for forming same |
US20020094602A1 (en) * | 2001-01-17 | 2002-07-18 | Tzong-Dar Her | DCA memory module and a fabrication method thereof |
US20030122246A1 (en) * | 2001-12-31 | 2003-07-03 | Mou-Shiung Lin | Integrated chip package structure using silicon substrate and method of manufacturing the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11330256A (en) * | 1998-05-19 | 1999-11-30 | Tif:Kk | Semiconductor device and its manufacture |
JP3465617B2 (en) * | 1999-02-15 | 2003-11-10 | カシオ計算機株式会社 | Semiconductor device |
JP2001053193A (en) * | 1999-08-10 | 2001-02-23 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
JP2001223319A (en) * | 1999-11-30 | 2001-08-17 | Nissan Motor Co Ltd | Semiconductor mounting structure and semiconductor chip set used therefor |
JP4356196B2 (en) * | 2000-06-02 | 2009-11-04 | 富士通株式会社 | Semiconductor device assembly |
-
2004
- 2004-09-15 CN CNA2004100785840A patent/CN1624919A/en active Pending
- 2004-09-30 DE DE102004049249A patent/DE102004049249B4/en not_active Expired - Fee Related
- 2004-12-02 JP JP2004350389A patent/JP2005175471A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4685998A (en) * | 1984-03-22 | 1987-08-11 | Thomson Components - Mostek Corp. | Process of forming integrated circuits with contact pads in a standard array |
US5910640A (en) * | 1993-07-10 | 1999-06-08 | Micron Technology, Inc. | Electrical contact assembly for use in a multi-die encapsulation device |
US6210993B1 (en) * | 1998-05-20 | 2001-04-03 | Micron Technology, Inc. | High density semiconductor package and method of fabrication |
US20020031858A1 (en) * | 1998-09-01 | 2002-03-14 | Larry Kinsman | Semiconductor device comprising a socket and method for forming same |
US20020094602A1 (en) * | 2001-01-17 | 2002-07-18 | Tzong-Dar Her | DCA memory module and a fabrication method thereof |
US20030122246A1 (en) * | 2001-12-31 | 2003-07-03 | Mou-Shiung Lin | Integrated chip package structure using silicon substrate and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
DE102004049249A1 (en) | 2005-07-07 |
JP2005175471A (en) | 2005-06-30 |
CN1624919A (en) | 2005-06-08 |
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