DE102005039786A1 - Dual-die ball grid array (DDBGA) has length equalization of wiring between upper and lower dies - Google Patents

Dual-die ball grid array (DDBGA) has length equalization of wiring between upper and lower dies Download PDF

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DE102005039786A1
DE102005039786A1 DE102005039786A DE102005039786A DE102005039786A1 DE 102005039786 A1 DE102005039786 A1 DE 102005039786A1 DE 102005039786 A DE102005039786 A DE 102005039786A DE 102005039786 A DE102005039786 A DE 102005039786A DE 102005039786 A1 DE102005039786 A1 DE 102005039786A1
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substrate
dies
ball
die
pads
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Jochen Dipl.-Ing. Thomas
Wolfgang Hetzel
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

Dual-die ball grid array (DDBGA) (30) comprises copper wiring planes on a multiplanar substrate (33) with stacked dies with opposite ball pads to receive solder balls (37) that are electrically connected to bond pads on the dies. The electrical leads to connect the lower dies (35) to the ball pads of the ball grid array substrate are lengthened to correspond with the length of the upper die (46) connections in which chip signals of the lower dies are led around from the form the wire bridges (32) through vias (41) in the substrate on to additional leads (42).

Description

Die Erfindung betrifft ein Dual-Die-FBGA mit auf einem mit einer Ein- oder Mehrebenen-Cu-Verdrahtung versehenen Substrat gestapelten Dies, wobei das Substrat auf der den Dies gegenüber liegenden mit Ball Pads zur Aufnahme von Lötbällen versehen ist und wobei die Ball Pads mit Bondpads auf den Dies elektrisch verbunden sind.The The invention relates to a dual-die FBGA with on one with a or multi-level Cu wiring provided substrate stacked dies, the substrate being on the opposite of the die with ball pads provided for receiving solder balls is and where the ball pads with bond pads on the dies electric are connected.

Für die Realisierung von DIMM (Dual In-line Memory Module, ein 168-Pin-Modul) ist oft eine Stapelanordnung notwendig, um die nötige Funktionsdichte realisieren zu können. In Frage kommt dabei entweder ein Packagestapel, z. B. US 2002/0135066 A1 mit einem gestapelten BGA-Package, oder ein Die-Stapel (Chipstapel). Um eine 4 GB DDR1 DIMM mit einer sehr hohen Dichte realisieren zu können, ist die Stapeltechnologie wegen der geringen Package-Abmessungen unumgänglich. Um solche Die-Stapel zu realisieren, kommen zwei Möglichkeiten in Betracht. Dies ist entweder die Dual-Die-BGA (DDBGA) in Faceup/Faceup (FUFU) Technologie mit RDL (Redistribution Layer), oder ein Facedown/Faceup (FDFU) DDBGA (Ball Grid Array). Unter Dual Die ist eine Stapelanordnung mit zwei Dies/Chips zu verstehen.For the realization DIMM (Dual In-line Memory Module, a 168-pin module) is often a stack arrangement necessary to realize the necessary functional density to be able to. In question comes either a package stack, z. For example, US 2002/0135066 A1 with a stacked BGA package, or a die stack (chip stack). To realize a 4 GB DDR1 DIMM with a very high density too can, is the stacking technology because of the small package dimensions unavoidable. To realize such die stacks, there are two possibilities into consideration. This is either the dual-die BGA (DDBGA) in Faceup / Faceup (FUFU) Technology with RDL (Redistribution Layer), or a Facedown / Faceup (FDFU) DDBGA (Ball Grid Array). Under Dual Die is a stacking arrangement to understand with two dies / chips.

Ein Beispiel für ein FUFU DDBGA mit Reroute Layer geht aus der US 2004/0036182 A1 hervor.One example for a FUFU DDBGA with Reroute Layer is from US 2004/0036182 A1 out.

Bei der FUFU-Technologie ist die Verwendung einer RDL unumgänglich, um die zentral auf dem Die angeordneten Bondpads auf den Rand des Dies „umzuverdrahten", so dass dann möglichst kurze Drahtbrücken zu Kontaktpads auf dem Substrat gezogen werden können. Es ist klar, dass dieser zusätzliche Prozessschritt die Fertigungskosten erhöht. Darüber hinaus ist zwischen den gestapelten Dies ein Spacer (Abstandhalter) notwendig, um das untere Die ebenfalls mit Drahtbrücken mit dem Substrat verbinden zu können, was zu zusätzlichen Montageschritten und einer größeren Packagehöhe führt.at FUFU technology requires the use of an RDL, in order to "rewire" the centrally arranged bond pads to the edge of the die, so that as possible short wire bridges can be pulled to contact pads on the substrate. It is clear that this additional Process step increases the production costs. In addition, between the stacked this a spacer (spacer) necessary to the bottom The also with wire bridges to connect to the substrate, what about additional Assembly steps and a larger package height leads.

1a (Stand der Technik) zeigt ein FUFU DDBGA auf einem BGA Substrat 1 mit Solder Balls 2 auf Ball Pads auf einer Seite und einem FUFU-Die-Stapel 3 auf der anderen Seite. Das untere Die 4 ist Face-Up mittels eines Adhesive Tapes/Klebeband 5 auf dem Substrat 1 befestigt und auf der aktiven Seite mit einer RDL 6 versehen, welche die mittigen Bondpads 7 auf den Randbereich des Dies 4 umverdrahtet. Die elektrische Verbindung zwischen dem Die 4 und der Cu-Verdrahtung 8 des Substrates 1 erfolgt mit Drahtbrücken 9. 1a (Prior Art) shows a FUFU DDBGA on a BGA substrate 1 with Solder Balls 2 on ball pads on one side and a FUFU die stack 3 on the other hand. The lower die 4 is Face-Up using an adhesive tape 5 on the substrate 1 attached and on the active side with an RDL 6 provided which the central bond pads 7 on the edge area of the Dies 4 rewired. The electrical connection between the die 4 and the Cu wiring 8th of the substrate 1 done with wire bridges 9 ,

Auf dem Die 4 ist schließlich ein Spacer 10 zur Aufnahme eines weiteren Dies 11 montiert. Die Abmessungen des Spacers 10 sind kleiner, als die des Dies 4, so dass am Rand des Dies 4 ein Freiraum freigehalten wird, um eine Drahtbondung zu ermöglichen.On the die 4 is finally a spacer 10 for receiving another dies 11 assembled. The dimensions of the spacer 10 are smaller than those of the Dies 4 so on the edge of this 4 a free space is left free to allow wire bonding.

Das Die 11 ist ebenfalls mit einer RDL 12 zur Umverdrahtung der zentralen Bondpads 13 auf den Rand versehen. Die elektrische Verbindung mit dem BGA-Substrat 1 erfolgt auch hier mit Drahtbrücken. Die elektrische Verbindung zu den Ball Pads erfolgt über Vias durch das BGA-Substrat 1.The die 11 is also with an RDL 12 for rewiring the central bond pads 13 provided on the edge. The electrical connection to the BGA substrate 1 also takes place here with wire bridges. The electrical connection to the ball pads is via vias through the BGA substrate 1 ,

1b (Stand der Technik) zeigt ein FDFU DDBGA. Hier ist das untere Die 14 direkt Face Down auf das BGA-Substrat 15 montiert. Auf der anderen Seite des Substrates 15 befinden sich Solder Balls/Lötkugeln 16. Auf dem Die 14 ist ein weiteres Die 17 Face Up unter Zwischenlage eines Adhesive Tape/Klebeband 18 montiert. Das Die 16 ist mit einem zusätzlichen Substrat 19 versehen und über Drahtbrücken 20 mit dem BGA-Substrat 15 elektrisch verbunden. Bei entsprechend kleinen Abmessungen der Dies 14, 17 kann auch auf das zusätzliche Substrat verzichtet werden und eine etwas längere Drahtbrücke vom oberen Die 17 zum Substrat 15 hergestellt werden. 1b (Prior Art) shows a FDFU DDBGA. Here is the bottom die 14 directly face down on the BGA substrate 15 assembled. On the other side of the substrate 15 There are Solder Balls / solder balls 16 , On the die 14 is another die 17 Face Up with the interposition of an Adhesive Tape / Adhesive Tape 18 assembled. The die 16 is with an additional substrate 19 provided and via wire bridges 20 with the BGA substrate 15 electrically connected. With correspondingly small dimensions of the Dies 14 . 17 can also be dispensed with the additional substrate and a slightly longer wire bridge from the upper die 17 to the substrate 15 getting produced.

Die elektrische Verbindung zwischen dem unteren Die 14 und der Ballseite des BGA-Substrates 15 erfolgt über Drahtbrücken 21, die durch einen zentralen Bondkanal 22 gezogen sind.The electrical connection between the lower die 14 and the ball side of the BGA substrate 15 via wire bridges 21 passing through a central bond channel 22 are drawn.

Dieser Die-Stapel hat den Nachteil einer unvermeidbaren Asymmetrie der elektrischen Verbindungen zwischen dem unteren und dem oberen Die in Bezug auf deren unterschiedlichen Länge zwischen Die 14, 17 und den Lötkugeln 16. Das untere Die 14 hat dabei eine sehr kurze Verbindungslänge (Trace Length) zum BGA-Substrat 15, verglichen zum oberen Die 17. Dadurch gehen die Signale des unteren Dies 14 direkt vom dessen Bond Pads (ausgestattet mit Solder Bumps/Löthöckern oder Compliant Bumps/nachgiebige Kontakthöcker) auf dem Die 14 zum entsprechenden Ball-Pad für eine Lötkugel 16. Die Signale vom oberen Die 17 benötigen eine sehr große Verdrahtungslänge zur Chipseite des Substrates 15, oder besitzen ein zusätzliches Substrat mit zusätzlichen Drahtbond-Verbindungen.This die stack has the disadvantage of an unavoidable asymmetry of the electrical connections between the lower and the upper Die in relation to their different length between the 14 . 17 and the solder balls 16 , The lower die 14 has a very short connection length (Trace Length) to the BGA substrate 15 , compared to the top die 17 , This will cause the signals of the lower dies 14 directly from its bond pads (equipped with solder bumps or compliant bumps) on the die 14 to the corresponding ball pad for a solder ball 16 , The signals from the upper die 17 require a very large wiring length to the chip side of the substrate 15 , or have an additional substrate with additional wire bond connections.

In beiden Fällen erstrecken sich die Drahtbrücken 20 zum unteren Substrat 15. Die Signale werden dann über ein Via 21 zum entsprechenden Ball-Pad geleitet.In both cases, the wire bridges extend 20 to the lower substrate 15 , The signals are then transmitted via a via 21 directed to the corresponding ball pad.

Beide DDBGA's sind zum Schutz der Komponenten mit einem Moldcompound auf der Chipseite umhüllt.Both DDBGA's are for Protection of components with a mold compound on the chip side envelops.

2 zeigt eine schematische dreidimensionale Ausschnitt-Darstellung des Layouts der Signalleitungen auf einem BGA-Substrat 15 nach dem Stand der Technik. Das BGA-Substrat ist mit einer chipseitigen Cu-Verdrahtung 15' und einer ballseitigen Cu-Verdrahtung 15'' versehen, wobei nur die Zuleitungen zu einem Ball-Pad für eine Lötkugel 16 dargestellt sind. 2 shows a schematic three-dimensional cutout view of the layout of the signal lines on a BGA substrate 15 According to the state of the art. The BGA substrate is a chip-side Cu wiring 15 ' and a ball-side Cu wiring 15 '' provided, with only the leads to a ball pad for a solder ball 16 are shown.

Die Cu-Verdrahtungen 15', 15'' sind hier nur schematisch angedeutet. Die ballseitige Cu-Verdrahtung 15'' enthält ein Bondpad für die Lötkugel 16, das über eine Cu-Leitbahn mit einem Via 23 und über eine weitere Cu-Leitbahn mit einem Bond-Pad 24 für den Anschluss einer Drahtbrücke 20 zum oberen Die 17 verbunden ist. Vom Via 23 führt eine weitere Cu-Leitbahn zu einem Bond-Pad 25 zum Anschluss des unteren Dies 14 über die Drahtbrücke 21.The copper wiring 15 ' . 15 '' are indicated here only schematically. The ball-side Cu wiring 15 '' contains a bondpad for the solder ball 16 which has a Cu interconnect with a via 23 and another Cu interconnect with a bond pad 24 for connecting a wire bridge 20 to the upper die 17 connected is. From the Via 23 leads another Cu interconnect to a bond pad 25 for connecting the lower dies 14 over the wire bridge 21 ,

Das führt zu unterschiedlichen Parasitäten (Widerstand, Induktivität, Kapazität) und daraus zu einem unsymmetrischen Verhalten der Anordnung mit Schwingungen (ringing) und kleineren Datenmengen.The leads to different parasites (resistance, inductance, Capacity) and from this to an asymmetrical behavior of the arrangement with Vibrations (ringing) and smaller amounts of data.

Der Erfindung liegt nunmehr die Aufgabe zugrunde, ein Dual-Die-FBGA in Form eines FDFU DDBGA zu schaffen, das mit geringerem Herstellungsaufwand gefertigt werden kann und bei dem der Nachteil der unterschiedlichen Signallaufzeiten sowie des schlechten Schwingungsverhaltens beseitigt ist.Of the Invention is now the object of a dual-die FBGA in the form to create a FDFU DDBGA, with less manufacturing overhead can be made and in which the disadvantage of different Signal delay and the poor vibration behavior is eliminated.

Die der Erfindung zugrunde liegende Aufgabe wird bei einem Dual-Die-FBGA der eingangs genannten Art gemäß den kennzeichnenden Merkmalen des Anspruchs 1 gelöst. Weitere Ausgestaltungen der Erfindung gehen aus den zugehörigen Unteransprüchen hervor.The The object underlying the invention is in a dual-die FBGA of the type mentioned according to the characterizing Characteristics of claim 1 solved. Further embodiments of the invention will become apparent from the accompanying dependent claims.

Die Erfindung wird an einem FDFU DDBGA realisiert, wodurch sich Vorteile bei der Fertigung realisieren lassen. Durch die innovative Substratgestaltung werden die Probleme der unterschiedlichen Leitungslängen (Trace Längths) zwischen dem oberen und dem unteren Die überwunden.The Invention is realized on a FDFU DDBGA, which has advantages can be realized during production. Due to the innovative substrate design become the problems of different line lengths (Trace Längths) between the upper and lower Die overcome.

Erreicht wird das durch die künstliche Verlängerung der Leitungslängen für das untere Die. Zu diesem Zweck werden die Chipsignale des unteren Dies vom Landing Pad für das Drahtbonden über Öffnungen (Vias) auf die obere Substratseite (Chipseite) umgeleitet. Die Öffnungen (Vias) können an jeder Stelle im Substrat positioniert werden, wo dies nach dem Substratdesign möglich ist. Damit wird erreicht, dass auf der Ball- und Chipseite des Substrates die Leitungslängen übereinstimmen. Die Leitungen des unteren und des oberen Dies werden gemeinsam auf die obere Substratseite (Chipseite) geführt und zwar bevorzugt nahe zu den Bond Pads für die Drahtbrücken vom oberen Die.Reached will that be through the artificial renewal the cable lengths for the lower die. For this purpose, the chip signals of the lower dies from the Landing pad for Wire bonding via openings (Vias) on the upper substrate side (chip side) redirected. The openings (Vias) can be positioned at any point in the substrate, where this after the Substrate design possible is. This ensures that on the ball and chip side of the substrate the cable lengths match. The lines of the lower and the upper dies are shared on the top substrate side (chip side) out and preferably close to the bond pads for the wire bridges from the upper die.

Von diesem Punkt aus, wo die Signale des unteren und des oberen Dies zusammengeführt sind, werden die Signale gemeinsam mittels eines Vias auf die Ballseite des Substrates und schließlich zum entsprechenden Ball Pad geleitet.From from this point, where the signals of the lower and the upper dies together are, the signals together by means of a vias on the ball side of the substrate and finally directed to the corresponding ball pad.

Bei Dies mit großen Abmessungen kann das obere Die mit einem zusätzlichen Substrat versehen werden, von dem dann kürzere Drahtbrücken zu den zentral angeordneten Bond Pads und etwas längere Drahtbrücken zum Substrat zu ziehen sind. Selbstverständlich kann auch eine RDL auf dem oberen Die verwendet werden.at This with big ones Dimensions, the upper die can be provided with an additional substrate, then shorter jumpers to the centrally arranged bond pads and slightly longer wire bridges to Substrate to draw. Of course, can also be an RDL the upper die are used.

Besitzt das obere Die kleinere Abmessungen, so können Drahtbrücken von dessen zentral angeordneten Bond Pads direkt zum Substrat gezogen werden.has the upper The smaller dimensions, so can wire bridges of whose centrally located bond pads are pulled directly to the substrate.

Im Ergebnis wird eine Übereinstimmung der Parasitäten (L, R, C) zwischen dem oberen und dem unteren Die erreicht. Die Folge sind wesentlich bessere elektrische Eigenschaften des FDFU DDFBGA.in the Result will be a match the parasites (L, R, C) between the upper and the lower die. The The result is much better electrical properties of the FDFU DDFBGA.

Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden. In den zugehörigen Zeichnungsfiguren zeigen:The Invention will be explained in more detail below using an exemplary embodiment. In the associated Drawing figures show:

1a: ein FUFU DDBGA (Stand der Technik), bei dem beide Dies auf der aktiven oberen Seite mit einer RDL versehen sind; 1a a FUFU DDBGA (prior art), both of which are provided with an RDL on the active upper side;

1b: ein FDFU DDBGA (Stand der Technik) mit einem zusätzlichen Substrat auf dem oberen Die; 1b a FDFU DDBGA (prior art) with an additional substrate on the top die;

2: eine schematische dreidimensionale Ausschnitt-Darstellung des Layouts der Signalleitungen nach dem Stand der Technik; 2 FIG. 3 is a schematic three-dimensional detail representation of the layout of the signal lines according to the prior art; FIG.

3: ein erfindungsgemäßes FDFU DDBGA mit einem symmetrischen Substrat-Layout für verbesserte elektrische Eigenschaften, bei dem auf der zeichnungsgemäß linken Seite eine Ausführung mit einem zusätzlichen Substrat und auf der zeichnungsgemäß rechten Seite eine Ausführung mit langen Drahtbrücken dargestellt ist; 3 a FDFU DDBGA according to the invention with a symmetrical substrate layout for improved electrical properties, in which on the left side according to the drawings an embodiment with an additional substrate and on the right side according to the drawing an embodiment with long wire bridges is shown;

4: eine schematische dreidimensionale Ausschnitt-Darstellung des Layouts der Signalleitungen nach der Erfindung. 4 : A schematic three-dimensional cutout view of the layout of the signal lines according to the invention.

3 zeigt ein erfindungsgemäßes FDFU DDBGA 30 mit einem symmetrischen Substrat-Layout für verbesserte elektrische Eigenschaften, bei dem auf der zeichnungsgemäß linken Seite eine Ausführung mit einem zusätzlichen Substrat 31 und auf der zeichnungsgemäß rechten Seite eine Ausführung mit langen Drahtbrücken 32 dargestellt ist. 3 shows an inventive FDFU DDBGA 30 with a symmetrical substrate layout for improved electrical properties, with an off on the left side as shown guide with an additional substrate 31 and on the right side according to the drawing a design with long wire bridges 32 is shown.

Das FDFU DDBGA 30 ist auf einem 2-Ebenen-Substrat 33 aufgebaut, das mit einem zentralen Bondkanal 34 versehen ist. Auf dem 2-Ebenen-Substrat ist auf einer Seite ein Die 35 Facedown mittels eines Tapes/Adhesive 36 chipgebondet. Auf der gegenüber liegenden Seite des 2-Ebenen-Substrates 33 befinden sich Lötbälle/Solder-Balls 37, die auf Ball-Pads 38 montiert sind. Die elektrische Verbindung der nicht dargestellten Bond-Pads des unteren Dies 35 mit ballseitigen Cu-Kontaktpads 39 erfolgt über Drahtbrücken 40, die durch den zentralen Bondkanal 34 gezogen sind. Die Cu-Kontaktpads 39 sind über Vias 41 mit der chipseitigen Cu-Verdrahtung 43 und dort mit weiteren Vias 42 verbunden, die schließlich eine elektrische Verbindung zu den Ball-Pads 38 schaffen. Auf diese Weise wird der Signalweg von den Bond-Pads des unteren Dies 35 zu den Ball-Pads 38 erheblich verlängert. Die Ball-Pads 38 sind durch Lötstopplack/Solder Resist 44 umgeben.The FDFU DDBGA 30 is on a 2-level substrate 33 built, with a central bond channel 34 is provided. On the 2-level substrate, there is a die on one side 35 Facedown by means of a tapes / adhesives 36 die-bonded. On the opposite side of the 2-level substrate 33 there are solder balls / solder balls 37 on ball pads 38 are mounted. The electrical connection of the bonding pads, not shown, of the lower die 35 with ball-side Cu contact pads 39 via wire bridges 40 passing through the central bond channel 34 are drawn. The Cu contact pads 39 are over vias 41 with the on-chip Cu wiring 43 and there with more vias 42 connected, which finally made an electrical connection to the ball pads 38 create. In this way, the signal path from the bond pads of the lower dies 35 to the ball pads 38 considerably extended. The ball pads 38 are by soldermask / solder resist 44 surround.

Auf dem unteren Die 35 ist unter Zwischenlage einer Klebefolie/Adhesive 45 ein oberes Die 46 Face-Up montiert. Die elektrische Verbindung der nicht dargestellten Bond Pads des oberen Dies 46 mit der chipseitigen Cu-Verdrahtung 43 erfolgt über eine kurze Drahtbrücke 47, die Leitbahnen der zusätzlichen Substrates 31 und eine längere Drahtbrücke 48 (linke Seite von 3). Das zusätzliche Substrat 31 ist mit einer Klebeschicht (Tape/Adhesive) 49 auf dem oberen Die 46 befestigt.On the lower die 35 is with the interposition of an adhesive film / adhesive 45 an upper die 46 Face-up mounted. The electrical connection of the not shown bond pads of the upper dies 46 with the on-chip Cu wiring 43 over a short wire bridge 47 , the interconnects of the additional substrate 31 and a longer wire bridge 48 (left side of 3 ). The additional substrate 31 is with an adhesive layer (Tape / Adhesive) 49 on the upper die 46 attached.

Auf der zeichnungsgemäß rechten Seite erfolgt die elektrische Verbindung von den Bond Pads des oberen Dies 46 zur chipseitigen Cu-Verdrahtung über eine lange Drahtbrücke 32. Dies ist möglich, wenn die Chipabmessungen das zulassen.On the right side of the drawing, the electrical connection is made from the bond pads of the upper die 46 to the on-chip Cu wiring over a long wire bridge 32 , This is possible if the chip dimensions allow this.

Die Signale des unteren Dies 35 und des oberen Dies werden in den Vias 42 zusammengeführt und gemeinsam auf die Ball-seite des 2-Ebenen-Substrates 33 und schließlich zum entsprechenden Ball Pad 38 geleitet. Zum Schutz der einzelnen Komponenten sind diese auf der Chipseite mit einer Moldmasse 51 umhüllt.The signals of the lower dies 35 and the upper dies are in the vias 42 brought together and together on the ball side of the 2-level substrate 33 and finally to the corresponding ball pad 38 directed. To protect the individual components, these are on the chip side with a molding compound 51 envelops.

Aus 4 ist eine schematische dreidimensionale Ausschnitt-Darstellung des Layouts der Signalleitungen nach der Erfindung ersichtlich. Mit der mäanderähnlichen Leitbahn 52 auf der chipseitigen Cu-Verdrahtung 43 kann zwischen den Vias 41 und 42 eine weitere Verlängerung des Signalweges vom unteren Die 35 zu den Ball-Pads 38 erreicht werden. Damit ist eine genaue Anpassung der Signalwege vom unteren Die 35 und vom oberen Die 46 auf einfache Weise möglich.Out 4 is a schematic three-dimensional cutout view of the layout of the signal lines according to the invention can be seen. With the meandering track 52 on the on-chip Cu wiring 43 can be between the vias 41 and 42 another extension of the signal path from the lower die 35 to the ball pads 38 be achieved. This is an exact adaptation of the signal paths from the lower die 35 and from the upper die 46 in a simple way possible.

11
BGA-SubstratBGA substrate
22
Solder Ball/LötkugelSolder Ball / solder ball
33
FUFU-Die-StapelFUFU-die stack
44
unteres Dielower The
55
Klebeband/AdhesiveTape / Adhesive
66
RDLRDL
77
Bondpadbonding pad
88th
Cu-VerdrahtungCu wiring
99
Drahtbrückejumper
1010
Spacerspacer
1111
weiteres Dieadditional The
1212
RDLRDL
1313
Bondpadbonding pad
1414
unters DieUnters The
1515
BGA-SubstratBGA substrate
15'15 '
Cu-VerdrahtungCu wiring
15''15 ''
Cu-VerdrahtungCu wiring
1616
Lötkugel/Solder BallSolder ball / Solder ball
1717
weiteres Dieadditional The
1818
Klebeband/AdhesiveTape / Adhesive
1919
zusätzliches Substratadditional substratum
2020
Drahtbrückejumper
2121
Drahtbrückejumper
2222
BondkanalBond channel
2323
ViaVia
2424
Bond-PadBonding pad
3030
FDFU DDBGAFDFU DDBGA
3131
zusätzliches Substratadditional substratum
3232
lange DrahtbrückeLong jumper
3333
2-Ebenen-Substrat2-plane substrate
3434
zentraler Bondkanalcentrally Bond channel
3535
unteres Dielower The
3636
Adhesive/Tape/KlebefolieAdhesive / tape / adhesive film
3737
Lötballsolder ball
3838
Ball-PadBall Pad
3939
ballseitiges Cu-Kontaktpadball-side Cu contact pad
4040
Drahtbrückejumper
4141
ViaVia
4242
chipseitige Cu-Verdrahtungchip-side Cu wiring
4343
chipseitige Cu-Verdrahtungchip-side Cu wiring
4444
Solder ResistSolder resist
4545
Klebefolieadhesive film
4646
oberes Dieupper The
4747
kurze Drahtbrückeshort jumper
4848
längere Drahtbrückelonger wire bridge
4949
Klebefolieadhesive film
5050
lange DrahtbrückeLong jumper
5151
Moldmassemolding compound
5252
mäanderähnliche Leitbahnmeander-like interconnect

Claims (6)

Dual-Die-FBGA mit auf einem mit einer Ein- oder Mehrebenen-Cu-Verdrahtung versehenen Substrat gestapelten Dies, wobei das Substrat auf der den Dies gegenüber liegenden mit Ball Pads zur Aufnahme von Lötbällen versehen ist und wobei die Ball Pads mit Bondpads auf den Dies elektrisch verbunden sind, dadurch gekennzeichnet, dass die elektrischen Leitungen zur Verbindung des unteren Dies mit den Ball-Pads des BGA-Substrates derart verlängert sind, dass deren Leitungslänge der Leitungslänge für den Anschluss des oberen Dies entspricht, indem die Chipsignale des unteren Dies von den Landing Pads der Drahtbrücken auf der Ballseite des Substrates über Vias im Substrat auf zusätzliche Leitungen auf die Chipseite des Substrates umgeleitet werden.Dual die FBGAs with dies stacked on a single or multi-level Cu wiring substrate, the substrate being provided with ball pads for receiving solder balls opposite the dies, and the ball pads with bond pads applied to the ball pads This electrically connected are that, characterized in that the electrical lines for connection of the lower dies are extended with the ball pads of the BGA substrate such that their cable length of the line length for the connection of the upper dies corresponds by the chip signals of the lower Dies from the landing Pads of the jumpers on the ball side of the substrate via vias in the substrate are redirected to additional lines on the chip side of the substrate. Dual-Die-FBGA nach Anspruch 1, dadurch gekennzeichnet, dass die Leitungen des unteren und des oberen Dies gemeinsam auf die Chipseite des Substrates geführt sind.Dual die FBGA according to claim 1, characterized in that that the lines of the lower and upper Dies together on guided the chip side of the substrate are. Dual-Die-FBGA nach Anspruch 2, dadurch gekennzeichnet, dass die Leitungen des unteren und des oberen Dies nahe zu den Bond Pads auf der Chipseite des Substrates für die Drahtbrücken vom oberen Die geführt sind.Dual die FBGA according to claim 2, characterized that the leads of the lower and upper dies are close to the bond Pads on the chip side of the substrate for the jumpers from the top The guided are. Dual-Die-FBGA nach Anspruch 1 bis 3, dadurch ge kennzeichnet, dass von dem Punkt aus, wo die Signale des unteren und des oberen Dies zusammengeführt sind, die Signale gemeinsam über Vias auf die Ballseite des Substrates und schließlich zum entsprechenden Ball Pad geleitet werden.Dual die FBGA according to claim 1 to 3, characterized that from the point where the signals of the lower and the upper This are merged the signals together over Vias on the ball side of the substrate and finally to the corresponding ball Pad are routed. Dual-Die-FBGA nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass die auf die Chipseite verlegten Leitungen des unteren Dies Verlängerungen aufweisen.Dual die FBGA according to one of claims 1 to 4, characterized in that laid on the chip side Lines of the lower dies extensions exhibit. Dual-Die-FBGA nach Anspruch 5, dadurch gekennzeichnet, dass die Verlängerungen mäanderähnlich ausgeführt sind.Dual die FBGA according to claim 5, characterized in that that the extensions Mäanderähnlich are executed.
DE102005039786A 2005-08-22 2005-08-22 Dual-die ball grid array (DDBGA) has length equalization of wiring between upper and lower dies Ceased DE102005039786A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433422B1 (en) * 1999-05-31 2002-08-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having semiconductor packages for mounting integrated circuit chips on both sides of a substrate
US6545366B2 (en) * 2001-01-11 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Multiple chip package semiconductor device
US20030124766A1 (en) * 2001-12-29 2003-07-03 Kim Ji Yon Method for manufacturing stacked chip package
US20040159954A1 (en) * 2002-12-17 2004-08-19 Infineon Technologies Ag Electronic device having a stack of semiconductor chips and method for the production thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433422B1 (en) * 1999-05-31 2002-08-13 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having semiconductor packages for mounting integrated circuit chips on both sides of a substrate
US6545366B2 (en) * 2001-01-11 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Multiple chip package semiconductor device
US20030124766A1 (en) * 2001-12-29 2003-07-03 Kim Ji Yon Method for manufacturing stacked chip package
US20040159954A1 (en) * 2002-12-17 2004-08-19 Infineon Technologies Ag Electronic device having a stack of semiconductor chips and method for the production thereof

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