DE102005045078B4 - Field effect transistor with a strained channel layer on sidewalls of a structure on a semiconductor substrate - Google Patents

Abstract

A field effect transistor (FET) having a channel layer on sidewalls of a structure (400, 410) on a semiconductor substrate (110) and having at least a portion of the channel layer in a first direction in which the sidewalls of the structure are away from the semiconductor substrate (110) extend, is strained,
wherein the transistor comprises a FinFET, wherein the structure has a fin structure (400, 410) and wherein the sidewalls have sidewalls of the fin structure (400, 410) and wherein the fin structure (400, 410) comprises a plurality of layers different materials, wherein the alternating layers have more than one layer (140) of Si and more than one layer (120) of SiGe,
furthermore with:
a gate dielectric (180) at the channel layer;
a gate electrode (220) at a portion of the gate dielectric (180); and source and drain regions (300) at opposite sides of the gate electrode (220) in a second direction perpendicular to the first direction.

Description

FIELD OF THE INVENTION

The The present invention relates to a field effect transistor having a strained channel layer on sidewalls of a structure on a Semiconductor substrate according to claim 1.

BACKGROUND OF THE INVENTION

From the WO 2004/032246 A1 For example, a FinFET device is known in which a strained silicon is used to increase carrier mobility. The FinFET device is patterned using a layer of silicon germanium (SiGe) superimposed on a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A voltage is induced in the epitaxial silicon as a result of different dimensions of the internal silicon and the silicon germanium crystal lattice, which serves as a template or mask on which the epitaxial silicon is grown. Tensioned silicon has increased carrier mobility compared to relaxed silicon, and as a result of the stressed epitaxial silicon, increased carrier mobility is achieved in the FinFET device. Therefore, a higher drive current can also be realized in a FinFET device using a strained silicon channel layer.

From the US2004 / 0157353 A1 A method is known for producing a voltage-carrying vertical channel of a field-effect transistor, as well as a field-effect transistor produced according to this method and a CMOS circuit arrangement having a drain zone, a semiconductor body and a source zone on a side wall of a vertical single-crystal semiconductor structure. wherein a heterojunction is formed between the source region and the main body of the transistor. In this known structure, the source region and the channel are independently held under a grid voltage with respect to the semiconductor body region, and the drain region includes a carbon doped region to prevent diffusion of the dopant (boron) into the semiconductor body , By means of this known structure, the problem of a leakage current from the source region across the heterojunction and the grating voltage region is reduced, and independently a grating voltage is realized in the channel region to increase the mobility, which also has a specific choice of semiconductor materials he follows.

Over the past 30 years, developments in silicon-based integrated circuit technology, such as For example, metal-oxide-semiconductor (MOS) devices including field effect transistors (FET and / or MOSFET), increased device speed, increased integration density, and improved device functionality are provided at a reduced cost. Referring to 1A MOS devices are typically in a substrate 10 with heavily doped source / drain (S / D) regions 12 passing through a more lightly doped channel region 18 are separated, formed. The canal region 18 can through a gate electrode 14 controlled by the channel region through a gate dielectric 16 is disconnected.

With growing demands for higher Integration as well as higher Performance, lower power consumption and greater economy can be one Variety of problems, the deterioration of transistor characteristics are assigned arise. While for example, the channel length a transistor can be reduced, short channel effects, such as z. B. a penetration, a drain-induced lowering of the barrier (DIBL = Drain Induced Barrier Lowering), a subthreshold rash, an increased parasitic capacitance between a transitional or junction region and the substrate (i.e., a junction capacitance) and increased leakage current occur.

A Variety of transistor designs has been developed that addresses some of the problems that you would find in conventional solid MOS semiconductor devices or bulk MOS semiconductor devices encountered, are addressed. These transistor designs include, for example, ultra-thin body transistors, double-gate transistors, Recessed channel array (RCAT) transistors Transistor), FinFET and gate all-around transistor (GAAT).

1B represents, for example, a conventional ultrathin body transistor. In an ultra-thin body transistor, the channel region 18 be formed in a thin film above an insulating region. 1C further illustrates a conventional double gate transistor. In a double gate transistor, a single channel region 18 through two gates 14a and 14b controlled by the channel region through gate dielectrics 16a and 16b are separated. As such, both sides of the channel region can be controlled.

The devices of 1B and 1C However, more complex manufacturing processes that can increase the effort and reduce the yield may require. Such devices can Kings Accordingly, they are less practical in general semiconductor manufacturing.

The Production of ultra-thin body transistors For example, it can be considerably more complex than conventional ones Bulk MOS devices. Although the same in some areas can deliver improved performance, can Ultra-thin body transistors across from Variable Area and heat transfer effects susceptible be and can Current limits, by the body thickness are imposed.

In addition, by controlling the channel from two sides, dual gate devices can exhibit improved leakage performance. However, dual gate devices may require more complex fabrication processes that increase the overhead and lower the yield. In particular, in dual gate transistor fabrication, it may be difficult to have an upper gate 14a and a lower gate 14b (as in 1C shown).

Gate all-round transistors are disclosed, for example, in the United States Patent US Pat. No. 6,391,782 B1 to Yu, entitled "PROCESS FOR FORMING MULTIPLE ACTIVE LINES AND GATE-ALL-AROUND MOSFET."

FinFET transistors in which the channel region is formed in a vertically protruding "fin" or "rib" of semiconductor material may provide leakage similar to or better than double gate transistors, but may be less complicated and less expensive to manufacture. FinFET transistors (or simply FinFETs) may further support scaling to sub-50nm channel lengths (and possibly as low as 10nm), which may provide additional improvements in integration density and speed of operation. FinFET structures are disclosed in the United States Patent US Pat. No. 6,413,802 B1 to Hu et al., entitled "FINFET TRANSISTOR STRUCTURES HAVING A DOUBLE GATE CHANNEL EXTENDING VERTICALLY FROM A SUBSTRATE AND METHODS OF MANUFACTURE".

at FinFET may be the channel region in a vertically oriented rib-shaped active Region protruding from the semiconductor substrate as above erör tert is, be formed. The gate dielectrics may be formed at the rib may be, and the gate electrode may be formed around the rib. The Channel region can be followed first by source and drain regions be formed. The source / drain regions may be higher than the rib. dielectric and conductive Materials can then used to double and / or triple gate devices to build.

2A to 2D FIG. 15 are cross-sectional views of a semiconductor substrate illustrating conventional methods of forming a FinFET.

Referring now to 2A becomes an etching mask pattern 13 on a silicon substrate 10 educated. A section of the silicon substrate 10 passing through the etching mask pattern 13 is anisotropically etched to a silicon fin 15 to build. An upper edge or an upper edge of the silicon fin 15 is formed at an acute angle (ie, almost at a right angle) due to the anisotropic etching. The etching mask pattern 13 may be formed of nitride, and a thermal oxide layer may be formed between the nitride and the substrate. To provide electrical isolation between the adjacent silicon fins, a device separator layer is formed 17 , as in 2 B shown is formed.

Referring now to 2C becomes a portion of the device separation layer 17 removes whatever lateral surfaces or sidewalls of the silicon fin 15 exposes. The lateral surfaces of the silicon fin 15 may serve as a channel region for a transistor.

Referring to 2D becomes a gate insulation layer 19 on the exposed sidewalls of the silicon fin 15 formed, and a gate electrode 21 is formed to produce a double-gate FinFET. Both side walls of the silicon fin 15 can through the gate electrode 21 to be controlled.

According to conventional methods of forming double gate FinFET, adhesion between the etch mask pattern 13 and the substrate 10 weakened when a section of the device separating layer 17 Will get removed. As the device separating layer 17 can also be formed from an oxide, a thermal oxide layer of Ätzmaskenmusters 13 at a portion of the silicon fin together with the portion of the device separation layer 17 be removed. Because the width of the silicon fin 15 can be scaled down to allow for higher device integration, it may be increasingly possible for the etch mask pattern 13 from the upper surface of the silicon fin 15 is disconnected. When the etching mask pattern is removed, an upper surface of the silicon fin may be formed 15 through the gate electrode 21 can be controlled, and a triple gate FinFET can be formed. Accordingly, double gate and triple gate FinFETs can be formed on the same wafer.

Further referring to 2D can to form higher performance devices that Width of the silicon fin 15 by performing a thermal oxidation process prior to forming the gate insulating layer 19 be reduced. The width of the silicon fin 15 in other words, by forming a sacrificial oxide layer on sidewalls of the fin 15 be reduced using a thermal oxidation process and then by removing the sacrificial oxide layer. As such, the rib can 15 a width narrower than the same of the etching mask pattern 13 exhibit. An undercut region may accordingly be under the etch mask pattern 13 be formed, resulting in a bad step coverage during subsequent procedures, such as. As the deposition of a gate electrode material leads. In addition, when the sacrificial oxide layer is removed, the thermal oxide layer of the etching mask pattern may become 13 also partially removed. As a result, the etch mask pattern 13 from the silicon rib 15 can be disconnected, and the problems described above can occur.

Triple-gate FinFET have been developed that address some of these problems. In triple-gate FinFETs, a top surface and both side walls the silicon fin controlled by a gate electrode, which improve the Stromtreibkapazität can.

A conventional method of forming a triple gate FinFET is described with reference to FIG 3A to 3B described. Triple gate FinFETs can be obtained by removing the etching mask pattern in the conventional double gate FinFET forming methods described above with reference to FIGS 2A to 2D are described are formed.

As in 2 B is shown, a silicon fin 15 and a device separator 17 educated. Then, as in 3A a portion of the device separator is shown 17 and an etching mask pattern 13 away. As a result, both sidewalls and an upper surface of the silicon fin are 15 exposed.

Referring to 3B becomes a gate insulation layer 19 on the exposed surfaces (ie, both sidewalls and the top surface) of the silicon fin 15 formed, and then becomes a gate electrode 21 educated.

transistors with improved mobility using a strained channel, were also studied to improve transistor performance. These transistors generally use as a voltage generator a thick epitaxial SiGe layer or use an epitaxial silicon-to-germanium-on-insulator (SGOI; SGOI = Epitaxial silicon to germanium to insulator) wafer. The usage However, a thick SiGe layer or a SGOI wafer can be complex to produce be. The strained channel transistors also typically become implemented in a planar structure. Transistors with strained channel For example, in Hoyt et al., "Strained Silicon MOSFET Technology", Electron Devices Meeting, 2002, IEDM '02, Digest. International, pp. 23-26; Ota et al., "Novel Locally Strained Channel Technique for High Performance 55nm CMOS ", Electron Devices Meeting, 2002, IEDM '02, Digest. International, pp. 27-30; Rim et al., "Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly to Insulator (SSDOI) MOSFETs ", Electron Devices Meeting, 2003, IEDM '03 Technical Digest. IEEE International, P. 3.1.1-3.1.4; Takagi et al., "Channel Structure Design, Fabrication and Ca Animal Transport Properties of Strained-Si / SiCe-On-Insulator (Strained SOI) MOSFETs ", Electron Devices Meeting, 2003, IEDM '03 Technical Digest. IEEE International, p. 3.3.1-3.3.4; Ge et al., "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering ", Electron Devices Meeting, 2003, IEDM '03 Technical Digest. IEEE International, p. 3.7.1-3.7.4; and Ernst et al., "Fabrication of a novel strained SiGe: C-channel planar 55nm nMOSFET for high-performance CMOS ", 2002 symposium VLSI Technology Digest of Technical Papers, whose Disclosures are incorporated herein by reference as if the same complete here would be set out.

SUMMARY OF THE INVENTION

The The problem underlying the invention is a field effect transistor with a channel layer on sidewalls of a structure at one To provide semiconductor substrate, wherein the channel layer at least has a portion in a direction in which the side walls the structure of the semiconductor substrate, is braced.

These The object is achieved by a Field effect transistor solved according to claim 1.

Especially advantageous embodiments and further developments of the field effect transistor according to the invention emerge from the dependent claims.

In particular embodiments of the present invention, the transistor comprises a FinFET, the structure on the semiconductor substrate has a fin structure, and the sidewalls have sidewalls of the fin structure. The channel layer may be an epitaxial Si layer. The channel layer may have a thickness of less than about 10.0 nm. In specific embodiments of the present invention the substrate on a Si substrate. The channel layer may have strained and unstressed portions. The strained and unstressed portions may have sidewalls of the channel layer.

at further embodiments According to the present invention, the rib structure has a plurality of layers of different materials. Each of the plural of layers of different materials has an upper surface across from and substantially parallel to the substrate and a sidewall surface, the is substantially perpendicular to the substrate, on, and the channel layer may be directly on the sidewall surfaces of the plurality of layers made of different materials.

at some embodiments In the present invention, the rib structures have alternating ones Layers of Si and SiGe on. The alternating layers can be epitaxial Be layers. The Si layers of the alternating layers may have a Have thickness of less than about 3.0 nm. The SiGe layers of alternating layers can have a thickness of less than about 5.0 nm. The alternate ones Layers can more than one layer of Si and more than one layer of SiGe exhibit. An outermost layer The alternating layers may further be a SiGe layer. A section of the channel layer may be directly at the outermost Layer of alternating layers can be arranged.

at additional embodiments According to the present invention, a FinFET has a gate dielectric at the channel layer, a gate electrode at a portion of Gate dielectric and source and drain regions on opposite Sides of the gate electrode. The channel layer can be epitaxial Si layer have. The source and drain regions can be the epitaxial Si layer have. The rib structure and the source and drain regions can have a plurality of layers of different materials. The rib structure and the source and drain regions may be alternating Have layers of Si and SiGe. The alternating layers can have epitaxial layers. The gate electrode may be a polysilicon layer. exhibit. In specific embodiments According to the present invention, the channel layer comprises sections, which are braced in a rich direction parallel to a gate width. The gate dielectric and the gate electrode may further have a damascene structure exhibit.

at further embodiments According to the present invention, a FinFET has a first dielectric Layer on the substrate, and the rib structure extends through the first dielectric layer, and the channel layer at a portion of the rib structure, but which is the first dielectric Layer extends, is arranged. The rib structure can be a Section of the substrate, wherein the portion of the Rib structure provided by the substrate over the first dielectric layer extends. The rib structure may alternatively comprise a portion of the substrate, wherein the portion the rib structure provided by the substrate does not over the extending first dielectric layer.

Some embodiments of the present invention provide fin (fin) field effect transistors (FET) and method of fabricating FinFET having an internal channel structure, a plurality of different layers of material with sidewalls, the extending from a semiconductor substrate and an outer channel layer on the side walls having the inner channel structure. The outer channel layer also faces side walls on. A gate dielectric layer may be on the sidewalls and on an upper surface the outer channel layer be provided and a side wall and an upper surface opposite the outer channel layer exhibit. A gate electrode may be attached to a portion of the sidewalls and the upper surface the gate dielectric layer may be provided. A source region and a drain region can at opposite Be arranged sides of the gate electrode.

at additional embodiments According to the present invention, the outer channel layer has an epitaxial Si layer on. Each of the plurality of different material layers can further an upper surface across from and substantially parallel to the substrate and a sidewall surface, the is substantially perpendicular to the substrate. The channel layer can directly on the sidewall surfaces of the plurality of layers made of different materials.

at further embodiments According to the present invention, the inner channel structure is alternating Layers of Si and SiGe on. The alternating layers can be epitaxial layers exhibit. The alternating layers can be more than one layer of Si and more than one layer of SiGe. An outermost layer the alternating layers may comprise a SiGe layer. One Section of the outer channel layer can also be directly at the outermost layer be arranged of the alternating layers. The gate electrode may comprise a polysilicon layer.

In additional embodiments of the According to the present invention, a first dielectric layer is provided on the substrate. The inner channel structure extends through the first dielectric layer, and the outer channel layer is disposed at a portion of the inner channel structure that extends beyond the first dielectric layer. The inner channel structure may include a portion of the substrate, and the portion of the inner channel structure provided by the substrate may extend beyond the first dielectric layer. The inner channel structure may alternatively comprise a portion of the substrate, and the portion of the inner channel structure provided by the substrate does not extend beyond the first dielectric layer.

at further embodiments According to the present invention, the substrate has an Si substrate. The outer channel layer may include portions that are in a direction parallel to a gate width are tense. The gate dielectric and the gate electrode may be a Damaszierungsstruktur have. The outer channel layer can be tense and unstressed portions. The tense and not tense sections can side walls the outer channel layer exhibit.

Some embodiments of the present invention provide a FinFET and / or method for producing a FinFET having an inner channel structure on a Semiconductor substrate, and sidewalls extending from the substrate extend, and an upper surface opposite to the substrate, an outer channel layer on the side walls and the upper surface the inner channel structure and side walls and an upper surface opposite to the having inner channel structure. At least a portion of the outer channel layer on the side walls the inner channel structure is braced. A gate dielectric layer is on the sidewalls and the upper surface the outer channel layer provided and has side walls and an upper surface across from the outer channel layer on. A gate electrode is attached to a portion of the sidewalls and the upper surface the gate dielectric layer intended. One source region and one drain region are at opposite ends Sides of the gate electrode arranged.

at further embodiments According to the present invention, the outer channel layer has an epitaxial Si layer on. The inner channel structure may include a plurality of Have layers of different materials. Each of the Multiple layers of different materials can be one upper surface across from and substantially parallel to the substrate and a sidewall surface, the is substantially perpendicular to the substrate. The outer channel layer may be directly on the sidewall surfaces of the plurality of layers made of different materials. The inner channel structure can have alternating layers of Si and SiGe. The alternate ones Channel layers can be epitaxial Have layers. The alternating layers can do more as a layer of Si and more than one layer of SiGe. An outermost layer the alternating layers may comprise a SiGe layer. One Section of the channel layer may be at the outermost layer of the alternating Layers can be arranged directly. The gate electrode may be a polysilicon layer exhibit.

at additional embodiments The present invention is a first dielectric layer provided on the substrate. The inner channel structure extends through the first dielectric layer, and the outer channel layer is at a portion the inner channel structure extending over the first dielectric Layer extends out, arranged. The inner channel structure can have a portion of the substrate, and the portion of the inner Channel structure, which is provided by the substrate extends over the first dielectric layer. The inner channel structure alternatively has a portion of the substrate, and the portion the inner channel structure provided by the substrate does not extend over the first dielectric layer.

at further embodiments According to the present invention, the substrate has an Si substrate. The outer channel layer may include portions that are in a direction parallel to a gate width are tense. The gate dielectric and the gate electrode may be a Damaszierungsstruktur have. The outer channel layer can be tense and unstressed portions. The tense and not tense sections can side walls the outer channel layer exhibit.

BRIEF DESCRIPTION OF THE DRAWINGS

1A is a cross-sectional view illustrating a conventional planar FET.

1B FIG. 10 is a cross-sectional view illustrating a conventional ultrathin body transistor. FIG.

1C FIG. 10 is a cross-sectional view illustrating a conventional double-gate FET. FIG.

2A to 2D FIG. 15 are cross-sectional views of a semiconductor substrate showing conventional methods of forming a conventional dop. FIG pel gate FinFET.

3A to 3B FIG. 15 are cross-sectional views of a semiconductor substrate illustrating conventional methods of forming a conventional triple gate FinFET.

4A FIG. 12 is a cross-sectional view of a FinFET according to some embodiments of the present invention. FIG.

4B FIG. 10 is an isometric view of a channel and gate region of a FinFET in accordance with some embodiments of the present invention. FIG.

4C FIG. 10 is a top view of a FinFET in accordance with some embodiments of the present invention. FIG.

5A and 5B 12 are schematic representations of grating structures at a portion of a fin of a FinFET in accordance with some embodiments of the present invention.

6A to 6E 12 are cross-sectional views illustrating methods of fabricating a FinFET according to some embodiments of the present invention.

7 FIG. 12 is a cross-sectional view of a FinFET according to further embodiments of the present invention. FIG.

DETAILED DESCRIPTION OF EXAMPLES THE INVENTION

The The present invention is described below with reference to FIGS attached Drawings in which exemplary embodiments of the invention are shown described. However, this invention should not be up these embodiments set forth herein be understood limited. Rather, these embodiments are such that this disclosure is thorough and complete, and they will be the scope of the invention to those skilled in the art Completely convey. In the drawings are the thicknesses of layers and Regions exaggerated for clarity shown. Same numbers refer to the same throughout Elements.

It is obvious that when on an element, such. A layer, Region or a substrate, as "on" or "on" or "on" or "on" another element referring to the same thing on the other Element can be located or directly on or to the other element can extend or intervening elements also exist could be. If in contrast to an element as being "directly on" or "directly on" or "directly on or on" another element are referenced, are not intervening Elements available. It is also obvious that when on one element as "connected" or "coupled" with another Element is referred, the same with the other element directly may be connected or coupled or intervening elements can be present. Conversely, when referring to an element as being "directly connected" or "directly coupled" to another element, There are no intervening elements.

It It is further evident that although the terms s), second (r, s) etc. can be used herein to various elements To describe these elements is not limited by these expressions should be. These expressions are only used to move one element from another differ. For example, a first element may be a second one Element, and similarly For example, a second element may be referred to as a first element without deviate from the scope of the present invention.

relative expressions such as B. "lower (r, s) "or" lowermost (r, s) "and" upper (r, s) "or" uppermost (r, s) "may also be used used herein to describe the relationship of one element to another Elements as shown in the figures to describe. It is Obviously, relative expressions have different orientations the device in addition to to include the orientation shown in the figures. If For example, the device rotated in one of the figures or Turned upside down are elements that are considered to be on the "lower" side of others Elements are then aligned to "upper" sides of the other elements. The exemplary expression "lower (r, s) "can therefore be dependent on the orientation of the figure comprises both an orientation of "lower (r, s)" and "upper (r, s)". If, similarly, the device in one of the figures is turned over are elements as "below" or "below" other elements are described as being "above" the other elements aligned. The example expressions "below" or "below" can therefore, include both an orientation from above and below.

The terminology used in the description of the invention herein is for the purpose of describing specific embodiments only and is not intended to limit the invention. As used in the description of the invention and the appended claims, the singular forms "a (r, s)" and "the" that are also meant to be plural unless the context shows otherwise. It is further apparent that the term "and / or" as used herein refers to and encompasses all possible combinations of one or more associated listed items.

embodiments The invention are described herein with reference to cross-sectional views schematic representations of idealized embodiments (and intermediate structures) of the invention are described. As such are variations of the forms of representations as a result of, for example, manufacturing processes and / or tolerances expect. embodiments Thus, the invention should not be considered as special forms regions described herein are construed to be limited, but should deviations regarding the shapes that result, for example, from manufacturing include. For example, an implanted region identifies as a rectangle is shown, typically rounded or curved features and / or a gradient of the implantation substance concentration the edges same and not a binary change from an implanted to a non-implanted region. A buried region formed by an implantation may be similar to implantation in the region between the buried region and the surface, through which the implantation takes place lead. The regions that are in The figures are thus in nature schematically, and the forms thereof are not intended to be the actual Represent a region of a device and are not supposed to Limit the scope of the invention.

It Unless otherwise defined, all expressions have that in the disclosure of embodiments of the invention, including technical and scientific expressions the same meaning as they usually do by those skilled in the art, and are not necessarily limited to specific definitions at the time of the present invention described, limited. These expressions can accordingly equivalent expressions which are created after such a time have. All publications, Patent applications, patents, and other references mentioned herein are by reference taken in their entirety.

Some embodiments of the present invention are described below with reference to FIGS 4A to 7 , which illustrate FinFET structures and methods of fabricating FinFET having a channel layer wherein at least a portion of the channel layer is distorted. However, the present invention should not be construed as limited to FinFET structures, but it may be used in other structures in which a channel is formed on a side wall of an underlying structure. A strained channel may thus be provided in, for example, an array transistor having a recessed channel or gate all-round transistor in addition to the fin-FET structures described herein. Accordingly, embodiments of the present invention may be used in FET structures having a channel layer on sidewalls of a structure wherein at least a portion of a channel layer of the FET is strained in a direction in which the sidewalls of the structure extend from a semiconductor substrate.

4A FIG. 12 illustrates a cross-sectional view of a portion of FinFET according to some embodiments of the present invention. FIG. 4B FIG. 12 is an isometric view of a gate and channel region of the FinFET of FIG 4A , As in 4A and 4B can be seen, has a substrate 110 an inner rib structure 400 having layers that conform to an outer rib structure 410 , which provides a channel layer, lattice-matched and lattice mismatched such that at least a portion of the outer fin structure 410 in a direction perpendicular to the direction of current flow in the outer fin structure 410 (eg in the vertical direction, the in 4A and 4B is shown) is braced. As will be discussed below, as used herein, layers may be lattice matched if a difference in lattice constants of the two layers is insufficient to provide sufficient stress to improve carrier mobility and may be lattice mismatched if the difference in lattice constants is two layers is sufficient to induce sufficient tension to enhance carrier mobility. In particular embodiments of the present invention, the substrate 110 an Si substrate and / or a silicon-on-insulator (SOI) substrate. The inner rib structure 400 may further SiGe layers 120 and Si layers 140 , which may each be epitaxial layers. The outer rib structure 410 may further comprise a Si layer 160 by selective epitaxial growth on the sidewall (sidewalls) and, in some embodiments, directly on the sidewall (sidewalls) of the inner fin structure 400 can be formed, such that the Si layer 160 directly on the SiGe layers 120 and the Si layers 140 is formed. In some embodiments, an outermost layer is the inner rib structure 400 a SiGe layer 120 ,

In particular embodiments of the present invention, a dielectric Gate layer 180 at the outer rib structure 410 provided, and a gate electrode 220 is at the gate dielectric layer 180 intended. In some embodiments of the present invention, the gate electrode 180 be provided by a polysilicon layer. In 4A and 4B is also a first dielectric layer 200 , which is a section of the inner rib structure 400 through the first dielectric layer 200 extends, shown. The gate dielectric layer 180 may be a suitable gate dielectric layer or layers that may be suitable for use with a FinFET structure and include, for example, an oxide, such as an oxide. For example, a silicon dioxide. The first dielectric layer 200 Similarly, it may be any suitable dielectric material including, for example, silicon dioxide. At the in 4A and 4B illustrated embodiments, the portion of the inner rib structure extends 400 passing through the substrate 110 is not substantially above the first dielectric layer 200 out. In alternative embodiments, as in FIG 7 however, a substrate may be shown 110 ' and the first dielectric layer 200 ' be provided, wherein the portion of the inner rib structure 400 ' passing through the first substrate 110 ' is provided over the first dielectric layer 200 ' out, and the outer rib structure 410 ' is at a portion of the substrate 110 ' that of the first dielectric layer 200 ' projected, provided.

4C represents source and drain regions 300 (not in 4A . 4B and 7 shown), which are also on opposite sides of the gate electrode 220 can be provided. The source and drain regions 300 can be more heavily doped than the channel region of the inner rib structure 400 or the outer rib structure 410 be. The special dopants that are used to source and drain regions 300 Depending on whether an nMOS or a pMOS device is to be provided. In some embodiments, the source and drain regions 300 through the alternating layers of SiGe 120 and Si 140 be provided. The source and drain regions 300 may further be through the epitaxial Si layer 160 be provided. The source and drain regions 300 may also be provided by regions of Si or SiGe. The SiGe, that in the source and drain regions 300 may be more heavily doped than if only Si is provided in the source and drain regions. The source and drain regions 300 can also be defined by counter-doping regions by ion implantation to define the source and drain regions.

In some embodiments of the present invention, the Si layers are 140 and the SiGe layers 120 provided as epitaxial layers. The SiGe layers 120 For example, about 30% may have Ge, which is a 1.2% difference in lattice constant between the SiGe layers 120 and the epitaxial Si layer 160 can deliver. The SiGe layers 120 can be as thick as possible, but not so thick that they significantly reduce the quality of the SiGe layers 120 for example, due to dislocation defects in the SiGe layers. The specific thickness of the SiGe layers 120 may depend on the amount of Ge in the layers, however, in some embodiments for SiGe layers of about 30% Ge, a thickness of up to about 20 nm may be provided. In some embodiments, the Si layers 140 a thickness of about 5 nm, and the SiGe layers 120 have a thickness of about 20 nm. The number of layers of Si 140 and SiGe 120 can from the total height of the inner rib structure 400 and depend on the thicknesses of each layer. However, in some embodiments, more than one layer of Si and more than one layer of SiGe may be provided. In specific embodiments of the present invention, the Si layers 140 a thickness of less than about 3.0 nm, and the SiGe layers have a thickness of less than about 5.0 nm. In some embodiments of the present invention, the overall height of the inner rib structure is 400 from about 100 nm to about 150 nm. An outermost layer of the alternating layers may further include a SiGe layer 120 be like in 4A is shown.

The outer rib structure 410 may be due to an epitaxial Si layer 160 attached to the inner rib structure 400 is formed, be provided. The epitaxial Si layer 160 may have a thickness of at least the expected channel depth of the device. However, in some embodiments, the epitaxial Si layer may 160 have a thickness of less than about the expected depth of the channel of the device, such that the channel is in operation in the inner rib structure 400 extends. The epitaxial Si layer may be to a thickness of about 2.0 nm to about 10.0 nm prior to the formation of the gate oxide 180 However, other thicknesses can be used. The gate oxide 180 may be formed by thermal oxidation and may include a portion of the epitaxial Si layer 160 consume. About 45% of the epitaxial Si layer 160 can be consumed during thermal oxidation to the gate oxide 180 to deliver. After the formation of the gate oxide 180 may be at least about 1.0 nm of the epitaxial Si layer 160 remain. The thickness of the grown epitaxial Si layer 160 may differ if other methods of forming the gate oxide 180 , such as B. by a deposition can be used.

As in 4A and 4B is thus an internal channel structure through the inner rib structure 400 provided and has a plurality of different material layers and side walls extending from the semiconductor substrate 110 extend. The plurality of different material layers have an upper surface opposite and substantially parallel to the substrate 110 and a sidewall surface substantially perpendicular to the substrate 110 is on. The plurality of different material layers may be provided as a stack of multiple layers of different semiconductor materials. An outer channel layer is through the outer rib structure 410 provided and located on the side walls of the inner channel structure. The outer channel layer further includes sidewalls and may be directly on the sidewalls of the plurality of different material layers of the inner channel structure. At least a portion of the outer channel layer on the side walls of the inner channel structure is braced. The gate dielectric layer 180 is provided on the sidewalls and an upper surface of the outer channel layer, and has a sidewall and an upper surface opposite to the outer channel layer. The gate electrode 220 is at a portion of the sidewalls and the upper surface of the gate dielectric layer 180 intended.

5A and 5B schematically represent lattice structures of the inner rib structure 400 and the outer rib structure 410 which provide a channel layer according to some embodiments of the present invention. As in 5A and 5B can be seen, has the inner rib structure 400 SiGe layers that are substantially lattice-matched to the Si layers in the (100) plane and mismatched with the Si layer of the outer fin structure in the (110) plane. The outer rib structure 410 that provides the channel layer is thus braced where the outer rib structure 410 at the SiGe layers of the inner rib structure 400 is formed, and is not strained where the outer rib structure 410 at the Si layers of the inner rib structure 400 is formed. As used herein, the terms lattice mismatch and lattice match refer to differences in lattice constants of the two materials. Differences in lattice constant are further considered essential if the differences cause stress to be induced in one of the layers sufficient to increase the vehicle mobility, at least in part, as a result of the stress induced in the layer improve.

As in 5B As can be seen, as a result of the lattice mismatch between the inner rib structure and the outer rib structure, the outer rib structure providing the channel layer may have strained and unstressed portions. Since the voltage in the vertical direction in the diagram of 5B and current flows in or out of the page in a FinFET configuration, the direction of the voltage is parallel to the width of the gate / channel. Since the SiGe layers have a larger lattice constant than the Si layers, the stress in the Si layer on the SiGe layers is a tensile stress. According to Ge et al., "Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering", Electron Devices Meeting, 2003, IEDM'03 Technical Digest. IEEE International, pp. 3.7.1-3.7.4, a strain perpendicular to the current flow and gate width can improve the performance of both nMOS and pMOS devices. Rib structures according to embodiments of the present invention may accordingly be suitable for use in both nMOS and p-MOS devices.

6A to 6E illustrate methods of fabricating FET with strained channel layers in accordance with some embodiments of the present invention 6A can be seen, alternating layers of SiGe 312 and Si 314 on a Si substrate 310 educated. The alternating layers of SiGe 412 and Si 314 may be formed by epitaxial growth and may be formed with dimensions as described above. Optionally, if a counter-doping implant on the resulting structure of 6A is performed, a buffer layer (not shown), such as. As an oxide layer, between the Si substrate 310 and the alternating layers of SiGe 312 and Si 314 be provided. Ceiling ion implantation may alternatively be performed on the resulting structure of 6A be carried out so that a counter-doping is unnecessary.

As in 6B can be shown, the inner rib structure 400 from 4A and 4B by etching the structure of 6A through the alternating layers of SiGe 312 and Si 314 and in the substrate 310 be formed to the substrate 110 , the SiGe layers 120 and the Si layers 140 to provide that form the inner rib structure. A SiN layer 322 may be provided on the inner fin structure and may be used as an etch mask. An oxide layer 320 , such as As SiO ₂ , may further on the substrate 100 be formed to surround the rib structure. In some embodiments of the present invention, after formation of the fin structure, an oxide layer is formed on the structure, and a trench corresponding to the fin structure is etched into the oxide layer to form the oxide layer 320 provided. The trench is then passed through a SiN layer filled, and a chemical-mechanical polishing process is carried out to the SiN layer 322 to provide in the trench. As discussed above, the SiN layer 322 as a mask during subsequent etching back of the oxide layer 320 Act.

6C provides the etching back of the oxide layer 320 to the oxide layer 200 provided. As in 6C can be seen, the oxide layer 320 to the substrate 110 be deepened or in some embodiments, as in 7 is shown over the portion of the substrate 110 which forms a section of the rib structure will be recessed out. The rib structure may optionally be trimmed or thinned such that the width of the rib structure is reduced.

6D represents the formation of the Si layer 160 on the inner rib structure 400 dar. The Si layer 160 that the outer rib structure 410 can be achieved by selective epitaxial growth of a Si layer on the SiGe layers 120 and the Si layers 140 be formed, such that the Si layer 160 on the sidewalls of the inner rib structure 400 is formed. The Si layer 160 could be further characterized by solid phase epitaxy by forming an amorphous silicon layer on the inner fin structure 400 and then annealing the amorphous layer to convert the layer into a crystalline layer.

6E represents the formation of the gate oxide 180 and the gate electrode 220 As discussed above, the gate oxide 180 by a thermal oxidation of the Si layer 160 be formed. The gate electrode 220 can be formed and patterned using conventional patterning techniques. After the formation and pattern of the gate electrode 220 Optionally, the source and drain regions can be increased by selective epitaxial growth in the source and drain regions.

at some embodiments In the present invention, the gate structure is formed by a damascene method formed to provide a damascene gate structure. In such embodiments For example, the gate may be formed in a depression around the fin structure Ceiling deposition of a gate material can be followed by a CMP or another planarization can be performed to remove the gate material, that is not in the depression. In such a Case may be there is no need to expand the source and drain regions to expand.

In The drawings and the description are typical embodiments of the invention, and although using specific terms they become merely general and descriptive Sense and not used for the purpose of limiting, with the scope of protection the invention is set forth in the following claims.

Claims (21)

Field effect transistor (FET) with a channel layer on sidewalls of a structure ( 400 . 410 ) on a semiconductor substrate ( 110 ) and at least a portion of the channel layer, in a first direction, in which the sidewalls of the structure of the semiconductor substrate ( 110 ), in which the transistor has a FinFET, in which the structure has a rib structure ( 400 . 410 ), and in which the side walls have side walls of the rib structure ( 400 . 410 ) and in which the rib structure ( 400 . 410 ) has a plurality of layers of different materials, wherein the alternating layers more than one layer ( 140 ) of Si and more than one layer ( 120 SiGe, further comprising: a gate dielectric ( 180 ) at the channel layer; a gate electrode ( 220 ) at a portion of the gate dielectric ( 180 ); and source and drain regions ( 300 ) at opposite sides of the gate electrode in a second direction perpendicular to the first direction (FIG. 220 ). The FET of claim 1, wherein the channel layer is a having epitaxial Si layer. FET according to claim 2, wherein the channel layer is a Thickness of less than about 10.0 nm The FET according to claim 1, wherein each of the plurality of layers ( 120 . 140 ) of different materials, an upper surface opposite and substantially parallel to the substrate ( 110 ) and a sidewall surface substantially perpendicular to the substrate (FIG. 110 ), and wherein the channel layer is directly on the sidewall surfaces of the plurality of layers (FIG. 120 . 140 ) is provided of different materials. FET according to claim 1, wherein the rib structure ( 400 . 410 ) has alternating layers of Si and SiGe. FET according to claim 5, in which the alternating layers ( 120 . 140 ) have epitaxial layers. FET according to claim 5, wherein the Si-Schich th ( 140 ) of the alternating layers ( 120 . 140 ) have a thickness of less than about 3.0 nm. FET according to claim 5, wherein the SiGe layers ( 120 ) of the alternating layers ( 120 . 140 ) have a thickness of less than about 5.0 nm. FET according to claim 5, in which an outermost layer of the alternating layers ( 120 . 140 ) has a SiGe layer. An FET according to claim 9, wherein a portion of the channel layer is located directly on the outermost surface of the alternating layers (Fig. 120 . 140 ) is arranged. FET according to claim 2, in which the source and drain regions ( 300 ) have the epitaxial Si layer. FET according to claim 1, wherein the rib structure ( 400 . 410 ) and the source and drain regions ( 300 ) comprise a plurality of layers of different materials. FET according to claim 1, wherein the rib structure ( 400 . 410 ) and the source and drain regions ( 300 ) have alternating layers of Si and SiGe. FET according to claim 13, in which the alternating layers comprise epitaxial layers ( 160 ) exhibit. FET according to Claim 1, in which the gate electrode ( 220 ) has a polysilicon layer. FET according to claim 1, further comprising a first dielectric layer ( 200 ) on the substrate ( 110 ), wherein the rib structure ( 400 . 410 ) through the first dielectric layer ( 200 ) and the channel layer at a portion of the rib structure ( 400 . 410 ) extending over the first dielectric layer ( 200 ) extends, is arranged. FET according to claim 16, wherein the rib structure ( 400 . 410 ) a portion of the substrate ( 110 ), and in which the portion of the rib structure ( 400 . 410 ) passing through the substrate ( 110 ) is not provided over the first dielectric layer ( 200 ) extends. FET according to claim 1, wherein the substrate ( 110 ) has a Si substrate. The FET of claim 1, wherein the channel layer is strained and not strained sections. FET according to claim 19, wherein the strained and non-strained portions have side walls of the channel layer. FET according to claim 1, wherein the gate dielectric ( 180 ) is formed on the sidewalls and an upper surface of the channel layer and having a sidewall and an upper surface opposite to the channel layer; and the gate electrode ( 220 ) at a portion of the sidewalls and the top surface of the gate dielectric ( 180 ) is trained.