DE102007035858A1 - Integrated circuit for use in e.g. semiconductor device, has memory cell array with spatially positioned cavities, where size of cavities are selected such that mechanical stress occurring inside array is compensated partially by cavities - Google Patents

Abstract

The circuit has a memory cell array (300) i.e. resistive memory cell array, with a set of spatially positioned cavities (302), where size of the cavities are selected such that the mechanical stress occurring inside the memory cell array is compensated partially by the cavities. The cavities are filled with a compressible material i.e. non-porous material, or a material with a negative thermal expansion coefficient i.e. zirconium tungstate. The memory cell array has an active material layer, and the cavities are arranged within the active material layer. An independent claim is also included for a method for manufacturing an integrated circuit.

Description

The The invention relates to an integrated circuit, a method for Producing an integrated circuit, a memory cell array, a memory module and a device.

Memory cell arrays generally consist of a variety of different materials. The Thermal expansion coefficients of these materials can be significant differ from each other. This can damage the memory cell array when exposed to high temperatures (delamination damage).

The The object underlying the invention is memory cell arrays from damage to preserve, from different thermal expansion coefficients result.

to solution This object is achieved by the invention integrated circuits according to claims 1 and 15 ready. Furthermore, the invention provides methods for the production integrated circuits according to patent claims 29 and 34 ready. The invention further provides memory cell arrays according to the claims 39 and 40 ready. The invention also provides memory modules according to claims 41 and 42 ready. After all the invention provides a semiconductor device according to the claim 43 ready. Advantageous embodiments or further developments of The idea of the invention can be found in the subclaims.

In The following description describes embodiments of memory cell arrays described. These apply analogously also for integrated Circuits containing memory cells.

According to one embodiment According to the invention, a device is provided which comprises a plurality of cavities having. The spatial dimensions and dimensions the cavities are chosen that in the memory cell array occurring mechanical stress through the cavities at least partially compensated. The device can be a Any device such as a motherboard of a staff Computer or any semiconductor device.

According to one embodiment The invention provides a memory cell array comprising a Plurality of cavities having. The spatial dimensions and dimensions of the cavities are chosen so that in the memory cell array occurring mechanical stress through the cavities at least partially compensated.

Memory cell arrays according to this embodiment can be exposed to strong mechanical stress as a stress compensation structure (Voids) integrated into the memory cell array, the mechanical stress compensated, for example, from high temperatures or from others influences results, which is exposed to a memory cell array. In order to the manufacturing process of the memory cell array becomes more flexible (Stress no longer needs to be considered to the same extent be taken).

According to one embodiment The invention is at least a part of at least one cavity with compressible material or material that has a negative thermal Expansion coefficient has filled.

According to one embodiment In accordance with the invention, the compressible material is more easily compressible as the materials that surround the compressible material.

According to one embodiment the invention is the compressible material nanoporous material.

The Memory cell arrays can be any type of memory cell array. For example, the Memory cell arrays are resistive memory cell arrays or nonvolatile memory cell arrays be. The invention is not limited to these examples.

in principle can the positions of the cavities chosen arbitrarily become. For example, at least a part of at least one Cavity within a layer of active material of the memory cell array be arranged. One more way is, all cavities to arrange within the layer of active material. Additionally or alternatively you can according to a embodiment the invention all cavities (or at least one cavity) within at least one dielectric Material layer may be provided. According to one embodiment The invention is the at least one dielectric material layer above an active material layer and / or an electrode layer, which is arranged above the active material layer, arranged.

According to one embodiment of the invention, the memory cell array is a programmable metallization array (PMC array), e.g. B. a solid electrolyte memory cell array random access (CBRAM cell array) comprising a layer of reactive electrodes, a layer of inert electrodes and a solid electrolyte layer which is disposed between the layer of reactive electrodes and the layer of inert electrodes. The solid state electrolyte layer is electrically connected to the layer of reactive electrodes and the layer of inert electrodes. In this embodiment, at at least one part of at least one cavity may be arranged inside the solid electrolyte layer or within the layer of inert electrodes or within the layer of reactive electrodes. The memory cell array may also include a phase change array (eg, a PCRAM array), a magnetoresistive array (eg, an MRAM array), an organic memory cell array (eg, an ORAM array), or a transition metal oxide array (TMO array).

According to one embodiment of the invention, the material having a negative thermal expansion coefficient is ZrW ₂ O ₈ (zirconium tungsten oxide). More generally, the material having a negative thermal expansion coefficient may be a compound.

According to one embodiment The invention relates to a memory cell array having a plurality of Compensation areas provided for the compensation of mechanical stress. Each stress compensation area has compressible material or Material with a negative thermal expansion coefficient on. The spatial Positions and dimensions of stress compensation areas are like this selected that mechanical stress that occurs in the memory cell area at least partially compensated by the stress compensation areas becomes.

Memory cell arrays according to this or other embodiment can be exposed to high mechanical stress as a stress compensating area integrated into the memory cell array, the mechanical stress compensated, for example, from high temperatures or from others influences results, which the memory cell array is exposed. In order to the manufacturing process of the memory cell array can be more flexible be designed. According to one embodiment The invention features at least one stress compensation area Trench structure on, at least partially with compressible Material or material that has a negative thermal expansion coefficient has, filled is. Alternatively or additionally the trench structure have a cavity structure.

in the Generally can the positions of the stress compensation regions within the memory cell array chosen arbitrarily become. For example, at least part of at least one stress compensation area within a layer of active material of the memory cell array be arranged. One more way is active all stress compensation areas within the shift To arrange materials. additionally or alternatively, at least part of at least one stress compensation area within a layer of dielectric material of the memory cell array be arranged. One more way is, all stress compensation areas within the layer dielectric To arrange materials.

If the memory cell array is a solid electrolyte memory cell array With random access (CBRAM cell array), at least a part of at least one stress compensation area within the Solid electrolyte layer or within the layer of inert electrodes or within the layer be arranged reactive electrodes.

According to one embodiment The invention is additional to the stress compensation areas within the memory cell array further provided a plurality of cavities, wherein the spatial Positions and dimensions of the cavities are chosen so that mechanical stress, which occurs within the memory cell array, at least through the cavities partially compensated.

According to one embodiment The invention relates to a method for producing a memory cell array which has the following processes: Provision a substrate; Depositing a plurality of layers on the Substrate, wherein in the plurality of layers, a trench structure is trained; overgrown the trench structure such that within the trench structure and / or cavities are formed above the trench structure.

According to one embodiment The invention includes the process of overgrowing the trench structure one (not uniform) Trenchauffüllprozess, in the trench filling material is introduced into the trench structure, wherein the Trenchauffüllprozess so executed will that overhangs of trench filling material grown on the edges of the trench structure opening area become.

According to one embodiment the invention, the Trenchauffüllprozess at least as long executed until overhangs touch each other opposite Edges of the trench structure opening area to be raised.

According to one embodiment The invention relates to a method for producing a memory cell array which has the following processes: Provision a substrate; Depositing a plurality of layers on the substrate, wherein a trench structure is formed in the plurality of layers is; and padding the trench structure with compressible material or material that has a negative thermal expansion coefficient.

According to an embodiment of the invention At least part of the trench structure is created within a plug layer that includes a plurality of plugs that contact a layer of active material or an electrode layer of the memory cell arrays.

According to one embodiment The invention becomes a back-end-of-line process carried out, after overgrowing the trench structure was, or after the trench structure with compressible material or material that has a negative thermal expansion coefficient has, filled has been.

According to one embodiment The invention is the process of monitoring the trench structure or the process of filling the trench structure with compressible material or with material, which has a negative thermal expansion coefficient, carried out at temperatures that lower than 400 ° C are to damage (eg delamination damage) within the layer of active material or within other parts of the memory cell array.

According to one embodiment of the invention, the material which has been filled into the trench structure or the material with which the trench structure has been overgrown comprises insulating material or semiconducting material, for example silicon oxide (SiO ₂ ), silicon nitride (SiN), germanium oxide (GeO). or germanium nitride (GeN).

The Invention will be described below with reference to the figures for example, embodiments explained in more detail. It demonstrate:

1A a schematic cross-sectional view of a CBRAM cell in a first memory state;

1B a schematic cross-sectional view of a CBRAM cell in a second memory state;

2 a schematic cross-sectional view of a portion of a memory cell array according to an embodiment of the invention;

3 a schematic plan view of a portion of a memory cell array according to an embodiment of the invention;

4A a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

4B a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

4C a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

5A a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

5B a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

5C a schematic cross-sectional view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

6 shows a schematic cross-sectional view of the in 4A process stage shown in detail;

7A a schematic plan view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

7B a schematic cross-sectional view of the in 7A shown process stage;

8A a schematic plan view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

8B a schematic cross-sectional view of the in 8A shown process stage;

9A a schematic plan view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

9B a schematic cross-sectional view of the in 9A shown process stage;

10A a schematic plan view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

10B shows a schematic cross-sectional view of the in 10A shown process stage;

11A shows a schematic plan view of a process stage of a method for producing a memory cell array according to an embodiment of the invention;

11B shows a schematic cross-sectional view of the in 11A shown process stage;

12 shows a schematic cross-sectional view of the in 11B shown memory cell arrays and its behavior during a high-temperature treatment;

13 shows a schematic cross-sectional view of a memory cell array, which has been damaged due to high temperatures;

14 shows a flowchart of a method for manufacturing a memory cell array according to an embodiment of the invention;

15A a memory module according to an embodiment of the invention;

15B a memory module according to an embodiment of the invention;

16 a schematic cross-sectional view of a phase change memory cell;

17 a schematic representation of a memory device with resistance change memory cells;

18A a schematic cross-sectional view of a carbon storage cell in a first memory state;

18B a schematic cross-sectional view of a carbon storage cell in a second memory state;

19A a schematic representation of a resistance change memory cell; and

19B a schematic representation of a resistance change memory cell.

In the characters can identical or corresponding areas, components or groups of components be marked with the same reference numerals. Furthermore is to mention, that the figures are schematic figures, so not to scale need to be.

Since the embodiments of the present invention are applicable to programmable metallization cells (PMCs) such as conductive bridging random access memory (CBRAM) devices, in the following description with reference to FIG 1a and 1b explaining an important principle underlying CBRAM devices.

A CBRAM cell has a first electrode 101 , a second electrode 102 and a solid electrolyte block (also known as an ion conductor block) 103 that is between the first electrode 101 and the second electrode 102 is arranged on. The solid electrolyte block may also be shared by multiple memory cells (not shown here). The first electrode 101 contacts a first surface 104 of the solid electrolyte block 103 , the second electrode 102 contacts a second surface 105 of the solid electrolyte block 103 , The solid-state electrolyte block 103 is opposite its environment by an isolation structure 106 isolated. The first surface 104 is usually the top, the second surface 105 the bottom of the solid electrolyte block 103 , The first electrode 101 is usually the upper electrode, the second electrode 102 the lower electrode of the CBRAM cell. One of the first and second electrodes 101 . 102 One is a reactive electrode, the other is an inert electrode. For example, the first electrode 101 the reactive electrode, and the second electrode 102 the inert electrode. In this case, the first electrode 101 for example, from silver (Ag), the solid electrolyte block 103 from chalcogenide material, and the isolation structure 106 consist of SiO ₂ or Si ₃ N ₄ . The second electrode 102 may alternatively or additionally nickel (Ni), platinum (Pt), iridium (Ir), rhenium (Re), tantalum (Ta), titanium (Ti), ruthenium (Ru), molybdenum (Mo), vanadium (V), may include conductive oxides, silicides, and nitrides of the aforementioned materials, and may further include alloys of the aforementioned materials. The thickness of the ion conductor block 103 may for example be 5 nm to 500 nm. The thickness of the first electrode 101 may for example be 10 nm to 100 nm. The thickness of the second electrode 102 For example, it may be 5 nm to 500 nm, 15 nm to 150 nm, or 25 nm to 100 nm. The embodiments of the invention are not limited to the above-mentioned materials and thicknesses.

According to one embodiment of the invention, chalcogenide material (more generally: the material of the ion conductor block 103 ) to understand a compound having oxygen, sulfur, selenium, germanium and / or tellurium. According to one embodiment of the invention, chalcogenide material is a compound of a chalcogenide and at least one metal of group I or group II of the periodic table, for example arsenic trisulfide silver. Alternatively, the chalcogenide material contains germanium sulfide (GeS _x ), germanium selenide (GeSe _x ), tungsten oxide (WO _x ), copper sulfide (CuS _x ) or like. Furthermore, the chalcogenide material may include metal ions, wherein the metal ions may be a metal selected from a group consisting of silver, copper, and zinc, or a combination or alloy of these metals. The ion conductor block 103 may consist of solid electrolyte material.

When a voltage across the solid electrolyte block 103 falls off, as in 1a is indicated, a redox reaction is set in motion, the Ag ⁺ ions from the first electrode 101 comes out and into the solid-state electrolyte block 103 into where they are reduced to silver. In this way, silver-containing clusters 108 in the solid electrolyte block 103 educated. When the voltage across the solid electrolyte block 103 decreases long enough, increases the size and number of silver-rich clusters within the solid electrolyte block 103 so strong that a conductive bridge (conductive path) 107 between the first electrode 101 and the second electrode 102 is trained. When the in 1b shown voltage across the solid electrolyte block 103 drops (inverse voltage compared to the in 1a shown voltage), a redox reaction is set in motion, the Ag ⁺ ions from the solid electrolyte block 103 out to the first electrode 101 drives, where they are reduced to silver. This will change the size and number of silver-rich clusters 108 within the solid electrolyte block 103 reduced. If this happens long enough, the conductive bridge becomes 107 deleted.

To determine the current memory state of the CBRAM cell, a measurement current is passed through the CBRAM cell. The measuring current experiences a high resistance when in the CBRAM cell no conductive bridge 107 is formed, and experiences a low resistance when in the CBRAM cell a conductive bridge 107 is trained. For example, a high resistance represents logic "0", whereas a low resistance logically represents "1" or vice versa. Instead of a measuring current, a measuring voltage can also be used.

2 shows an embodiment of a memory cell array according to the invention. A memory cell array 200 has a plurality of cavities / compensation areas 201 for the compensation of mechanical stress, which are embedded in the materials of the memory cell array and in their entirety by the reference numeral 202 are designated. The spatial positions and the dimensions of the cavities and / or the compensation areas 201 are chosen so that mechanical stress within the memory cell array 200 (within the memory cell array materials 202 ) occurs, at least partially through the cavities and the compensation areas 201 is compensated.

3 shows a memory cell array 300 that has a plurality of cavities 302 having the spatial positions and dimensions of the cavities 302 are chosen so that mechanical stress within the memory cell array 300 occurs, at least partially through the cavities 302 is compensated. The cavities 302 are provided, for example, within a layer of active material (not shown) that is above bottom electrodes 303 is provided (the cavities are provided, for example, between structured PL areas (PL includes the chalcogenide material and the top electrode material)). The lateral positions of the cavities 302 lie between the lateral positions of the bottom electrodes 303 , In other words: the cavities 302 lie between memory cells 304 the memory cell arrays 300 (The area of the layer of active material above a bottom electrode 303 is arranged, forms together with the bottom electrode 303 and a top electrode (not shown) disposed above the active material layer, a memory cell 304 ). At least a part of at least one cavity 302 may be filled with compressible material or material having a negative thermal expansion coefficient. The material having a negative thermal expansion coefficient may be ZrW ₂ O ₈ , for example.

If the memory cell array 300 exposed to high temperatures, for example during a temperature treatment process, expand the bottom electrodes 303 and the top electrodes (not shown) are relatively strong (compared to the other materials of the memory cell array 300 ), which means within the memory cell array 300 mechanical stress is generated. The through the bottom electrodes 303 and the top electrodes generated stress can at least partially through the cavities 302 be compensated: the spatial dimensions of the cavities 302 are reduced when the bottom electrodes 303 and the top electrodes expand, reducing the mechanical stress caused by the expansion of the bottom electrodes 303 and the top electrode is caused to be compensated.

4A shows a process stage of a method according to an embodiment of the invention. In the in 4B The process stage shown is a layer of active material 405 (for example, a chalcogenide layer) has been patterned to form a first region of active material 405 ₁ and a second area of active material 405 ₂ to obtain. After the layer of active material 405 was patterned, a Trenchauffüllprozess is performed in the Trenchfüllmaterial 406 (For example, dielectric material or semiconducting material) in a trench structure 407 filled between the first area of active material 405 ₁ and the second region of active material 405 ₂ is provided (the trench structure results from the structuring process mentioned above). For example, the trench filling process may be carried out using a chemical vapor deposition (PVD) process. The trench padding process can be performed so that overhangs 408 of trench filling material 406 on the edges 409 a Trench opening area grow. The Trenchauffüllprozess can for example be carried out until the overhangs 408 ₁ . 408 ₂ on opposite edges 409 of the trench track opening area (first opening area edge 409 ₁ and second opening area edge 409 ₂ ) grow, touching each other as in 4B is shown. In this way, a cavity 402 generated, wherein a first part of the cavity within the trench structure 407 , and a second part of the cavity above the trench structure 407 located. The Trenchauffüllprozess can for example be carried out until the cavity 402 with trench filling material 406 a certain thickness D is covered, as in 4C is shown. This ensures that the layer of trench filling material 407 not delaminated when within the trench padding material 406 a high mechanical stress occurs. Other layers may be above the trench padding material 406 be deposited, for example, during a back-end-of-line process.

5A shows the in 4C shown structure before it is subjected to a temperature treatment process (for example, at room temperature). For example, the temperature treatment process (performed during a back-end-of-line (BEOL) process), during which, for example, a temperature of 430 ° C prevails, causes the first region of active material 405 ₁ as well as the second area 405 ₂ active material vertically (indicated by the arrow "H") and laterally expand (indicated by the arrow "L"). The expansion of the first region of active material 405 ₁ and the second region of active material 405 ₂ causes mechanical stress within the structure. This mechanical stress is compensated by the spatial dimensions of the cavities 402 be reduced as in 5B is shown. Once the temperature treatment process is completed, the spatial dimensions of the first area of active material decrease 450 ₁ and the second region of active material 405 ₂ whereas the spatial dimensions of the cavity 402 be enlarged (see 5C ). In this way it is possible that the layer of active material 405 expands without the trench padding material 406 to destroy / delaminate (more generally: without a structure that includes the active material to destroy / delaminate).

6 shows that in 4A shown process stage in more detail. The first area of active material 405 ₁ and the second area of active material 405 ₂ are on a support structure 600 provided, for example, on a dielectric with bottom electrode contacts.

7A and 7B show a process stage 700 a method for manufacturing a memory cell array according to an embodiment of the invention, in which a layer of active material 701 (For example, a chalcogenide layer) on a substrate layer 702 was applied, which has a plurality of bottom electrodes 703 having.

8A and 8B show a process stage 800 in which a top electrode layer 801 on the layer of active material 701 was applied. Furthermore, it was on the top electrode layer 801 a structured mask layer 802 intended. The top electrode layer 801 can be used as a hard mask during the manufacturing process.

9A and 9B show a process stage 900 in which a trench structure 901 was generated within a composite structure, which is the top electrode layer 801 and the layer of active material 701 having. The trench structure 901 can be generated, for example, by an etching process involving the mask layer 802 used. Here, the case is shown where completely down to the substrate layer 702 is etched down. Alternatively, it may be sufficient to use only a portion of the active material layer 701 or the top electrode layer 801 to etch.

10A and 10B show a process stage 1000 in which the trench structure 901 with filling material 1001 has been filled, wherein the filler material is compressible material (for example, nanoporous material) or material having a negative coefficient of thermal expansion.

In the 11A and 11B is a process stage 1100 shown in which a dielectric layer 1101 (ILD layer) on top of the in the 10A / 10B shown structure was applied. Prior to this process, a chemical mechanical polishing (CMP) process can be performed to achieve a uniform surface.

12 shows the in the 11A and 11B shown structure during a temperature treatment process of the structure. As 12 can be taken, is mechanical stress, which is indicated by the arrows "S" (expansion of the patterned top electrode layer 801 ), through the filler material 1001 compensated, whereby the spatial dimensions of the filling material 1001 due to a negative thermal expansion coefficient or due to the compression properties of the filler 1001 reduce what is indicated by arrows "C". In this way, damage to the in 12 shown structure due to mechanical (thermal) stress prevented.

13 shows the delamination of a pile 1300 of layers that are above a Si substrate 1301 are arranged after a heat treatment process has been performed. The stack 1300 is delaminated at an interface between Si-based material and GeS ₂ -based material, leaving a gap 1302 originated. This shows possible consequences of thermal expansion.

14 shows a manufacturing method according to an embodiment of the invention. In a first process P1, a substrate is provided. In a second process P2, a plurality of layers are deposited on the substrate, the plurality of layers having a trench structure. In a third process P3, the trench structure is overgrown such that voids are generated within the trench structure or above the trench structure, and / or the trench structure is filled with compressible material or with material having a negative coefficient of thermal expansion.

As in 15A and 15B 1, embodiments of the memory arrays / integrated circuits according to the invention can be used in modules. In 15A is a memory module 1500 shown one or more memory arrays / integrated circuits 1504 which is on a substrate 1502 are arranged. Each memory array / integrated circuit 1504 can contain several memory cells. The memory module 1500 can also use one or more electronic devices 1506 comprising memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuits or electronic devices that may be combined with memory device (s) of a module, such as memory arrays / integrated circuits 1504 , Furthermore, the memory module 1500 a plurality of electrical connections 1508 which can be used to the memory module 1500 to connect with other electronic components, such as other modules.

As in 15B As shown, these modules may be stackable to form a stack 1550 train. For example, a stackable memory module 1552 one or more memory arrays / integrated circuits 1556 included on a stackable substrate 1554 are arranged. Each memory array / integrated circuit 1556 can contain several memory cells. The stackable memory module 1552 can also use one or more electronic devices 1558 which include memory, processing circuits, control circuits, address circuits, bus connection circuits, or other circuitry, and which may be combined with memory devices of a module, such as memory arrays / integrated circuits 1556 , Electrical connections 1560 are used to make the stackable memory module 1552 with other modules within the stack 1550 connect to. Other modules of the stack 1550 may be additional stackable memory modules that are the stackable memory module described above 1552 or other types of stackable modules, such as stackable processing modules, communication modules, or modules containing electronic components.

According to one embodiment of the invention the memory cells of the memory cell arrays / integrated circuits Phase change memory cells be, the phase change material exhibit. The phase change material can be switched between at least two crystallization states (i.e. H. the phase change material may assume at least two degrees of crystallization), each one Crystallization state represents a memory state. If the number of possible Crystallization states two is, becomes the crystallization state having a high degree of crystallization also known as "crystalline Condition ", where against the crystallization state, which has a low degree of crystallization also known as "amorphous State " becomes. Different crystallization states can be differentiated by corresponding different electrical properties are distinguished from each other, in particular through different resistances, which are implied by this. For example, a crystallization state, a high degree of crystallization (ordered atomic structure) generally has a lower resistance than a crystallization state, which has a low degree of crystallization (disordered atomic structure). For the sake of simplicity, it is assumed below be that phase change material two crystallization states can accept (an "amorphous State "and a" crystalline State "). However be mentioned that too extra intermediate states can be used.

Phase change memory cells can change from the amorphous state to the crystalline state (and vice versa) when temperature fluctuations within the phase change material. Such temperature changes can be caused in different ways. For example, a current may be passed through the phase change material (or a voltage may be applied to the phase change material). Alternatively, a current or voltage may be supplied to a resistance heating element provided adjacent to the phase change material. In order to set the memory state of a resistance change memory cell, a sense current may be passed through the phase change material (or a sense voltage may be applied to the phase change material), thereby measuring the resistance of the resistance change memory cell representing the memory state of the memory cell.

16 shows a cross-sectional view of an exemplary phase change memory cell 1600 (Active-in-via type). The phase change memory cell 1600 has a first electrode 1602 , Phase change material 1604 , a second electrode 1606 as well as insulating material 1608 on. The phase change material 1604 becomes lateral through the insulating material 1608 locked in. A selection device (not shown) such as a transistor, a diode or other active device may be connected to the first electrode 1602 or the second electrode 1606 be coupled to the application of the phase change material 1604 with current or voltage using the first electrode 1602 and / or the second electrode 1606 to control. To the phase change material 1604 into the crystalline state, the phase change material 1604 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 1604 above the phase change material crystallization temperature, but kept below the phase change material melting temperature. If the phase change material 1604 is to be converted into the amorphous state, the phase change material 1604 be subjected to a current pulse and / or a voltage pulse, wherein the pulse parameters are selected so that the temperature of the phase change material 1604 rises rapidly above the phase change material melting temperature, with the phase change material 1604 then cooled quickly.

The phase change material 1604 can contain a variety of materials. According to one embodiment, the phase change material 1604 comprise (or consist of) a chalcogenide alloy containing one or more elements of group VI of the periodic table. According to a further embodiment, the phase change material 1604 Comprise or consist of clalcogenide composite material such as GeSbTe, SbTe, GeTe or AbInSbTe. According to a further embodiment, the phase change material 1604 comprise or consist of a chalcogen-free material, such as GeSb, GaSb, InSb, or GeGaInSb. According to a further embodiment, the phase change material 1604 comprise or consist of any suitable material comprising one or more of Ge, Sb, Te, Ga, Bi, Pb, Sn, Si, P, O, As, In, Se, and S.

According to one embodiment of the invention, at least one of the first electrode 1602 and the second electrode 1606 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or mixtures or alloys thereof (or consist thereof). According to a further embodiment, at least one of the first electrode 1602 and the second electrode 1606 Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W and two or more elements of the group: B, C, N, O, Al, Si, P, S and / or mixtures and alloys thereof (or consist of this). Examples of such materials are TiCN, TiAlN, TiSiN, W-Al ₂ O ₃ , and Cr-Al ₂ O ₃ .

17 shows a block diagram of a memory device 1700 containing a write pulse generator 1702 , a distribution circuit 1704 , Phase change memory cells 1706a . 1706b . 1706c . 1706D (For example, phase change memory cells 1600 as in 16 shown) and a sense amplifier 1708 having. According to one embodiment, the write pulse generator generates 1702 Current pulses or voltage pulses representing the phase change memory cells 1706a . 1706b . 1706c . 1706D by means of the distribution circuit 1704 whereby the storage states of the phase change memory cells 1706a . 1706b . 1706c . 1706D be programmed. According to one embodiment, the distribution circuit 1704 a plurality of transistors connecting the phase change memory cells 1706a . 1706b . 1706c . 1706D or heating elements adjacent to the phase change memory cells 1706a . 1706b . 1706c . 1706D are provided to supply DC pulses or DC pulses.

As already indicated, the phase change material of the phase change memory cells 1706a . 1706b . 1706c . 1706D from the amorphous state to the crystalline state (or vice versa) by changing the temperature.

More generally, the phase change material can be converted from a first degree of crystallization to a second degree of crystallinity due to a temperature change. For example For example, the bit value "zero" may be assigned to the first (low) degree of crystallization, and the bit value "1" to the second (high) degree of crystallization. Since different degrees of crystallization imply different electrical resistances, the sense amplifier is 1708 capable of storing one of the phase change memory cells 1706a . 1706b . 1706c or 1706D depending on the resistance of the phase change material to determine.

In order to achieve high storage densities, the phase change memory cells 1706a . 1706b . 1706c and 1706D be designed to store several bits of data (ie the phase change material can be programmed to different resistance values). For example, if a phase change memory cell 1706a . 1706b . 1706c and 1706D is programmed to one of three possible resistance levels, 1.5 data bits per memory cell are stored. If the phase change memory cell is programmed to one of four possible resistance levels, two bits of data per memory cell can be stored, and so on.

In the 17 The illustrated embodiment may similarly be applied to other resistance change memory elements such as programmable metallization cells (PMCs), magnetoresistive memory cells (eg, MRAMs), organic memory cells (eg, ORAMs), or transition metal oxide memory cells (TMOs).

Another type of memory cell that can be used is to use carbon as a resistance change material. In general, amorphous carbon rich in sp ³ -hybridized carbon (ie, tetrahedral bonded carbon) has high resistance, whereas amorphous carbon rich in sp ² -hybridized carbon (i.e., trigonal-bonded carbon) has low resistance , This resistance difference can be utilized in resistance change memory cells.

According to one embodiment of the invention, a carbon memory cell is formed in a similar manner as described above in connection with the phase change memory cells. A temperature-induced change between an sp ³ -rich state and an sp ² -rich state can be used to change the resistance of amorphous carbon material. These varying resistances can be used to represent different memory conditions. For example, an sp ³ rich state (high resistance state) may represent "zero", and an sp ² rich state (low resistance state) may represent "one". Intermediate resistance states can be used to represent multiple bits as described above.

In this type of carbon storage cell, the use of a first temperature generally causes a transition that converts sp ³ -rich amorphous carbon into sp ² -rich amorphous carbon. This transition can be reversed by the application of a second temperature, which is typically higher than the first temperature. As mentioned above, these temperatures may be generated by, for example, charging the carbon material with a current pulse and / or a voltage pulse. Alternatively, the temperatures may be generated using a resistance heating element provided adjacent to the carbon material.

Another way to utilize resistance changes in amorphous carbon to store information is the field strength induced formation of a conductive path in an insulating amorphous carbon film. For example, applying a voltage pulse or current pulse may cause the formation of a conductive sp ² filament in insulating, sp ³ -rich amorphous carbon. The operation of this resistance carbon storage type is described in FIGS 18A and 18B shown.

18A shows a carbon storage cell 1800 who have a top contact 1802 a carbon storage layer 1804 with insulating amorphous carbon material rich in sp ³ -hybridized carbon atoms and a bottom contact 1806 having. As in 18B can be shown by means of a current (or voltage) passing through the carbon storage layer 1804 is passed, an SP ² filament 1850 in the sp ³ -rich carbon storage layer 1804 are formed, whereby the resistance of the memory cell is changed. Applying a high energy (or reverse polarity) current pulse (or voltage pulse) may be the sp ² filament 1850 destroy what the resistance of the carbon storage layer 1804 is increased. As discussed above, the changes in resistance may be to the carbon storage layer 1804 be used to store information, for example, representing a high resistance state "zero", and a low resistance state "one". Additionally, in some embodiments, intermediate levels of filament formation or formation of multiple filaments in sp ³ -rich carbon films may be used to provide multiple varying levels of resistance, thus providing more information in a carbon memory cell onbits are storable. In some embodiments, alternating sp ³ -rich carbon layers and sp ² -rich carbon layers may be employed, wherein the sp ³ -rich layers excite conductive filament formation, such that the currents and / or voltages used to write a value into this carbon storage type be used, can be reduced.

The resistance change memory cells such as the phase change memory cells and the carbon memory cells described above may be provided with a transistor, a diode or other active element for selecting the memory cell. 19A shows a schematic representation of such a memory cell using a resistance change memory element. The memory cell 1900 has a selection transistor 1902 and a resistance change memory element 1904 on. The selection transistor 1902 has a source section 1906 that with a bit line 1908 is connected, a drain section 1910 that with the memory element 1904 connected, and a gate section 1912 that with a wordline 1914 is connected. The resistance change memory element 1904 is still with a common line 1916 which may be grounded or connected to another circuit, such as a circuit (not shown) for determining the resistance of the memory cell 1900 what can be used in reading operations. Alternatively, in some configurations, a circuit (not shown) for determining the state of the memory cells 1900 during the read operation with the bit line 1908 be connected.

When in the memory cell 1900 will be described, the word line 1914 for selecting the memory cell 1900 used, and the resistance change memory element 1904 is done with a current pulse (or voltage pulse) using the bit line 1908 applied, whereby the resistance of the resistance change memory element 1904 will be changed. Similarly, when out of the memory cell 1900 is read, the word line 1914 used the cell 1900 and the bit line 1908 is used to change the resistance change memory element 1904 to apply a read voltage or a read current to the resistance of the resistance change memory element 1904 to eat.

The memory cell 1900 may be referred to as a 1T1J cell because it includes a transistor and a memory transition (the resistance change memory element 1904 ) uses. Typically, a storage device comprises an array having a plurality of such cells. Instead of a 1T1J memory cell, other configurations may be used. For example, in 19B an alternative construction of a 1T1J memory cell 1950 shown in which a selection transistor 1952 and a resistance change memory element 1954 are arranged in a different way compared to that in 19A shown construction. In this alternative construction, the resistance change storage element is 1954 with a bit line 1958 as well as with a source section 1956 of the selection transistor 1952 connected. A drain section 1960 of the selection transistor 1952 is with a common line 1966 which may be grounded or connected to another circuit (not shown) as discussed above. A gate section 1962 of the selection transistor 1952 is by means of a wordline 1964 controlled.

In The following description is intended to provide further aspects of example embodiments of the invention explained become.

The Invention relates to u. a. producing non-volatile memory, For example, the manufacture of conductive bridging (CB) RAMs. The concept of this type of memory is based on the generation or the To destroy of cable bridges, formed by a metal within a chalcogenide glass matrix be when a tension that is greater than a certain one Threshold voltage applied to make the bridge or larger (more negative) as a certain negative voltage threshold is to the bridge to delete. The stored in this bridge Information can be read with the aid of an intermediate voltage become. Compared to available Technologies (eg DRAM, Flash) will be a continuous one Scalability down to very small feature sizes simultaneous non-volatility, faster programming and low power consumption.

At present becomes for the formation of the cable bridges For example, the metal silver (Ag) used as this metal a high mobility within has the matrix and thus the production of very fast switching memory allows. As for chalcogenide materials, for example, in particular Barium sulfide compounds or germanium selenide compounds usable.

However, when using silver (Ag), selenium (Se) and sulfur (S) based materials, the relatively large thermal expansion coefficients must be taken into account, as can be seen from the following expansion coefficient list: Ge 6.0 10 ^-6 / K Ag 19.0 10 ^-6 / K S 36.0 10 ^-6 / K SiO ₂ 0.5 10 ^-6 / K Si ₃ N ₄ 3.3 10 ^-6 / K

Since the thermal expansion coefficients of standard interlayer dielectrics (ILD) materials such as silicon oxide (SiO ₂ ) or silicon nitride (SiN) significantly differ from the thermal expansion coefficients of silver (Ab), selenium (Se), sulfur ( S) or similar materials, arises during the heat treatment process mechanical stress.

According to one embodiment The invention is a perforated ("cheese-shaped") active material plate formed in place of a continuous active material plate. Around to enable this can be an extra Lithography step be required. This can be used to define areas within which the etching / "holes" should be performed. To this In a manner, cavities are introduced into the CBRAM cell areas.

The etching (more generally: "holes") does not necessarily have the entire Etch plate material / active material. A balance of active material and / or Plate (top electrode) may remain between the cells after etching. After the "punching" process, a film deposition process can be carried out by which the trenches within the individual CBRAM cells are overgrown. This process can be, for example, a CVD process (or a physical process) Dampfabscheideverfahren PVD). The material to be deposited can For example, a dielectric material or a semiconducting Be material.

To In this process, a standard Back - End Of Line (BEOL) process is performed producing one or more metal layers, dielectric Layers, metallic contacts and a final encapsulation having.

storage devices can a whole (continuous) plate of active CBRAM material with a common metal contact on one side and individual via contacts on the other side of the active material. by virtue of the significant thermal expansion of the above-mentioned materials can Delamination effects or other general material effects during the Integration processes are the result, which are carried out at elevated temperatures and after the deposition of the active material are used.

According to one embodiment of the invention, a holey active material is used instead of a continuous material. The holes of the patterned active material are filled with nanoporous material that is easily compressible or filled with a material that has a negative coefficient of thermal expansion, such as ZrW ₂ O ₈ . According to one embodiment of the invention, stacked levels of active CBRAM material are employed. The patterning to create the holes may be limited to a portion of the active material stack.

100

CBRAM cell

102

first electrode

102

second electrode

103

Solid electrolyte

104

first surface

105

second surface

106

isolation structure

107

jumper

200

Memory cell array

201

compensation region

202

Memory cell array Material

300

Memory cell array

302

cavity

303

bottom electrode

304

memory cell

405

Active material layer

406

Trenchauffüllmaterial

407

trench structure

108

overhang

409

edge

700

process stage

701

Active material layer

702

substrate layer

703

bottom electrode

800

process stage

801

top electrode

802

mask layer

900

process stage

901

trench structure

1000

process stage

1001

Trenchauffüllmaterial

1100

process stage

1101

dielectric

1300

stack

1301

Si substrate

1301

gap

1500

memory module

1502

substratum

1504

integrated Circuit / memory device

1506

electronic contraption

1508

electrical connection

1550

stack

1552

memory module

1554

substratum

1556

storage device

1558

electronic contraption

1560

electrical connection

1600

Phase change memory cell

1602

first electrode

1604

Phase change material

1606

second electrode

1608

insulating material

1700

storage device

1702

Write pulse generator

1704

distribution circuit

1706

Phase change memory cells

1708

sense amplifier

1800

Carbon memory cell

1802

top contact

1804

Carbon storage layer

1806

bottom Contact

1850

filament

1900

memory cell

1902

selection transistor

1904

Resistance change memory element

1906

source

1908

bit

1910

drain

1912

gate

1914

wordline

1916

common management

1950

memory cell

1952

selection transistor

1954

Resistance change memory element

1956

source

1958

bit

1960

drain

1962

gate

1964

wordline

1966

common management

Claims (43)

Integrated circuit, which is a memory cell array with a plurality of cavities having the spatial Positions and dimensions the cavities so chosen are that occurring within the memory cell array mechanical stress is at least partially compensated by the cavities. An integrated circuit according to claim 1, wherein at least a cavity with compressible material or material with a negative thermal expansion coefficient is filled. An integrated circuit according to claim 2, wherein said compressible material nanoporous Material is. Integrated circuit according to one of claims 1 to 3, wherein the memory cell array is a resistive memory cell array is. Integrated circuit according to one of claims 1 to 4, wherein the memory cell array is a nonvolatile memory cell array is. Integrated circuit according to one of claims 1 to 5, wherein the memory cell array has an active material layer, wherein at least a part of at least one cavity within the Active material layer is arranged. An integrated circuit according to claim 6, wherein all cavities are provided within the active material layer. Integrated circuit according to one of claims 1 to 6, with all cavities are provided within at least one dielectric material layer. An integrated circuit according to claim 8, wherein all cavities provided within at least one dielectric material layer are those above an active material layer and / or an electrode layer, which is arranged above the active material layer, arranged is. Integrated circuit according to one of claims 1 to 9, wherein the memory cell array is a solid state electrolyte memory cell array with random access, that is a reactive electrode layer, an inert electrode layer and a solid electrolyte layer, between the reactive electrode layer and the inert electrode layer is arranged, wherein the solid electrolyte layer with the reactive electrode layer and the inert electrode layer is electrically connected. An integrated circuit according to claim 10, wherein at least a part of at least one cavity within the solid electrolyte layer or within the inert electrode layer or within the reactive electrode layer is provided. Integrated circuit according to Claim 10 or 11, wherein at least a portion of at least one cavity within a dielectric layer is arranged, which is above the solid electrolyte layer located. Integrated circuit according to one of claims 1 to 12, wherein at least a portion of a cavity is filled with material, which has a negative thermal expansion coefficient, wherein the material has a compound. The integrated circuit of claim 13, wherein the material having a negative thermal expansion coefficient is ZrW ₂ O ₈ . Integrated circuit comprising a memory cell array having a plurality of compensation regions for compensating mechanical Stress, wherein each stress compensation area comprises compressible material or material having a negative thermal expansion coefficient, and wherein the spatial positions and dimensions of the stress compensation areas are selected such that mechanical stress occurring within the memory cell array is at least partially compensated by the stress compensation areas. An integrated circuit according to claim 15, wherein said compressible material nanoporous Material is. Integrated circuit according to Claim 15 or 16, characterized wherein the memory cell array is a resistive memory cell array is. Integrated circuit according to one of Claims 15 to 17, wherein the memory cell array is a non-volatile memory cell array is. Integrated circuit according to one of Claims 15 to 18, wherein at least one compensation region has a trench structure wherein the trench structure is at least partially compressible Material or material that has a negative thermal expansion coefficient has, is filled. Integrated circuit according to one of claims 15 to 18, wherein the memory cell array has an active material layer, wherein at least a part of at least one compensation area is provided within the active material layer. The integrated circuit of claim 20, wherein all Compensation areas provided within the active material layer are. Integrated circuit according to one of Claims 15 to 20, wherein at least a part of the compensation areas within a dielectric material layer are provided above the active material layer is provided. Integrated circuit according to one of Claims 15 to 22, wherein the memory cell array is a programmable metallization cell array having. Integrated circuit according to one of Claims 15 to 23, wherein the memory cell array is a solid electrolyte memory cell array with random access, which is a reactive electrode layer, a Inert electrode layer and a solid-state electrode layer, the between the reactive electrode layer and the inert electrode layer is arranged, wherein the solid electrolyte layer with the Reactive electrode layer and the inert electrode electrically connected is. The integrated circuit of claim 24, wherein at least a part of at least one compensation area within the solid electrolyte layer or within the inert electrode layer or within the reactive electrode layer is provided. Integrated circuit according to one of Claims 15 to 25, wherein the memory cell array comprises a phase change memory cell array. Integrated circuit according to one of Claims 15 to 26, with a plurality of cavities whose spatial Positions and dimensions are chosen so that within the Memory cell arrays occurring at least mechanical stress partly through the cavities is compensated. The integrated circuit of any one of claims 15 to 27, wherein the material having a negative thermal expansion coefficient is ZrW ₂ O ₈ . Method for producing an integrated circuit, having a memory cell array with: Providing a substrate, - Separate a plurality of layers on the substrate, wherein the layers have a trench structure, - Overgrowth of the trench structure such that within the trench structure and / or above the trench structure cavities be generated. The method of claim 29, wherein the process of overgrowth the trench structure includes a trench padding process in which Trenchauffüllmaterial filled in the trench structure being, the trench replenishment process so executed will that overhangs of Trenchauffüllmaterial on the edges of the trench structure opening area grow up. The method of claim 30, wherein the trench replenishment process run so long until overhangs, the on opposite sides Edges of the trench structure opening area grow up, touch each other. A method according to any one of claims 29 to 31, wherein at least a part of the trench structure within an active material layer the memory cell array is generated. A method according to any one of claims 29 to 32, wherein at least a part of the trench structure within a dielectric material layer the memory cell array is generated. A method of fabricating an integrated circuit having a memory cell array, comprising the following processes: Providing a substrate, depositing a plurality of layers on the substrate, wherein a trench structure is formed in the layers, filling the trench structure with compressible material or material having a negative thermal expansion coefficient. The method of claim 34, wherein at least one Part of the trench structure within an active material layer of the Memory cell arrays is generated. A method according to claim 34 or 35, wherein at least a part of the trench structure within a dielectric material layer the memory cell array is generated. Method according to one of claims 34 to 36, with a back-end-of-line process, the one after the overgrowth the trench structure or after filling the trench structure with compressible material or material that has a negative thermal expansion coefficient has executed becomes. Method according to one of claims 34 to 37, wherein the in filled the trench structure Material is insulating material or semiconductive material. Memory cell array having a plurality of cavities, being the spatial Positions and dimensions the cavities so chosen are that occurring within the memory cell array mechanical Stress is at least partially compensated by the cavities. Memory cell array, which has a plurality of compensation areas to compensate for mechanical stress, - in which each stress compensating area compressible material or material, which has a negative thermal expansion coefficient, has, and - in which the spatial Positions and dimensions the stress compensation areas are chosen so that within the Memory cell arrays occurring at least mechanical stress partially compensated by the stress compensation areas. Memory module, with a memory cell array, the a plurality of cavities having the spatial Positions and dimensions the cavities so chosen are that occurring within the memory cell array mechanical Stress is at least partially compensated by the cavities. Memory module, with a memory cell array, the a plurality of compensation regions for compensating mechanical Has stress, - in which each stress compensating area compressible material or material, which has a negative thermal expansion coefficient, has, and - in which the spatial Positions and dimensions the stress compensation areas are chosen so that within the Memory cell arrays occurring at least mechanical stress partially compensated by the stress compensation areas. Semiconductor device having a plurality of cavities, wherein the spatial Positions and dimensions the cavities so chosen are that occurring within the memory cell array mechanical Stress is at least partially compensated by the cavities.