DE102008034346B4 - Method for accessing a memory chip - Google Patents

Abstract

Method for accessing a memory chip (200), characterized by: positioning a plurality of first input pins (PIN_R0, PIN_R1, PIN_R2, PIN_R3, PIN_R4, PIN_R5) and a plurality of second input pins (PIN_C0, PIN_C1, PIN_C2, PIN_C3, PIN_C4) the memory chip (200); respective input of a plurality of row address signals (RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5) into the plurality of first input pins (PIN_R0, PIN_R1, PIN_R2, PIN_R3, PIN_R4, PIN_R5), whereby a length of a row address command packet (each row address command packet , RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5) corresponds to a plurality of clock periods of a clock signal (CLK); and respectively inputting a plurality of column address signals (ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4) into the plurality of second input pins (PIN_C0, PIN_C1, PIN_C2, PIN_C3, PIN_C4), wherein a length of a column address command packet of each column address signal (ColAdr0, ColAdr2, ColAdr3, ColAdr4) corresponds to a plurality of clock periods of a clock signal (CLK).

Description

The present invention relates to a method for accessing a memory chip according to the preamble of claim 1.

With respect to the prior art synchronous double data rate (SDRAM) DRAM (SDRAM) architecture, an SDRAM typically has the following input signals: two clock signals, i. H. CLK and #CLK, sixteen memory address input signals A0-A15, four memory bank address input signals B0-BA3, a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, a sync signal CKE , a calibration signal ZQ and a reset signal RESET. The length of an input command of each input signal mentioned above corresponds to one clock period of a clock signal, and each input signal is input to a memory chip via its own pin dedicated to the input signal. Therefore, the memory chip of the prior art SDRAM typically has twenty-nine input pins.

In the prior art double-row memory device (DIMM), two adjacent memory chips having twenty-nine electrical wirings are connected to each other. Generally speaking, the more input pins the memory chip has, the closer the distance between two electrical wirings, thereby causing increased problems of the layout of the electrical wirings and increased interference between the signals transmitted through the electrical wirings. Therefore, the layout of the DIMMs is problematic because of these disadvantages. In terms of testing the memory chips running as DIMMs, the tooling cost seems to be too high and the number of memory chips that a testing station can test seems to be insufficient.

From the document US Pat. No. 6,067,632 A For example, a memory unit is known, which has a control unit, by means of which an internal operation command signal is generated, and a shift register, by means of which the operation command signal is provided only after the lapse of a predetermined time of an internal circuit.

From the document US 5,870,350 A a memory bus system is known by means of which input commands can be separated from data. As a result, several data operations can be carried out in parallel by means of this memory bus system.

From the document US Pat. No. 6,236,251 B1 a semiconductor chip with an integrated circuit is known, wherein the integrated circuit comprises two synchronization circuits, each of which is adapted to receive a clock signal and to output a synchronized with the respective received clock signal another clock signal.

Against this background, it is an object of the invention to provide a method for accessing a memory chip, which can reduce the number of input pins of a memory chip.

The solution of this object is achieved by the features of claim 1, the dependent claims disclose preferred developments of the invention.

As will be more clearly apparent from the following detailed description, the claimed method of accessing a memory comprises the steps of: positioning a plurality of first input pins and a plurality of second input pins on the memory chip; Inputting a corresponding plurality of row address signals into the plurality of first input pins, wherein a length of a row address command packet of each row address signal corresponds to a plurality of clock periods of a clock signal, and the row address command packet has a plurality of row input commands; and inputting a corresponding plurality of column address signals to the plurality of second input pins, wherein a length of a column address command packet of each column address signal corresponds to a plurality of clock periods of a clock signal and the column address command packet has a plurality of column input commands.

Further details, features and advantages of the invention will become apparent from the following description of exemplary embodiments with reference to the drawings.

It shows:

1 an illustration illustrating a prior art double row memory device (DIMM),

2 an illustration illustrating a memory chip according to an embodiment of the present invention,

3 an illustration illustrating six row address signals according to an embodiment of the present invention;

4 an illustration illustrating five column address signals according to an embodiment of the present invention, and

5 a figure illustrating an exemplary process of accessing the in 2 illustrated memory chip illustrated.

It will open 1 Referenced. 1 FIG. 13 is a diagram illustrating a prior art double row memory device (DIMM). FIG. As in 1 shown, the DIMM points 100 eight memory chips 110_1 - 110_8 on and each memory chip has twenty-nine input pins. Regarding the working process of the DIMM 100 become the twenty-nine input signals from a control unit 120 on the memory chip 110_1 then the input signals are successively transferred to the memory chip 110_2 . 110_3 , ..., 110_8 transfer. Therefore, two adjacent memory chips having twenty-nine wirings are connected together. Generally speaking, the more input pins the memory chip has, the closer the distance between two electrical wirings, thereby causing increased problems of the layout of the electrical wirings and increased interference between the signals transmitted through the electrical wirings.

In the prior art DDR SDRAM architecture, a length of an input command of each input signal corresponds to one clock period of a clock signal, and each input signal is input to a memory chip through its own pin. Therefore, the prior art memory chip has twenty-nine input pins. To reduce the number of input pins, the present invention uses the concept of the "instruction packet". That is, each PIN is used to receive a command packet, and the command packet has a plurality of input commands, such as a command packet. For example, four input commands. As a result, the number of input pins of a memory chip installed according to the invention can be reduced. However, because each command packet has four input commands and the length of an input command corresponds to one clock period, the length of a command packet is equal to four clock periods. In the working process of the memory, the row address signal and the column address signal can not be simultaneously input to the same memory bank. Thus, if the instruction packet whose length is four clock periods is used, it is necessary in the conventional architecture to wait for four clock periods after the row address signal is input to a memory bank, and then the column address signal can be input to the same memory bank, which is a serious one Deterioration of the performance of the memory caused.

Therefore, the present invention provides a method that reduces the number of input pins of a memory chip without seriously degrading the performance of the memory. The working process is described as follows.

It will open 2 Referenced. 2 is an illustration showing a memory chip 200 illustrated according to an embodiment of the invention. As in 2 shown, the memory chip 200 a clock pin PIN_CLK, six row address signal pins PIN_R0-PIN_R5, five column address signal pins PIN_C0-PIN_C4, a first chip select signal pin PIN_CSr for a chip select signal, such as a pin select signal PIN_CSr; A row address chip select signal, and a second chip select signal pin PIN_CSC for a chip select signal, such as a chip select signal. A column address chip select signal. In this embodiment, the clock signal pin PIN-CLK is used to receive a clock signal CLK, the row address signal pins PIN_R0-PIN_R5 are used to receive the column address signal pins corresponding to six row address signals RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5 PIN_C0-PIN_C4 are used to receive correspondingly five column address signals ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4, the first chip select signal pin PIN_CSR (ie, the row address chip select signal pin) is used to generate a first chip select signal CSR to receive the memory chip 200 to receive the row address signals, and the second chip select signal pin PIN_CSC (ie, the column address chip select signal pin) is used to receive a second chip select signal CSC to the memory chip 200 to receive the column address signals. Note that the on the in 2 illustrated memory chip 200 Positioned pins are for illustrative purposes only. Without affecting the disclosure of the present invention, FIG 2 moreover, only a portion of the pins with respect to a further description of the present invention. In practice, the memory chip according to the invention 200 not limited to the same as in 2 have shown pin arrangement. The access operations of the memory chip 200 are described below.

It will open 3 Referenced. 3 FIG. 12 is an illustration illustrating six row address signals according to one embodiment of the invention. FIG. In the present invention, the six row address signals RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5 are input to the memory chip via the six first input pins (ie, the row address signal pins PIN_R0-PIN_R5). As in 3 1, the length of a row address command packet of each row address signal corresponds to four clock periods of the clock signal CLK and the row address signal. Command package has four row input commands. Therefore, the six row address command packets of the six row address signals have twenty-four input commands. In this embodiment, the twenty-four row input commands include four pieces of memory address setting information BA0-BA3, sixteen pieces of memory address setting information A0-A15, and four pieces of memory control command setting information CMD0-CMD3, the four pieces of memory bank address setting information BA0- BA3 may be implemented to replace the memory bank address inputs BA0-BA3 in the prior art DDR SDRAM architecture, and the sixteen pieces of memory address setting information A0-A15 are implemented to provide the memory address input signals A0-A15 to replace the DDR SDRAM architecture of the prior art. Moreover, the four pieces of the memory control command setting information CMD0-CMD3 are decoded to generate a control command from a plurality of memory control commands, the memory control commands being an activate command, a pre-charge command, a refresh command , a mode register set (MRS) command, a self refresh entry (SRE) command, a power down entry command, a ZQ calibration long / ZQ calibration short (ZQCU / ZQCS) command, ..., etc.

It will open 4 Referenced. 4 FIG. 12 is an illustration illustrating five column address signals according to one embodiment of the invention. FIG. In the present invention, the five column address signals ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4 are applied across the five second input pins (ie, the in 2 shown column address signal pins PIN_C0-PIN_C4) entered into the memory chip. As in 4 1, the length of a column address command packet of each column address signal corresponds to four clock periods of the clock signal CLK, and the column address command packet has four column input commands. Therefore, the five column address command packets of the five column address signals have twenty column input commands. The twenty column input commands have four pieces of setting information for the memory bank addresses BA0-BA3, thirteen pieces of setting information for the memory addresses A0-A12, a write-enable (WE) input command, an auto-pre-charge (AP) input command, and a Burst-Chop 4 / Burst-Length 8 (BC4 / BC8) input command. The four pieces of bank address setting information BA0-BA3 are implemented to replace the bank address input signals BA0-BA3 in the prior art DDR SDRAM architecture, and the thirteen pieces of the memory address setting information A0-A12 are implemented to replace the memory address input signals A0-A12 in the prior art DDR SDRAM architecture.

It should be noted that the input instructions of the six row address command packets of the six row address signals are for illustrative purposes only. In practice, the twenty-four row input commands can be rearranged and the twenty in 4 The column input commands shown may also be rearranged without affecting the working process of the memory chip of the present invention. For example, the positions of any two input commands may be interchanged and the positions of any two column input commands may also be interchanged. In another example, the positions of the row input commands may be changed in rotation and the positions of the column input commands may also be changed in cycles. In addition, the number of the above-mentioned row address signals (RowAdr0-RowAdr5), the number of the above-mentioned column address signals (ColAdr0-ColAdr4), and the number of pieces of setting information for the bank addresses (BA0-BA3) are for illustrative purposes only. When the memory capacity of the memory is increased (ie, the number of pieces of setting information of the memory addresses is increased or the number of memory banks is increased), in practice, seven or more row address signals may be used and six or more column address signals may be used. The memory chip 200 can z. B. also have a row address signal pin PIN_R6 and a column address signal pin PIN_C5, wherein the row address signal pin PIN_R6 is used to receive a row address signal RowAdr6, and a row address command packet of the row address signal RowAdr6 has two pieces of setting information for the bank addresses BA4, BA5 and two pieces of setting information for the memory addresses A16, A17; and a column address command packet of the column address signal ColAdr5 has two pieces of setting information for the bank addresses BA4, BA5 and two pieces of setting information for the memory addresses A13, A14. Since the row address (column address) command packet of this embodiment has four row (column) input commands, as mentioned above, adding only one additional row address signal pin and only one additional column address signal pin in a variation of this embodiment may include four parts of the Add setting information for the bank address or memory address. As a result, the trial costs for the memory chip can be reduced.

As mentioned above, both the row address signals and the column address signals have the setting information for the memory addresses (A0, A1, ..., etc.), and therefore, different memory banks can be operated at the same time. 5 is an illustration that illustrates an exemplary process of accessing the in 2 illustrated memory chip illustrated. As in 5 At time T1, six row address command packets of the six row address signals RowAdr0-RowAdr5 are used to form a first memory bank of the memory chip 200 At the same time, five column address command packets of the five column address signals ColAdr0-ColAdr4 are used for writing in a second memory bank (if the second memory bank is activated). At a time T2, six row address command packets of the six row address signals RowAdr0-RowAdr5 are used to activate a third memory bank. At a time T3, five column address command packets of the five column address signals ColAdr0-ColAdr4 are used to read the first memory bank. Thereby, the performance deterioration of the memory due to the instruction packet whose length is four clock periods can be reduced.

In the DDR SDRAM architecture of the prior art, many parameters such. For example, the RAS-to-RAS delay time tRRD, the RAS pre-charge time tRP, the RAS-to-CAS Deley time tRCD, the row cycle time tRC, ..., u. s. w., prescribed values. When the clock period of the memory is equal to 1.25 nanoseconds, the lengths of the row address command packet and column address command packet provided by the present invention are equal to 5 nanoseconds, which can be used to accomplish the related operations of the prior art DDR SDRAM architecture to adequately replace the technique without violating the prescribed values of the associated parameters. For example, the RAS pre-charge time tRP is at least 10 nanoseconds and is identical to the length of two row address command packets. That is, a length of an interval between a pre-charge operation and an activation operation of a memory bank is identical to the length of the row address command packet. Therefore, the performance of the memory is not affected.

In addition, the prior art DDR SDRAM architecture has a chip select signal that is used to unlock a memory chip. In the present invention, since both the six row address signals and the five column address signals have the setting information for the memory addresses, the present invention further includes a first chip select signal CSR (ie, the row address chip select signal) used to enable the memory chip. to receive the row address signals, and a second chip select signal CSC (ie, the column address chip select signal) used to enable the memory chip to receive the column address signals. The row address chip select signal CSR and the column address chip select signal CSC via a third input pin (ie, the first in 1 represented chip selection signal pin PIN_CSR) and a fourth input pin (ie the second in 1 illustrated chip select signal pin PIN_CSC) are input to the memory chip. If, as in 5 2, the row address chip select signal CSR or the column address chip select signal CSC is in an enabled state, the memory chip may receive the row address signals or the column address signals.

The above-described method of accessing the memory chip will be briefly summarized. In the embodiment of the present invention, the lengths of the six row address command packets of the six row address signals are identical to four clock periods, and each row address command packet has four row input commands; and the lengths of the five column address command packets of the five column address signals are identical to four clock periods and each column address command packet has four column input commands. If one of the above-mentioned eleven address input signals, the two clock signals CLK and #CLK, the row address chip selection signal CSR, the column address chip selection signal CSC, an on-the-termination signal ODT, a synchronous signal CKE, a calibration When the signal ZQ and a reset signal RESET are added together, the method for accessing the memory chip provided by the embodiment of the invention requires nineteen input signals. That is, the memory chip requires only nineteen input pins. In contrast to the prior art memory chip with twenty-nine input pins, the present invention actually reduces the input pins of the memory chip. Therefore, the layout of the DIMM is simpler and the trial cost can also be reduced.

In summary:
The present invention provides a method of accessing a memory chip. The method includes the steps of: positioning a plurality of first input pins and a plurality of second input pins on the memory chip; respectively inputting a plurality of row address signals into the plurality of first input pins, wherein a length of a row address command packet of each row address signal corresponds to a plurality of clock periods of a clock signal and the row address command packet comprises a plurality of row input commands; and respectively inputting a plurality of column address signals into the plurality of second input pins, wherein a length of a column address command packet of each column address signal corresponds to a plurality of clock periods of a clock signal and the column address command packet comprises a plurality of column input commands.

LIST OF REFERENCE NUMBERS

100

Double-row memory chip (DIMM)

110_1-110_8

memory chips

120

control unit

200

memory chip

A0-A15

Memory address input signals

BA0-BA3

Memory bank address input signals

CLK, #CLK

clock signals

CS

Chip select signal

CAS

Column address strobe

CKE

synchronous signal

ColAdr0-ColAdr4

Column address signals

CSR

First chip select signal

CSC

Second chip select signal

PIN_CLK

Clock signal pin

PIN_R0-PIN_R5

Row address signal pins

PIN_C0-PIN_C4

Column address signal pins

PIN_CSR

First chip select signal pin

PIN_CSC

Second chip select signal pin

RowAdr0-RowAdr5

Row address signals

RAS

Row address strobe

RESET

Reset signal

ZQ

Calibration signal

Claims (11)

Method for accessing a memory chip ( 200 ), characterized by: positioning a plurality of first input pins (PIN_R0, PIN_R1, PIN_R2, PIN_R3, PIN_R4, PIN_R5) and a plurality of second input pins (PIN_C0, PIN_C1, PIN_C2, PIN_C3, PIN_C4) on the memory chip ( 200 ); respectively inputting a plurality of row address signals (RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5) into the plurality of first input pins (PIN_R0, PIN_R1, PIN_R2, PIN_R3, PIN_R4, PIN_R5), wherein a length of a row address command packet of each row address signal (RowAdr0 RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5) corresponds to a plurality of clock periods of a clock signal (CLK); and respectively inputting a plurality of column address signals (ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4) into the plurality of second input pins (PIN_C0, PIN_C1, PIN_C2, PIN_C3, PIN_C4), wherein a length of a column address command packet of each column address signal (ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4) corresponds to a plurality of clock periods of a clock signal (CLK). The method of claim 1, characterized in that the row address command packet has a plurality of row input commands and the column address command packet has a plurality of column input commands. A method according to claim 2, characterized in that the length of the row address command packet corresponds to four clock periods and the row address command packet comprises four row input commands. A method according to claim 3, characterized in that a number of the first input pins (PIN_R0, PIN_R1, PIN_R2, PIN_R3, PIN_R4, PIN_R5) is equal to six. A method according to claim 4, characterized in that the row input commands of the six row address command packets of the six row address signals (RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5) four pieces of setting information of a memory bank address (BA0, BA1, BA2, BA3), sixteen parts setting information of a memory address (A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15) and four pieces of memory control command setting information (CMD0, CMD1 , CMD2, CMD3). A method according to claim 5, characterized in that the method further comprises: decoding the four pieces of memory control command setting information (CMD0, CMD1, CMD2, CMD3) to generate a memory control command. The method of claim 2, characterized in that the length of the column address command packet corresponds to four clock periods and the column address command packet has four column input commands. A method according to claim 7, characterized in that the number of second input pins (PIN_C0, PIN_C1, PIN_C2, PIN_C3, PIN_C4) is equal to five. A method according to claim 8, characterized in that the column input commands of the five column address command packets of the five column address signals (ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4) comprise at least four pieces of bank address setting information (BA0, BA1, BA2, BA3) and have thirteen pieces of setting information for a memory address (A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12). A method according to claim 8, characterized in that the column input commands of the five column address command packets of the five column address signals comprise at least one Write Enable (WE) input command (WE), auto precharge (AP) input command (AP) and a burst chop / burst length (BC / BL) input command (BC4 / BL8). Method according to claim 1, characterized in that the method further comprises the following steps: positioning a third input pin and a fourth input pin on the memory chip ( 200 ); Inputting a first chip select signal (CSR) into the third input pin (PIN_CSR) to the memory chip ( 200 ) to receive the plurality of row address signals (RowAdr0, RowAdr1, RowAdr2, RowAdr3, RowAdr4, RowAdr5); and inputting a second chip select signal (CSC) into the fourth input pin (PIN_CSC) to connect the memory chip ( 200 ) to receive the plurality of column address signals (ColAdr0, ColAdr1, ColAdr2, ColAdr3, ColAdr4).

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