DE10206374A1 - Production of planar nitrided read only memory cells comprises implanting nitrogen in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that oxidation rate is adjusted - Google Patents

Production of planar nitrided read only memory cells comprises implanting nitrogen in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that oxidation rate is adjusted

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Publication number
DE10206374A1
DE10206374A1 DE10206374A DE10206374A DE10206374A1 DE 10206374 A1 DE10206374 A1 DE 10206374A1 DE 10206374 A DE10206374 A DE 10206374A DE 10206374 A DE10206374 A DE 10206374A DE 10206374 A1 DE10206374 A1 DE 10206374A1
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DE
Germany
Prior art keywords
bit lines
oxide
oxidation rate
semiconductor material
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10206374A
Other languages
German (de)
Inventor
Von Kamienski Elard Stein
Thomas Gaertner
Joerg Schulze
Dirk Caspary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10206374A priority Critical patent/DE10206374A1/en
Publication of DE10206374A1 publication Critical patent/DE10206374A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

Production of planar NROM (nitrided read only memory) cells having gate electrodes, a gate oxide and bit lines comprises forming an oxide for insulating the bit lines and an oxide for forming the gate oxide whilst thermally oxidizing a semiconductor material. Nitrogen is implanted in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that an oxidation rate is adjusted. Preferred Features: Additional low voltage components are produced. Implantation of nitrogen in the region of the bit lines is carried out so that the oxidation rate is lower than the oxidation rate in the region of the components.

Description

Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung von planaren NROM-Zellen, bei dem das Bitleitungsoxid gemeinsam mit dem Gateoxid gefertigt wird. Falls Niedervoltbauelemente zusätzlich integriert werden, wird noch ein weiteres Gateoxid benötigt. Diese Oxide werden hergestellt, indem das Halbleitermaterial thermisch oxidiert wird. Während dieser thermischen Oxidation, insbesondere bei niedrigen Oxidationstemperaturen, wächst das Bitleitungsoxid im Bereich der vorgesehenen Bitleitungen im Vergleich zu dem Oxid, das für die Gate-Elektroden vorgesehen ist, merklich schneller, da das Halbleitermaterial in diesem Bereich hoch dotiert ist. Dieses schnelle Oxidwachstum im Bereich der Bitleitungen stellt ein erhebliches technisches Problem dar, da das Oxid bei gleichzeitigem Wachstum mit dem Gateoxid im Bitleitungsbereich zu dick hergestellt wird. Mit zunehmender Miniaturisierung der Bauelemente muss das thermische Budget bei der Herstellung weiter verringert werden, um die Ausdiffusionen von Dotierstoff besser kontrollieren zu können, so dass die Oxidationstemperaturen geringer eingestellt werden als bisher. Außerdem sind dünnere Bitleitungsoxide als bisher notwendig. The present invention relates to a method for Manufacture of planar NROM cells in which the bit line oxide is manufactured together with the gate oxide. If Low-voltage components are also integrated additional gate oxide needed. These oxides are made by thermally oxidizing the semiconductor material. While this thermal oxidation, especially at low Oxidation temperatures, the bit line oxide grows in the area of the provided bit lines compared to the oxide that is provided for the gate electrodes, noticeably faster, because the semiconductor material is highly doped in this area. This rapid oxide growth in the area of the bit lines represents a significant technical problem because the oxide with simultaneous growth with the gate oxide in Bit line area is made too thick. With increasing Miniaturization of the components must be followed by the thermal budget Manufacturing can be further reduced to the out diffusions of dopant to control better, so that the Oxidation temperatures are set lower than so far. In addition, bitline oxides are thinner than before necessary.

Die Oxidationsrate von thermisch oxidiertem Halbleitermaterial kann dadurch verringert werden, dass zuvor eine Implantation von Stickstoff in das Halbleitermaterial vorgenommen wird. Mit der Höhe der Dosis der Implantation kann die spätere Oxidationsrate in einer vorgesehenen Weise eingestellt werden. The oxidation rate of thermally oxidized Semiconductor material can be reduced in that a Implantation of nitrogen made in the semiconductor material becomes. With the amount of the implantation dose, the later oxidation rate set in a designated manner become.

Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung planarer NROM-Zellen anzugeben, bei dem ohne erheblichen zusätzlichen Aufwand bei gleichzeitiger Oxidation des Gateoxids und des Bitleitungsoxids das Oxid im Bitleitungsbereich dünner hergestellt werden kann, als das bisher möglich war. The object of the present invention is to provide a method for Manufacture of planar NROM cells to specify in which without considerable additional effort with simultaneous oxidation of the gate oxide and the bit line oxide the oxide in Bit line area can be made thinner than before was possible.

Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus dem abhängigen Anspruch. This task is accomplished with the method with the characteristics of Claim 1 solved. Refinements result from the dependent claim.

Bei dem Verfahren wird vor der Herstellung des Oxids der Bitleitungen in das Halbleitermaterial im Bereich der Bitleitungen eine Implantation von Stickstoff vorgenommen, mit der eine Oxidationsrate in diesem Bereich eingestellt wird, die in der gewünschten Relation zu der Oxidationsrate im Bereich der Gate-Elektroden steht. Durch die Wahl der richtigen Implantationsdosis wird die Dicke des im späteren Prozess der Oxidation gebildeten Bitleitungsoxids in dem vorgesehenen Umfang verringert, wobei gleichzeitig die Parameter der Oxidation weitgehend frei gewählt werden können. Bei einer zusätzlichen Herstellung von Niedervoltbauelementen kann die Oxidationsrate im Bereich der Bitleitungen durch die Implantation von Stickstoff insbesondere so eingestellt werden, dass die Oxidationsrate im Bereich der Bitleitungen auch in der geeigneten Relation zu der Oxidationsrate im Bereich der Niedervoltbauelemente steht. Insbesondere kann die Implantation von Stickstoff im Bereich der Bitleitungen so vorgenommen werden, dass eine geringere Oxidationsrate eingestellt wird als die Oxidationsrate im Bereich der Bauelemente. In the process, the Bit lines in the semiconductor material in the area of Bit lines made an implantation of nitrogen with which an oxidation rate is set in this range, which in the desired relation to the oxidation rate in the range of Gate electrodes. By choosing the right one Implantation dose will be the thickness of the later process Oxidation formed bit line oxide to the intended extent decreased, at the same time the parameters of oxidation can be chosen largely freely. With an additional The manufacture of low-voltage components can Oxidation rate in the area of the bit lines through the implantation of Nitrogen in particular be adjusted so that the Oxidation rate in the area of the bit lines also in the suitable relation to the oxidation rate in the range of Low voltage components stands. In particular, the implantation of Nitrogen in the area of the bit lines are made so that a lower oxidation rate is set than that Oxidation rate in the area of the components.

Claims (3)

1. Verfahren zur Herstellung planarer NROM-Zellen mit Gate- Elektroden, Gateoxid und Bitleitungen, bei dem
ein Oxid zur Isolation der Bitleitungen und
ein Oxid zur Ausbildung des Gateoxids hergestellt werden, indem eine thermische Oxidation von Halbleitermaterial durchgeführt wird,
dadurch gekennzeichnet, dass
vor der Herstellung des Oxids der Bitleitungen in das Halbleitermaterial im Bereich der Bitleitungen eine Implantation von Stickstoff erfolgt, mit der eine Oxidationsrate eingestellt wird, die in einer vorgesehenen Relation zu der Oxidationsrate im Bereich der Gate-Elektroden steht. 1. Process for the production of planar NROM cells with gate electrodes, gate oxide and bit lines, in which
an oxide to isolate the bit lines and
an oxide for forming the gate oxide can be produced by performing a thermal oxidation of semiconductor material,
characterized in that
before the production of the oxide of the bit lines in the semiconductor material in the area of the bit lines, an implantation of nitrogen is carried out, with which an oxidation rate is set which is in a predetermined relation to the oxidation rate in the area of the gate electrodes. 2. Verfahren nach Anspruch 1, bei dem zusätzlich Niedervoltbauelemente hergestellt werden, für die ebenfalls eine Oxidation erfolgt und die Implantation von Stickstoff im Bereich der Bitleitungen so vorgenommen wird, dass eine Oxidationsrate eingestellt wird, die in einer vorgesehenen Relation zu der Oxidationsrate im Bereich der Niedervoltbauelemente steht. 2. The method according to claim 1, in which additionally Low-voltage components are manufactured, for which also one Oxidation takes place and the implantation of nitrogen in the area of the bit lines is made so that an oxidation rate is set which is in an intended relation to the Oxidation rate in the area of low-voltage components. 3. Verfahren nach Anspruch 1 oder 2, bei dem die Implantation von Stickstoff im Bereich der Bitleitungen so vorgenommen wird, dass eine geringere Oxidationsrate eingestellt wird als die Oxidationsrate im Bereich der Bauelemente. 3. The method according to claim 1 or 2, wherein the implantation of nitrogen in the area of the bit lines is made so that a lower oxidation rate is set as the oxidation rate in the range of Components.
DE10206374A 2002-02-15 2002-02-15 Production of planar nitrided read only memory cells comprises implanting nitrogen in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that oxidation rate is adjusted Ceased DE10206374A1 (en)

Priority Applications (1)

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DE10206374A DE10206374A1 (en) 2002-02-15 2002-02-15 Production of planar nitrided read only memory cells comprises implanting nitrogen in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that oxidation rate is adjusted

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DE10206374A DE10206374A1 (en) 2002-02-15 2002-02-15 Production of planar nitrided read only memory cells comprises implanting nitrogen in the region of the bit lines before the oxide of the bit lines is formed in the semiconductor material so that oxidation rate is adjusted

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5504030A (en) * 1995-07-21 1996-04-02 United Microelectronics Corporation Process for fabricating high-density mask ROM devices
US5597753A (en) * 1994-12-27 1997-01-28 United Microelectronics Corporation CVD oxide coding method for ultra-high density mask read-only-memory (ROM)
US5942780A (en) * 1996-08-09 1999-08-24 Advanced Micro Devices, Inc. Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5330920A (en) * 1993-06-15 1994-07-19 Digital Equipment Corporation Method of controlling gate oxide thickness in the fabrication of semiconductor devices
US5597753A (en) * 1994-12-27 1997-01-28 United Microelectronics Corporation CVD oxide coding method for ultra-high density mask read-only-memory (ROM)
US5504030A (en) * 1995-07-21 1996-04-02 United Microelectronics Corporation Process for fabricating high-density mask ROM devices
US5942780A (en) * 1996-08-09 1999-08-24 Advanced Micro Devices, Inc. Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate

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