DE1269472T1 - Einsparung des vorladungsschrittes bei einem synchronen flash-speicher - Google Patents

Einsparung des vorladungsschrittes bei einem synchronen flash-speicher

Info

Publication number
DE1269472T1
DE1269472T1 DE1269472T DE01920861T DE1269472T1 DE 1269472 T1 DE1269472 T1 DE 1269472T1 DE 1269472 T DE1269472 T DE 1269472T DE 01920861 T DE01920861 T DE 01920861T DE 1269472 T1 DE1269472 T1 DE 1269472T1
Authority
DE
Germany
Prior art keywords
saving
flash memory
synchronous flash
precharge step
precharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1269472T
Other languages
English (en)
Inventor
F Roohparvar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE1269472T1 publication Critical patent/DE1269472T1/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
DE1269472T 2000-03-30 2001-03-30 Einsparung des vorladungsschrittes bei einem synchronen flash-speicher Pending DE1269472T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19350600P 2000-03-30 2000-03-30
US09/568,935 US6314049B1 (en) 2000-03-30 2000-05-11 Elimination of precharge operation in synchronous flash memory
PCT/US2001/010038 WO2001075895A2 (en) 2000-03-30 2001-03-30 Elimination of precharge operation in synchronous flash memory

Publications (1)

Publication Number Publication Date
DE1269472T1 true DE1269472T1 (de) 2003-08-14

Family

ID=26889062

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1269472T Pending DE1269472T1 (de) 2000-03-30 2001-03-30 Einsparung des vorladungsschrittes bei einem synchronen flash-speicher

Country Status (7)

Country Link
US (2) US6314049B1 (de)
EP (1) EP1269472A2 (de)
JP (1) JP3773846B2 (de)
KR (1) KR100438635B1 (de)
AU (1) AU2001247871A1 (de)
DE (1) DE1269472T1 (de)
WO (1) WO2001075895A2 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7073014B1 (en) * 2000-07-28 2006-07-04 Micron Technology, Inc. Synchronous non-volatile memory system
US6621761B2 (en) * 2000-05-31 2003-09-16 Advanced Micro Devices, Inc. Burst architecture for a flash memory
US20020132617A1 (en) * 2001-01-05 2002-09-19 Nuss Randall S. Method and apparatus for providing virtual frequency identifiers for internet radio
JP4569915B2 (ja) * 2000-08-11 2010-10-27 エルピーダメモリ株式会社 半導体記憶装置
US6580659B1 (en) * 2000-08-25 2003-06-17 Micron Technology, Inc. Burst read addressing in a non-volatile memory device
US6865702B2 (en) * 2001-04-09 2005-03-08 Micron Technology, Inc. Synchronous flash memory with test code input
JP4109841B2 (ja) * 2001-06-19 2008-07-02 株式会社東芝 半導体集積回路装置および半導体機器システム
US6560161B1 (en) * 2001-08-30 2003-05-06 Micron Technology, Inc. Synchronous flash memory command sequence
US6870770B2 (en) * 2001-12-12 2005-03-22 Micron Technology, Inc. Method and architecture to calibrate read operations in synchronous flash memory
US6671212B2 (en) * 2002-02-08 2003-12-30 Ati Technologies Inc. Method and apparatus for data inversion in memory device
US6721227B2 (en) * 2002-02-11 2004-04-13 Micron Technology, Inc. User selectable banks for DRAM
US7035753B2 (en) * 2002-03-20 2006-04-25 Infineon Technologies Ag Method and apparatus for placing an integrated circuit into a default mode of operation
US7251711B2 (en) 2002-05-28 2007-07-31 Micron Technology, Inc. Apparatus and methods having a command sequence
US6751139B2 (en) 2002-05-29 2004-06-15 Micron Technology, Inc. Integrated circuit reset circuitry
US7007133B2 (en) * 2002-05-29 2006-02-28 Micron Technology, Inc. Synchronous memory open page register
KR100464034B1 (ko) * 2002-07-19 2005-01-03 엘지전자 주식회사 클록 동기화 방법
JP4111789B2 (ja) 2002-09-13 2008-07-02 富士通株式会社 半導体記憶装置の制御方法及び半導体記憶装置
JP2004185686A (ja) 2002-11-29 2004-07-02 Toshiba Corp 半導体記憶装置
US6870774B2 (en) * 2002-12-10 2005-03-22 Micron, Technology, Inc. Flash memory architecture for optimizing performance of memory having multi-level memory cells
WO2006011216A1 (ja) * 2004-07-29 2006-02-02 Spansion Llc 不揮発性記憶装置の情報設定方法、不揮発性記憶装置、およびそれらを搭載したシステム
US20060095622A1 (en) * 2004-10-28 2006-05-04 Spansion, Llc System and method for improved memory performance in a mobile device
US7336558B2 (en) * 2004-11-02 2008-02-26 Samsung Electronics Co., Ltd. Semiconductor memory device with reduced number of pads
US20060143330A1 (en) * 2004-12-23 2006-06-29 Oliver Kiehl Method for data transmit burst length control
US7512507B2 (en) * 2006-03-23 2009-03-31 Micron Technology, Inc. Die based trimming
KR101019443B1 (ko) * 2006-03-31 2011-03-07 후지쯔 가부시끼가이샤 메모리 장치, 그 에러 정정의 지원 방법, 그 지원 프로그램을 저장한 컴퓨터로 판독가능한 기록매체, 메모리 카드, 회로 기판 및 전자 기기
EP2003568B1 (de) * 2006-03-31 2012-02-22 Fujitsu Limited Speicherbaustein, steuerverfahren dafür, steuerprogramm dafür, speicherkarte, leiterplatte und elektronische geräte
JPWO2007116483A1 (ja) * 2006-03-31 2009-08-20 富士通株式会社 メモリ装置、その制御方法、その制御プログラム、メモリ・カード、回路基板及び電子機器
US7849302B2 (en) 2006-04-10 2010-12-07 Apple Inc. Direct boot arrangement using a NAND flash memory
US7292487B1 (en) * 2006-05-10 2007-11-06 Micron Technology, Inc. Independent polling for multi-page programming
CN101542629B (zh) * 2006-07-07 2014-02-26 S.阿夸半导体有限公司 存储器设备和计算系统
KR101364443B1 (ko) * 2007-01-31 2014-02-17 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리 제어기와 메모리,이 시스템의 신호 구성 방법
US7729191B2 (en) 2007-09-06 2010-06-01 Micron Technology, Inc. Memory device command decoding system and memory device and processor-based system using same
JP2012203919A (ja) 2011-03-23 2012-10-22 Toshiba Corp 半導体記憶装置およびその制御方法
KR20130032505A (ko) * 2011-09-23 2013-04-02 에스케이하이닉스 주식회사 반도체 시스템
US9740485B2 (en) 2012-10-26 2017-08-22 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9754648B2 (en) 2012-10-26 2017-09-05 Micron Technology, Inc. Apparatuses and methods for memory operations having variable latencies
US9734097B2 (en) * 2013-03-15 2017-08-15 Micron Technology, Inc. Apparatuses and methods for variable latency memory operations
US9727493B2 (en) 2013-08-14 2017-08-08 Micron Technology, Inc. Apparatuses and methods for providing data to a configurable storage area
US10365835B2 (en) 2014-05-28 2019-07-30 Micron Technology, Inc. Apparatuses and methods for performing write count threshold wear leveling operations
KR20180049502A (ko) 2016-11-03 2018-05-11 삼성전자주식회사 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법
US11581053B2 (en) 2020-08-06 2023-02-14 Micron Technology, Inc. Memory device test mode access

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
KR940006094B1 (ko) 1989-08-17 1994-07-06 삼성전자 주식회사 불휘발성 반도체 기억장치 및 그 제조방법
JP3319105B2 (ja) 1993-12-15 2002-08-26 富士通株式会社 同期型メモリ
FR2714202B1 (fr) * 1993-12-22 1996-01-12 Sgs Thomson Microelectronics Mémoire en circuit intégré à temps de lecture amélioré.
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
DE69513113T2 (de) * 1994-08-31 2000-06-21 Motorola Inc Verfahren zum synchronen Speicherzugriff
US5661054A (en) 1995-05-19 1997-08-26 Micron Technology, Inc. Method of forming a non-volatile memory array
US5600605A (en) 1995-06-07 1997-02-04 Micron Technology, Inc. Auto-activate on synchronous dynamic random access memory
US5598374A (en) * 1995-07-14 1997-01-28 Cirrus Logic, Inc. Pipeland address memories, and systems and methods using the same
US5666321A (en) 1995-09-01 1997-09-09 Micron Technology, Inc. Synchronous DRAM memory with asynchronous column decode
US5748551A (en) * 1995-12-29 1998-05-05 Micron Technology, Inc. Memory device with multiple internal banks and staggered command execution
US5787457A (en) 1996-10-18 1998-07-28 International Business Machines Corporation Cached synchronous DRAM architecture allowing concurrent DRAM operations
US5974514A (en) 1996-11-12 1999-10-26 Hewlett-Packard Controlling SDRAM memory by using truncated burst read-modify-write memory operations
US5825710A (en) 1997-02-26 1998-10-20 Powerchip Semiconductor Corp. Synchronous semiconductor memory device
US5978284A (en) * 1997-08-22 1999-11-02 Micron Technology, Inc. Synchronous memory with programmable read latency
US6141247A (en) 1997-10-24 2000-10-31 Micron Technology, Inc. Non-volatile data storage unit and method of controlling same
US5889714A (en) 1997-11-03 1999-03-30 Digital Equipment Corporation Adaptive precharge management for synchronous DRAM

Also Published As

Publication number Publication date
WO2001075895A3 (en) 2002-03-21
KR100438635B1 (ko) 2004-07-02
KR20020087113A (ko) 2002-11-21
US6496444B2 (en) 2002-12-17
US6314049B1 (en) 2001-11-06
JP2003529882A (ja) 2003-10-07
JP3773846B2 (ja) 2006-05-10
EP1269472A2 (de) 2003-01-02
US20020006074A1 (en) 2002-01-17
AU2001247871A1 (en) 2001-10-15
WO2001075895A2 (en) 2001-10-11

Similar Documents

Publication Publication Date Title
DE1269472T1 (de) Einsparung des vorladungsschrittes bei einem synchronen flash-speicher
DE60119199D1 (de) Speicherzelle
DE50111881D1 (de) MRAM-Speicher
DE60109958D1 (de) Seitenlöschbarer flash-speicher
DE60136143D1 (de) Speichersteuergerät
DE602004010303D1 (de) Mehrere schnittstellen in einem speichergehäuse
AU8210601A (en) Associative memory
DE60100716D1 (de) Nichtflüchtige Halbleiterspeicher
DE60111108D1 (de) Verbesserung in einem Ekonomiserkreislauf
DE69938621D1 (de) Befehlausgabe in einem Rechner
DE60118573D1 (de) Druckspeicher
NO20034338L (no) Ekspanderbart verktöy nede i brönnen
NO20030045L (no) Soppcelleveggsyntesegen
NO20024781D0 (no) Sidemodus-sletting i et flash-minne oppsett
AU2823101A (en) Validator with removable flash memory
NO20032188L (no) En selvinnstillende ikke-volatil minnecelle
DE60107606D1 (de) Formgedächtnislegierung
AU2001280952A1 (en) Word line decoding architecture in a flash memory
DE60140314D1 (de) Ionenspeicher
DE50014731D1 (de) Speicherzellenanordnung
DE10196001T1 (de) Schnittstellenbefehlsarchitektur für synchronen Flashspeicher
DE10196002T1 (de) Synchroner Flashspeicher mit simultanem Schreib-und Lesebetrieb
ITMI20022464A1 (it) Memoria a semiconduttore con dram incorporata
NO20023682D0 (no) Enkelttrinns multisone hydroisomeriseringsprosess
AU2001251121A1 (en) Synchronous flash memory with non-volatile mode register