DE19526012A1 - Electrically erasable and programmable non-volatile memory cell - Google Patents

Abstract

The invention concerns an electrically erasable and programmable non-volatile storage location which consists of only one MOS transistor formed by a source-channel-drain junction. According to the invention, a semiconductor substrate (1) of a first type of conductivity contains a drain region (2) and a source region (3) of a second type of conductivity with opposite polarity to the first type of conductivity. The transistor also comprises a gate electrode (4) which has floating potential and is electrically insulated from the drain region (2) by a tunnel oxide (5) and from a channel region (9) located between the drain and source regions (2, 3) by a gate oxide (5; 10). The gate electrode (4) extends in the source-channel-drain direction at least over part of the channel region (9) and part of the drain region (2). The transistor finally comprises a control electrode (7) which is electrically insulated from the gate electrode (4) by a coupling oxide (8).

Description

Microcontrollers need for general purpose applications Tax tasks, especially in smart cards, are non-cursed memory as program memory and data storage. In front especially when used in portable data carriers with battery operation, such as with mobile data transmission and data processing processing, or with wireless energy supply, as with con tactless chip cards are especially for data storage only programming and erasing procedures with low performance consumption acceptable. In the same way, the Versor voltage are less than 3 V. Because controller and Smart cards are subject to high price pressure for one wide application a low manufacturing process complexity non-volatile memory important.

The FLOTOX EEPROM cells, such as those from "microelectronic Speicher "by Dietrich Rhein and Heinz Freitag, Springer-Ver lay Vienna, 1992, especially page 122 are known are characterized by low power consumption, since they have Fow ler-Nordheim tunnel currents can be programmed and deleted. This makes it easy to program the voltages on the Chip also from low supply voltages that are smaller than 3 V can produce. The reprogramming is at such memories possible byte by byte, so that FLOTOX EEPROM cells are particularly suitable for data storage in Operation can be reprogrammed. These FLOTOX EEPROM cells consist of a selection and a memory transistor and therefore require a large cell area, so that on one Chip only small memory can be realized. Besides, is due to the required high programming voltage of 15 to 20 V the realization of the high-voltage transistors to this To be able to switch programming voltage is complex.  

In contrast to EEPROMs, flash memories have only one Transistor realized per memory cell, so clearly here more complex memories than possible with FLOTOX-EEPROM cells are. However, they are loaded with hot charge carriers (chan nel hot electron: CHE) programmed. This type of program mation requires high programming currents, which are the minimum Limit supply voltage to approx. 5 V. That is why you are as a data storage device that is in operation from low supply voltages or reprogrammed via contactless energy supply should not be used. A common one today Split-gate flash EEPROM cell is also in the book "Microelectronic memories" shown on page 126 and described.

It is therefore the object of the present invention, an elek Trically erasable and programmable non-volatile memories cell to specify the small space required in mobile Systems can be used.

The invention is based on a memory cell with the features of claim 1 solved. Advantageous further developments are in specified in the subclaims.

The memory cell according to the invention consists of only one Transistor, so its space requirement over conventional FLOTOX-EEPROM cells is significantly lower. However, it will in the same way as such FLOTOX-EEPROM cells by Fow ler-Nordheim tunnel currents programmed and deleted. If the first conductivity type is the p-type, it is at the MOS transistor forming the cell by an n-channel train sistor, the cell is typically pro grammes that a voltage of -12 V and a voltage of +5 V is applied to the drain while the source is connected to ground. This will tunnel in the Be of the tunnel oxide, i.e. in the area in which the floating gate electrode, the  so-called floating gate overlapped with the drain area, La manure carrier through the tunnel oxide, so that the floating Gate charges positively. This shifts the stake voltage of this MOS transistor to lower values. To the Deletion of a cell programmed in this way is sent to the Control electrode a voltage of typically 12 V and on the source electrode has a voltage of typically -6 V applied while the drain remains open. Thereby tunnel charge carriers between the floating gate and the Source and also channel area, so that the floating gate like which is discharged and the operating voltage of the Transi shifts to higher values. The threshold voltages are around 1 V for a programmed cell and a non-programmed cell at around 5 V. Reading therefore a voltage of approximately 3 V is applied to the control gate applies a voltage of approximately 1 V and at the drain a voltage of 0 V is applied to the source. Only one programmed cell will then flow a current that at for example, can be detected as a logical "1".

Due to the simultaneous use of a po positive and negative voltage for programming and Deleting a memory cell according to the invention it is possible on an additional, requiring a lot of space Dispense selection transistor and still any memory to be able to address cells individually. With a conventional one Arrangement of the memory cells in a memory matrix in which the gate connections of the memory cells with the word lines and the drain connections are connected to the bit lines, are applying a negative voltage to a word line necessarily all memory cells, their gate connections connected with this word line, with this negative Tension connected. However, it only becomes that memory cell programmed whose drain connection with a positive span connected. The condition that both tensions apply to only one memory cell at a time,  can thus by selecting only one word line and only one Bit line can be met.

The memory cell according to the invention can be advantageous Way together with standard CMOS logic circuits on one Semiconductor substrate, so be realized on a chip. It is also possible to simultaneously use the high-voltage CMOS Circuits for switching the required positive and negative high voltages on the same semiconductor substrate realize. Both the memory cells and the high voltage For this purpose, circuits are installed in deep tubs with a Polarity of the conductivity type, which corresponds to the polarity of the conductor ability type of the semiconductor substrate is opposite arranged.

In a first embodiment of a memory according to the invention cell, the floating gate extends into source channel drain Direction over the entire canal area and one more Part of the drain area. This overlap area floating gate drain defines the tunnel area during programming. In a particularly advantageous training, this is isolie oxide thin at least in part of the overlap region ner than over the channel area. Through this thinner area the tunnel area is then defined. To gate field-induced However, it is to avoid drain leakage currents when programming particularly advantageous if in the area of the pn transition from Drain area to the channel area the oxide is thicker than that Tunnel oxide.

For memory cells in which the floating gate covers the entire The channel area is covered if the programming is too long The threshold voltage of the cell is negative, so that deselection such programmed cells is prevented from reading. This can be achieved through the advantageous design of a so-called Split gate cell can be prevented. This extends Floating gate only over part of the channel area while the control electrode over the entire channel area  stretches and in the area where there is no floating gate, capacitively coupled to the channel for its control. With Such a split gate cell is made from the control electronics trode and gate oxide series transistor formed the lower The cell's threshold voltage is limited even if the insert Voltage of the transistor part made of floating gate and gate oxide becomes negative.

The invention is described below with reference to an embodiment be explained in more detail with the help of figures. Here demonstrate:

Fig. 1 shows a schematic representation of a cross section through a memory cell,

Fig. 2 shows a schematic representation of a cross section through a development of the memory cell according to the invention,

Fig. 3 shows a schematic representation of the arrangement of such memory cells in a memory cell matrix and

Fig. 4 shows in schematic form the basic implementation of memory field, standard CMOS logic and high-voltage CMOS circuits in a semiconductor substrate.

Fig. 1 shows a semiconductor substrate 1 , of a first conductivity type, which should be, for example, of the p-type. In it are a drain region 2 and a source region 3 of a conductivity type with opposite polarity to the conductivity type of the semiconductor substrate 1 , in the present example thus of the n-type. Accordingly, the transistor of this memory cell is an n-channel transistor. The drain region 2 is provided with a drain connection D and the source region 3 with a source connection S. An oxide layer is formed as an electrical insulating layer above the drain region 2 and the source region 3 and the channel region 9 located between these regions. Above this oxide layer 5 , 6 , a gate electrode 4 is formed, which is at an electrically floating potential. It is commonly referred to as a floating gate. According to the invention, it extends in the source-channel-drain direction of the MOS transistor over the channel region and at least part of the drain region 2 . The region of the oxide layer between the floating gate 4 and the channel region is referred to as gate oxide 5 and the region of the oxide layer between the floating gate 4 and the drain region 2 is referred to as tunnel oxide 6 . In the further development of the invention shown in FIG. 1, the tunnel oxide 6 has a smaller thickness than the gate oxide 5 . It when the tunnel oxide 6 , as shown in Fig. 1, in the region of the pn junction from the drain region 2 to the channel region 9 has the same thickness as the gate oxide 5 , whereby a gate field-induced drain leakage current is prevented or at least reduced, is particularly advantageous. For applications in which a higher drain current of this type can be accepted during programming, the arrangement in FIG. 1 can be simplified in that the thicknesses of the tunnel oxide 6 and the gate oxide 5 are chosen to be the same. For this simplified memory cell, some process steps are omitted in the manufacturing process. Above the gate electrode or the floating gate 4 , a control electrode 7, which is electrically insulated from the floating gate 4 by a coupling oxide 8, is arranged. This is connected to a gate terminal G the.

FIG. 2 shows a development of the memory cell according to FIG. 1, the same parts having the same reference numerals. A split gate cell is shown. Here, the floating gate 4 extends only over part of the channel region 9 . As a result, the control electrode 7 can capacitively couple to the channel region 9 via a partial region 10 of the gate oxide and thereby control the latter. This measure compensates the effect of the negative threshold voltage during "over-programming".

Fig. 3 shows a schematic representation of the present invention memory cells in a memory cell array. The memory cell matrix is in word lines. . . WL _n , WL _m . . . and bit lines. . . BL _k , BL _l . . . organized. The memory cells are each with their gate connection G with one of the word lines. . . WL _n , WL _m . . . and with its drain terminal D to one of the bit lines. . . BL _k , BL _l . . . connected. The source connections S of all memory cells are connected to a source line SL. Of course, there can also be several source lines, which are then each connected to only one group of memory cell source connections S.

In a memory cell formed with an NMOS transistor, a high negative programming voltage must be applied to the control electrode, that is to say to the gate terminal G of the memory cell, for programming. Referring to FIG. 3, this means that to a word line WL _n this programming voltage must be applied. However, this means that this programming voltage is present at the same time on all of their memory cells whose gate connections are connected to this word line. In order for programming to take place in a memory cell according to the invention, positive voltage must be applied to the drain terminal D at the same time as the high negative programming voltage at the gate terminal G ei. Referring again to refer to FIG. 3, this positive voltage to a bit line BL must be applied _k, so as derum this positive voltage to all the drain terminals D of the _k with this bit line BL connected to the memory cell is created. However, programming only takes place if a negative programming voltage is present at the gate connection and a positive voltage is present at the drain connection. If only one word line and only one bit line have been selected, this condition is only fulfilled for a single memory cell. Thus, in a memory constructed with memory cells according to the invention, each memory cell can be addressed individually. Of course, it is also possible to program several memory cells simultaneously by addressing several word lines and / or several bit lines.

To erase, a must be connected to the gate of a memory cell high positive voltage and a negati at the source connection ve voltage is applied. If all source connections with connected to a source line is only one when selected Word line on which the high positive voltage is present, the smallest number of memory cells that are erased at once are the number of memory cells attached to a word line tung lie. This will make the deletion process accelerated considerably.

When implementing the electrically erasable and programmable non-volatile memory described above together with CMOS logic, special precautions must be taken, in particular because of the high positive and negative voltages that occur. These are shown schematically in Fig. 4 Darge. Starting from a p-type semiconductor substrate, the N and PMOS field effect transistors for the logic are produced in the p-type substrate and in an n-well. This means that the CMOS logic is design-compatible with standard CMOS circuits. A thicker gate oxide is necessary for the high-voltage CMOS transistors, and the NMOS transistors for switching negative voltages are placed in a p-well within a deep n-well to isolate negative voltages. The high-voltage PMOS transistors are in the n-well. If the switching speed of the logic is only low, the high-voltage and logic transistors can also be implemented with the same (thicker) oxide thickness. The memory cells are isolated from the substrate in a p-well within a deep n-well. This makes it possible to apply a negative voltage to the common source line without influencing the logic part.

By using positive and negative tensions is the amount of programming voltages occurring to approx.  12 V limited, so that the high-voltage parts only to this amount must be interpreted. By using the isolated p-well inside the deep n-well can have negative voltages gene processed without chip in the high-voltage part tion inverter or PMOS source follower got to. The isolated p-well has the advantage in the storage cell field part that the common source management to a negative Voltage can be applied without the CMOS logic part to influence. The positive and negative programming chip due to the low power consumption of the Fowler-Nordheim programming easily on the chip by La tion pumps are generated.

The individual components in FIG. 4 are separated from one another by field oxide regions FO. In Fig. 4, the gate electrodes G of the CMOS logic and the high-voltage CMOS circuits are shown at the same distance from the channel region, but in practice, if fast CMOS logic is required, the oxide thicknesses among the Gate electrodes G can be selected differently. In the cell of the memory array shown in FIG. 4, the floating gate FG and the control gate SG are shown in a schematic manner.

Claims (8)

1. Electrically erasable and programmable non-volatile memory cell, which is formed with only one MOS transistor formed by a source-channel-drain junction,

• - In which a drain ( 2 ) and a source region ( 3 ) of a second conductivity type with opposite polarity to the first conductivity type are formed in a semiconductor substrate ( 1 ) of a first conductivity type,
• - With a floating gate electrode ( 4 ) from the drain region ( 2 ) through a tunnel oxide ( 5 ) and from one between the drain and the source region ( 2 , 3 ) channel region ( 9 ) through a Gate oxide ( 5 ; 10 ) is electrically insulated and extends in the source-channel-drain direction at least over part of the channel region ( 9 ) and part of the drain region ( 2 ) and
• - With a control electrode ( 7 ) which is electrically isolated by a coupling oxide ( 8 ) from the gate electrode ( 4 ).

2. Memory cell according to claim 1, characterized in that the gate electrode ( 4 ) extends over the entire channel region ( 9 ). 3. Memory cell according to claim 1, characterized in that the oxide layer over the Kanalbe area ( 9 ) in a first gate oxide region ( 5 ) which capacitively couples the gate electrode ( 4 ) to the channel region ( 9 ) and in a second gate oxide region ( 10 ) is subdivided, the second gate oxide region ( 10 ) capacitively coupling part of the control electrode ( 7 ) to the channel region ( 9 ). 4. Memory cell according to one of the preceding claims, characterized in that the tunnel oxide ( 6 ) is thinner than the gate oxide ( 5 ). 5. Memory cell according to claim 4, characterized in that the gate oxide ( 5 ) extends into the region of the transition from the drain region ( 2 ) to the channel region and the drain region ( 2 ) partially overlaps. 6. Memory cell according to one of the preceding claims, characterized in that the MOS transistor in a tub is formed from the first conductivity type, which in a deep tub of the second conductivity type is arranged. 7. Memory cell according to claim 6, characterized in that the MOS transistor is arranged together with a standard CMOS logic circuit and / or a high-voltage circuit in a semiconductor substrate ( 1 ). 8. Memory cell according to one of the preceding claims, characterized in that positive and negative voltages are simultaneously applied to the control electrode ( 7 ) and the source region ( 3 ) or the drain region ( 2 ) for erasing and programming.