DE3072083D1 - Error correction system - Google Patents

Error correction system

Info

Publication number
DE3072083D1
DE3072083D1 DE8080901621T DE3072083T DE3072083D1 DE 3072083 D1 DE3072083 D1 DE 3072083D1 DE 8080901621 T DE8080901621 T DE 8080901621T DE 3072083 T DE3072083 T DE 3072083T DE 3072083 D1 DE3072083 D1 DE 3072083D1
Authority
DE
Germany
Prior art keywords
error correction
correction system
error
correction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8080901621T
Other languages
English (en)
Inventor
Genzo Nagano
Masao Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3072083D1 publication Critical patent/DE3072083D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1024—Identification of the type of error
DE8080901621T 1979-08-31 1980-08-29 Error correction system Expired DE3072083D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP54111152A JPS6051749B2 (ja) 1979-08-31 1979-08-31 エラ−訂正方式
PCT/JP1980/000199 WO1981000641A1 (en) 1979-08-31 1980-08-29 Error correction system

Publications (1)

Publication Number Publication Date
DE3072083D1 true DE3072083D1 (en) 1988-04-21

Family

ID=14553772

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8080901621T Expired DE3072083D1 (en) 1979-08-31 1980-08-29 Error correction system

Country Status (7)

Country Link
US (1) US4394763A (de)
EP (1) EP0034188B1 (de)
JP (1) JPS6051749B2 (de)
AU (1) AU530666B2 (de)
CA (1) CA1165893A (de)
DE (1) DE3072083D1 (de)
WO (1) WO1981000641A1 (de)

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150197A (en) * 1981-03-11 1982-09-16 Nippon Telegr & Teleph Corp <Ntt> Storage circuit
US4450559A (en) * 1981-12-24 1984-05-22 International Business Machines Corporation Memory system with selective assignment of spare locations
US4458349A (en) * 1982-06-16 1984-07-03 International Business Machines Corporation Method for storing data words in fault tolerant memory to recover uncorrectable errors
US4562576A (en) * 1982-08-14 1985-12-31 International Computers Limited Data storage apparatus
US4506364A (en) * 1982-09-30 1985-03-19 International Business Machines Corporation Memory address permutation apparatus
JPS59117800A (ja) * 1982-12-25 1984-07-07 Fujitsu Ltd バツフア・ストレ−ジの１ビツトエラ−処理方式
JPS59165300A (ja) * 1983-03-10 1984-09-18 Fujitsu Ltd メモリ障害訂正方式
US4608687A (en) * 1983-09-13 1986-08-26 International Business Machines Corporation Bit steering apparatus and method for correcting errors in stored data, storing the address of the corrected data and using the address to maintain a correct data condition
US4625312A (en) * 1983-10-06 1986-11-25 Honeywell Information Systems Inc. Test and maintenance method and apparatus for investigation of intermittent faults in a data processing system
US4544850A (en) * 1983-12-05 1985-10-01 Gte Automatic Electric Incorporated Race condition mediator circuit
US4646312A (en) * 1984-12-13 1987-02-24 Ncr Corporation Error detection and correction system
US4654847A (en) * 1984-12-28 1987-03-31 International Business Machines Apparatus for automatically correcting erroneous data and for storing the corrected data in a common pool alternate memory array
JPS61264599A (ja) * 1985-05-16 1986-11-22 Fujitsu Ltd 半導体記憶装置
JPS623499A (ja) * 1985-06-28 1987-01-09 Mitsubishi Electric Corp 半導体メモリ装置
US4710934A (en) * 1985-11-08 1987-12-01 Texas Instruments Incorporated Random access memory with error correction capability
US4719627A (en) * 1986-03-03 1988-01-12 Unisys Corporation Memory system employing a low DC power gate array for error correction
JPS6324428A (ja) * 1986-07-17 1988-02-01 Mitsubishi Electric Corp キヤツシユメモリ
US5128943A (en) * 1986-10-24 1992-07-07 United Technologies Corporation Independent backup mode transfer and mechanism for digital control computers
JPS63245529A (ja) * 1987-03-31 1988-10-12 Toshiba Corp レジスタ退避復元装置
US4980850A (en) * 1987-05-14 1990-12-25 Digital Equipment Corporation Automatic sizing memory system with multiplexed configuration signals at memory modules
US4955024A (en) * 1987-09-14 1990-09-04 Visual Information Technologies, Inc. High speed image processing computer with error correction and logging
US4931990A (en) * 1987-11-19 1990-06-05 Bruce C. Perkin Hardened bubble memory circuit
JPH0290816A (ja) * 1988-09-28 1990-03-30 Hitachi Ltd 誤り訂正方法および回路
US5199033A (en) * 1990-05-10 1993-03-30 Quantum Corporation Solid state memory array using address block bit substitution to compensate for non-functional storage cells
FR2751083B1 (fr) * 1996-07-12 1998-10-30 Sextant Avionique Procede et dispositif pour quantifier l'impact des rayonnements cosmiques sur un equipement electronique a memoire
JP3871471B2 (ja) 1999-07-12 2007-01-24 松下電器産業株式会社 Ｅｃｃ回路搭載半導体記憶装置及びその検査方法
WO2001099106A1 (fr) * 2000-06-23 2001-12-27 Sony Corporation Dispositif et procede de reproduction d'un support enregistre, procede de controle de sortie de donnees, procede de sortie de donnees, procede de detection d'erreur, et procede de reproduction de sortie de donnees
US7069494B2 (en) * 2003-04-17 2006-06-27 International Business Machines Corporation Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism
US7392347B2 (en) * 2003-05-10 2008-06-24 Hewlett-Packard Development Company, L.P. Systems and methods for buffering data between a coherency cache controller and memory
US7320100B2 (en) * 2003-05-20 2008-01-15 Cray Inc. Apparatus and method for memory with bit swapping on the fly and testing
US7184916B2 (en) * 2003-05-20 2007-02-27 Cray Inc. Apparatus and method for testing memory cards
US7278083B2 (en) * 2003-06-27 2007-10-02 International Business Machines Corporation Method and system for optimized instruction fetch to protect against soft and hard errors
US7336102B2 (en) * 2004-07-27 2008-02-26 International Business Machines Corporation Error correcting logic system
US7642813B2 (en) * 2004-07-27 2010-01-05 International Business Machines Corporation Error correcting logic system
WO2006039556A2 (en) * 2004-10-02 2006-04-13 Wms Gaming Inc. Gaming device with error correcting memory
JP4734003B2 (ja) * 2005-03-17 2011-07-27 富士通株式会社 ソフトエラー訂正方法、メモリ制御装置及びメモリシステム
US7831882B2 (en) 2005-06-03 2010-11-09 Rambus Inc. Memory system with error detection and retry modes of operation
US9459960B2 (en) 2005-06-03 2016-10-04 Rambus Inc. Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
US8205146B2 (en) * 2005-07-21 2012-06-19 Hewlett-Packard Development Company, L.P. Persistent error detection in digital memory
US7562285B2 (en) 2006-01-11 2009-07-14 Rambus Inc. Unidirectional error code transfer for a bidirectional data link
JP2007257791A (ja) * 2006-03-24 2007-10-04 Fujitsu Ltd 半導体記憶装置
US7292950B1 (en) * 2006-05-08 2007-11-06 Cray Inc. Multiple error management mode memory module
CN103258572B (zh) 2006-05-12 2016-12-07 苹果公司 存储设备中的失真估计和消除
WO2007132456A2 (en) 2006-05-12 2007-11-22 Anobit Technologies Ltd. Memory device with adaptive capacity
US8156403B2 (en) 2006-05-12 2012-04-10 Anobit Technologies Ltd. Combined distortion estimation and error correction coding for memory devices
US20070271495A1 (en) * 2006-05-18 2007-11-22 Ian Shaeffer System to detect and identify errors in control information, read data and/or write data
US8352805B2 (en) 2006-05-18 2013-01-08 Rambus Inc. Memory error detection
US7975192B2 (en) 2006-10-30 2011-07-05 Anobit Technologies Ltd. Reading memory cells using multiple thresholds
WO2008068747A2 (en) 2006-12-03 2008-06-12 Anobit Technologies Ltd. Automatic defect management in memory devices
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
WO2008111058A2 (en) 2007-03-12 2008-09-18 Anobit Technologies Ltd. Adaptive estimation of memory cell read thresholds
WO2008139441A2 (en) * 2007-05-12 2008-11-20 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
US8259497B2 (en) * 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
WO2009063450A2 (en) 2007-11-13 2009-05-22 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US8225181B2 (en) * 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) * 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8493783B2 (en) 2008-03-18 2013-07-23 Apple Inc. Memory device readout using multiple sense times
US7995388B1 (en) 2008-08-05 2011-08-09 Anobit Technologies Ltd. Data storage using modified voltages
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) * 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8677203B1 (en) 2010-01-11 2014-03-18 Apple Inc. Redundant data storage schemes for multi-die memory systems
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8493781B1 (en) 2010-08-12 2013-07-23 Apple Inc. Interference mitigation using individual word line erasure operations
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals
US9235466B2 (en) * 2012-07-03 2016-01-12 Samsung Electronics Co., Ltd. Memory devices with selective error correction code
CN103942119A (zh) * 2013-12-26 2014-07-23 杭州华为数字技术有限公司 一种存储器错误的处理方法和装置
WO2019190866A1 (en) 2018-03-26 2019-10-03 Rambus Inc. Command/address channel error detection
US11269720B2 (en) * 2019-08-11 2022-03-08 Winbond Electronics Corp. Memory storage apparatus and data access method
US11556416B2 (en) 2021-05-05 2023-01-17 Apple Inc. Controlling memory readout reliability and throughput by adjusting distance between read thresholds
US11847342B2 (en) 2021-07-28 2023-12-19 Apple Inc. Efficient transfer of hard data and confidence levels in reading a nonvolatile memory

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3656107A (en) * 1970-10-23 1972-04-11 Ibm Automatic double error detection and correction apparatus
US3917933A (en) * 1974-12-17 1975-11-04 Sperry Rand Corp Error logging in LSI memory storage units using FIFO memory of LSI shift registers
US3949208A (en) * 1974-12-31 1976-04-06 International Business Machines Corporation Apparatus for detecting and correcting errors in an encoded memory word
JPS51137335A (en) * 1975-05-22 1976-11-27 Yoshihiro Toma Faulty memory permissible control system
JPS5381036A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Error correction-detection system
JPS592057B2 (ja) * 1979-02-07 1984-01-17 株式会社日立製作所 エラ−訂正・検出方式
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
US4359771A (en) * 1980-07-25 1982-11-16 Honeywell Information Systems Inc. Method and apparatus for testing and verifying the operation of error control apparatus within a memory

Also Published As

Publication number Publication date
AU530666B2 (en) 1983-07-21
CA1165893A (en) 1984-04-17
JPS6051749B2 (ja) 1985-11-15
AU6226180A (en) 1981-03-19
JPS5637896A (en) 1981-04-11
EP0034188B1 (de) 1988-03-16
US4394763A (en) 1983-07-19
WO1981000641A1 (en) 1981-03-05
EP0034188A1 (de) 1981-08-26
EP0034188A4 (de) 1984-08-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee