DE3469977D1 - Wafer fabrication by implanting through protective layer - Google Patents

Wafer fabrication by implanting through protective layer

Info

Publication number
DE3469977D1
DE3469977D1 DE8484401427T DE3469977T DE3469977D1 DE 3469977 D1 DE3469977 D1 DE 3469977D1 DE 8484401427 T DE8484401427 T DE 8484401427T DE 3469977 T DE3469977 T DE 3469977T DE 3469977 D1 DE3469977 D1 DE 3469977D1
Authority
DE
Germany
Prior art keywords
implanting
protective layer
wafer fabrication
fabrication
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484401427T
Other languages
English (en)
Inventor
Paul J Howell
Gregory B Currier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Application granted granted Critical
Publication of DE3469977D1 publication Critical patent/DE3469977D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
DE8484401427T 1983-07-05 1984-07-05 Wafer fabrication by implanting through protective layer Expired DE3469977D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/510,761 US4498227A (en) 1983-07-05 1983-07-05 Wafer fabrication by implanting through protective layer

Publications (1)

Publication Number Publication Date
DE3469977D1 true DE3469977D1 (en) 1988-04-21

Family

ID=24032080

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401427T Expired DE3469977D1 (en) 1983-07-05 1984-07-05 Wafer fabrication by implanting through protective layer

Country Status (5)

Country Link
US (1) US4498227A (de)
EP (1) EP0134166B1 (de)
JP (1) JPH0697665B2 (de)
CA (1) CA1216075A (de)
DE (1) DE3469977D1 (de)

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JPS61222137A (ja) * 1985-03-06 1986-10-02 Sharp Corp チップ識別用凹凸パターン形成方法
GB2175136B (en) * 1985-04-10 1988-10-05 Mitsubishi Electric Corp Semiconductor manufacturing method
JPH0719838B2 (ja) * 1985-07-19 1995-03-06 松下電器産業株式会社 半導体装置およびその製造方法
US4669179A (en) * 1985-11-01 1987-06-02 Advanced Micro Devices, Inc. Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions
JPH0666402B2 (ja) * 1985-12-12 1994-08-24 三菱電機株式会社 半導体集積回路装置の入力保護回路
US4729006A (en) * 1986-03-17 1988-03-01 International Business Machines Corporation Sidewall spacers for CMOS circuit stress relief/isolation and method for making
JPS6370516A (ja) * 1986-09-12 1988-03-30 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 金属接点の形成方法
JP2609313B2 (ja) * 1986-12-11 1997-05-14 フェアチャイルド セミコンダクタ コーポレーション バイポーラ修正型アイソプレーナ集積回路構成体及びその製造方法
US4849344A (en) * 1986-12-11 1989-07-18 Fairchild Semiconductor Corporation Enhanced density modified isoplanar process
IT1231913B (it) * 1987-10-23 1992-01-15 Sgs Microelettronica Spa Procedimento di fabbricazione di transistori ad alta frequenza.
JPH01116617U (de) * 1988-02-02 1989-08-07
US4847672A (en) * 1988-02-29 1989-07-11 Fairchild Semiconductor Corporation Integrated circuit die with resistive substrate isolation of multiple circuits
US5041896A (en) * 1989-07-06 1991-08-20 General Electric Company Symmetrical blocking high voltage semiconductor device and method of fabrication
US5139961A (en) * 1990-04-02 1992-08-18 National Semiconductor Corporation Reducing base resistance of a bjt by forming a self aligned silicide in the single crystal region of the extrinsic base
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion
US5220192A (en) * 1992-07-10 1993-06-15 Lsi Logic Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof
EP0592084B1 (de) * 1992-09-22 1998-01-07 National Semiconductor Corporation Verfahren zur Herstellung eines Schottky-Transistors mit retrogradierter n-Wannenkathode
DE4340590A1 (de) * 1992-12-03 1994-06-09 Hewlett Packard Co Grabenisolation unter Verwendung dotierter Seitenwände
US5516731A (en) * 1994-06-02 1996-05-14 Lsi Logic Corporation High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
TW274628B (de) * 1994-06-03 1996-04-21 At & T Corp
KR0156316B1 (ko) * 1995-09-13 1998-12-01 김광호 반도체장치의 패턴 형성방법
JP2865045B2 (ja) 1996-02-28 1999-03-08 日本電気株式会社 半導体装置の製造方法
JP4027447B2 (ja) 1996-04-24 2007-12-26 株式会社ルネサステクノロジ 半導体装置の製造方法
US6001701A (en) * 1997-06-09 1999-12-14 Lucent Technologies Inc. Process for making bipolar having graded or modulated collector
US6097062A (en) * 1997-09-12 2000-08-01 Advanced Micro Devices, Inc. Optimized trench edge formation integrated with high quality gate formation
US6444534B1 (en) 2001-01-30 2002-09-03 Advanced Micro Devices, Inc. SOI semiconductor device opening implantation gettering method
US6376336B1 (en) 2001-02-01 2002-04-23 Advanced Micro Devices, Inc. Frontside SOI gettering with phosphorus doping
US6670259B1 (en) 2001-02-21 2003-12-30 Advanced Micro Devices, Inc. Inert atom implantation method for SOI gettering
US6958264B1 (en) 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
WO2003075092A2 (en) * 2002-03-01 2003-09-12 Massachusetts Institute Of Technology Protecting group-containing polymers for lithographic resist compositions
KR100731087B1 (ko) * 2005-10-28 2007-06-22 동부일렉트로닉스 주식회사 바이씨모스 소자 및 그의 제조방법
KR101040367B1 (ko) * 2008-12-26 2011-06-10 주식회사 하이닉스반도체 새들 핀 트랜지스터를 구비하는 반도체소자 및 그 제조방법
CN116504612B (zh) * 2023-02-09 2023-11-21 长鑫存储技术有限公司 半导体结构及其形成方法

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Also Published As

Publication number Publication date
US4498227A (en) 1985-02-12
EP0134166A1 (de) 1985-03-13
CA1216075A (en) 1986-12-30
EP0134166B1 (de) 1988-03-16
JPH0697665B2 (ja) 1994-11-30
JPS6037775A (ja) 1985-02-27

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee