DE3855354D1 - Halbleiteranordnung mit metallischen Leiterschichten und Verfahren zu ihrer Herstellung - Google Patents
Halbleiteranordnung mit metallischen Leiterschichten und Verfahren zu ihrer HerstellungInfo
- Publication number
- DE3855354D1 DE3855354D1 DE3855354T DE3855354T DE3855354D1 DE 3855354 D1 DE3855354 D1 DE 3855354D1 DE 3855354 T DE3855354 T DE 3855354T DE 3855354 T DE3855354 T DE 3855354T DE 3855354 D1 DE3855354 D1 DE 3855354D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- conductor layers
- metallic conductor
- semiconductor arrangement
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62203483A JPH084109B2 (ja) | 1987-08-18 | 1987-08-18 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3855354D1 true DE3855354D1 (de) | 1996-07-11 |
DE3855354T2 DE3855354T2 (de) | 1996-10-10 |
Family
ID=16474900
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3855354T Expired - Fee Related DE3855354T2 (de) | 1987-08-18 | 1988-08-17 | Halbleiteranordnung mit metallischen Leiterschichten und Verfahren zu ihrer Herstellung |
Country Status (5)
Country | Link |
---|---|
US (1) | US5160998A (de) |
EP (2) | EP0525824B1 (de) |
JP (1) | JPH084109B2 (de) |
KR (1) | KR920003311B1 (de) |
DE (1) | DE3855354T2 (de) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW214599B (de) * | 1990-10-15 | 1993-10-11 | Seiko Epson Corp | |
JP2667605B2 (ja) * | 1991-02-21 | 1997-10-27 | 株式会社東芝 | 不揮発性半導体記憶装置およびその製造方法 |
JP2875093B2 (ja) * | 1992-03-17 | 1999-03-24 | 三菱電機株式会社 | 半導体装置 |
US5448111A (en) * | 1993-09-20 | 1995-09-05 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
JP2919257B2 (ja) * | 1993-12-15 | 1999-07-12 | 日本電気株式会社 | 多層配線半導体装置 |
JP3122297B2 (ja) * | 1993-12-28 | 2001-01-09 | 株式会社東芝 | 半導体装置 |
US6300253B1 (en) | 1998-04-07 | 2001-10-09 | Micron Technology, Inc. | Semiconductor processing methods of forming photoresist over silicon nitride materials, and semiconductor wafer assemblies comprising photoresist over silicon nitride materials |
US5926739A (en) | 1995-12-04 | 1999-07-20 | Micron Technology, Inc. | Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride |
US6323139B1 (en) | 1995-12-04 | 2001-11-27 | Micron Technology, Inc. | Semiconductor processing methods of forming photoresist over silicon nitride materials |
KR100271222B1 (ko) * | 1995-12-14 | 2000-12-01 | 오카베 히로무 | 반도체 소자 및 그 제조 방법 |
JP3586031B2 (ja) * | 1996-03-27 | 2004-11-10 | 株式会社東芝 | サセプタおよび熱処理装置および熱処理方法 |
US5913140A (en) * | 1996-12-23 | 1999-06-15 | Lam Research Corporation | Method for reduction of plasma charging damage during chemical vapor deposition |
JP3226816B2 (ja) * | 1996-12-25 | 2001-11-05 | キヤノン販売株式会社 | 層間絶縁膜の形成方法、半導体装置及びその製造方法 |
US6110775A (en) * | 1997-02-04 | 2000-08-29 | Matsushita Electronics Corporation | Process for fabrication of a dram cell having a stacked capacitor |
US6551857B2 (en) | 1997-04-04 | 2003-04-22 | Elm Technology Corporation | Three dimensional structure integrated circuits |
US5985771A (en) | 1998-04-07 | 1999-11-16 | Micron Technology, Inc. | Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers |
US6316372B1 (en) | 1998-04-07 | 2001-11-13 | Micron Technology, Inc. | Methods of forming a layer of silicon nitride in a semiconductor fabrication process |
US6635530B2 (en) * | 1998-04-07 | 2003-10-21 | Micron Technology, Inc. | Methods of forming gated semiconductor assemblies |
US6136688A (en) * | 1999-10-20 | 2000-10-24 | Vanguard International Semiconductor Corporation | High stress oxide to eliminate BPSG/SiN cracking |
US7645719B2 (en) * | 2004-10-13 | 2010-01-12 | Ncr Corporation | Thermal paper with security features |
US7300886B1 (en) * | 2005-06-08 | 2007-11-27 | Spansion Llc | Interlayer dielectric for charge loss improvement |
GB201410317D0 (en) | 2014-06-10 | 2014-07-23 | Spts Technologies Ltd | Substrate |
US10515822B2 (en) | 2016-06-20 | 2019-12-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing bottom layer wrinkling in a semiconductor device |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5915489B2 (ja) * | 1975-04-09 | 1984-04-10 | 日本電気株式会社 | 半導体集積回路装置 |
JPS5228870A (en) * | 1975-08-29 | 1977-03-04 | Hitachi Ltd | Method for production of thin membrane |
SE7700229L (sv) * | 1976-01-22 | 1977-07-23 | Western Electric Co | Forfarande for beleggning av substrat genom utfellning fran ett plasma |
US4135954A (en) * | 1977-07-12 | 1979-01-23 | International Business Machines Corporation | Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers |
JPS5519850A (en) * | 1978-07-31 | 1980-02-12 | Hitachi Ltd | Semiconductor |
JPS5745931A (en) * | 1980-09-04 | 1982-03-16 | Fujitsu Ltd | Semiconductor device with multilayer passivation film and manufacture thereof |
US4455568A (en) * | 1981-08-27 | 1984-06-19 | American Microsystems, Inc. | Insulation process for integrated circuits |
JPS58190043A (ja) * | 1982-04-30 | 1983-11-05 | Seiko Epson Corp | 多層配線法 |
US4446194A (en) * | 1982-06-21 | 1984-05-01 | Motorola, Inc. | Dual layer passivation |
JPS59163834A (ja) * | 1983-03-09 | 1984-09-14 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS60178695A (ja) * | 1984-02-17 | 1985-09-12 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | 電気的相互接続パツケ−ジ |
JPS60192359A (ja) * | 1984-03-14 | 1985-09-30 | Nec Corp | 半導体メモリ装置 |
JPS61279132A (ja) * | 1985-06-05 | 1986-12-09 | Sony Corp | 半導体装置 |
JPS6257255A (ja) * | 1985-09-06 | 1987-03-12 | Agency Of Ind Science & Technol | 化合物半導体装置の製造方法 |
JPS62145842A (ja) * | 1985-12-20 | 1987-06-29 | Nec Corp | 半導体装置の製造方法 |
JPS62145839A (ja) * | 1985-12-20 | 1987-06-29 | Seiko Epson Corp | Mos型集積回路装置の多層配線レイアウト |
JPS62154642A (ja) * | 1985-12-26 | 1987-07-09 | Matsushita Electronics Corp | 半導体装置 |
JPS62193265A (ja) * | 1986-02-20 | 1987-08-25 | Toshiba Corp | 半導体装置の製造方法 |
DE3685495D1 (de) * | 1986-07-11 | 1992-07-02 | Ibm | Verfahren zur herstellung einer unteraetzten maskenkontur. |
US4825277A (en) * | 1987-11-17 | 1989-04-25 | Motorola Inc. | Trench isolation process and structure |
-
1987
- 1987-08-18 JP JP62203483A patent/JPH084109B2/ja not_active Expired - Fee Related
-
1988
- 1988-08-17 DE DE3855354T patent/DE3855354T2/de not_active Expired - Fee Related
- 1988-08-17 KR KR1019880010438A patent/KR920003311B1/ko not_active IP Right Cessation
- 1988-08-17 EP EP92115068A patent/EP0525824B1/de not_active Expired - Lifetime
- 1988-08-17 EP EP88307623A patent/EP0307099B1/de not_active Expired - Lifetime
-
1991
- 1991-10-21 US US07/780,564 patent/US5160998A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5160998A (en) | 1992-11-03 |
DE3855354T2 (de) | 1996-10-10 |
EP0307099A1 (de) | 1989-03-15 |
EP0307099B1 (de) | 1994-05-25 |
EP0525824B1 (de) | 1996-06-05 |
KR890004403A (ko) | 1989-04-21 |
EP0525824A2 (de) | 1993-02-03 |
EP0525824A3 (en) | 1993-03-10 |
JPH084109B2 (ja) | 1996-01-17 |
JPS6447052A (en) | 1989-02-21 |
KR920003311B1 (ko) | 1992-04-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3855354D1 (de) | Halbleiteranordnung mit metallischen Leiterschichten und Verfahren zu ihrer Herstellung | |
DE3683382D1 (de) | Elektrische schaltungen mit reparierbaren verbindungslinien und verfahren zur herstellung. | |
DE3583721D1 (de) | Poroese folien und verfahren zu ihrer herstellung. | |
DE69224740D1 (de) | Vertikale halbleiteranordnung mit isoliertem gate und verfahren zu ihrer herstellung | |
DE3855912T2 (de) | Supraleitender Draht und Verfahren zu seiner Herstellung | |
DE3578019D1 (de) | Einrichtung mit veraenderlicher spalte und verfahren zu ihrer herstellung. | |
DE68905980T2 (de) | Hochfeste supraleitfähige drähte und kabel mit hoher stromdichte sowie verfahren zur herstellung. | |
DE3669758D1 (de) | Sicherungsmutter und verfahren zu ihrer herstellung. | |
DE3853089T2 (de) | Supraleitender Draht und Verfahren zu seiner Herstellung. | |
DE68919913D1 (de) | Zusammengesetzter supraleitender Draht und Verfahren zu dessen Herstellung. | |
DE68925679T2 (de) | Isolierte Leitung und Verfahren zu ihrer Herstellung | |
DE3767139D1 (de) | Quellfaehige kabelbandage und verfahren zu ihrer herstellung. | |
DE3685969T2 (de) | Integrierte schaltung mit halbleiterkondensator und verfahren zu ihrer herstellung. | |
DE3689503D1 (de) | Multifilament-Supraleiterdrähte und Verfahren zu deren Herstellung. | |
DE3581039D1 (de) | Halbleitervorrichtung mit einem verbindungsdraht und verfahren zu ihrer herstellung. | |
KR890701228A (ko) | 9Ok초전도체 제조를 위한 개선된 방법 | |
DE69026530T2 (de) | Halbleiteranordnung mit zwei leitenden Schichten und Verfahren zu ihrer Herstellung | |
DE3880860D1 (de) | Halbleiterspeicheranordnung und verfahren zu ihrer herstellung. | |
DE3688711D1 (de) | Integrierte halbleiterschaltungsanordnung und verfahren zu ihrer herstellung. | |
DE69027566D1 (de) | Halbleiteranordnung mit einer Mehrschichten-Gateelektrode und Verfahren zu ihrer Herstellung | |
DE69124072D1 (de) | Supraleitende Schaltung und Verfahren zu ihrer Herstellung | |
DE3853607T2 (de) | Supraleitender Draht und Verfahren zu seiner Herstellung. | |
DE3879719D1 (de) | Halbleiterspeicheranordnung und verfahren zu ihrer herstellung. | |
DE3584197D1 (de) | Halbleitervorrichtung und verfahren zu ihrer herstellung. | |
DE3871659T2 (de) | Supraleitfaehiger keramischer draht und verfahren zu seiner herstellung. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |