DE3882266T2 - Abfrageprüfgerät für digitale Systeme mit dynamischem Direktzugriffspeicher. - Google Patents

Abfrageprüfgerät für digitale Systeme mit dynamischem Direktzugriffspeicher.

Info

Publication number
DE3882266T2
DE3882266T2 DE88303223T DE3882266T DE3882266T2 DE 3882266 T2 DE3882266 T2 DE 3882266T2 DE 88303223 T DE88303223 T DE 88303223T DE 3882266 T DE3882266 T DE 3882266T DE 3882266 T2 DE3882266 T2 DE 3882266T2
Authority
DE
Germany
Prior art keywords
random access
dynamic random
access memory
tester
query
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88303223T
Other languages
English (en)
Other versions
DE3882266D1 (de
Inventor
David J Garcia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of DE3882266D1 publication Critical patent/DE3882266D1/de
Application granted granted Critical
Publication of DE3882266T2 publication Critical patent/DE3882266T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
DE88303223T 1987-04-16 1988-04-11 Abfrageprüfgerät für digitale Systeme mit dynamischem Direktzugriffspeicher. Expired - Fee Related DE3882266T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/039,548 US4827476A (en) 1987-04-16 1987-04-16 Scan test apparatus for digital systems having dynamic random access memory

Publications (2)

Publication Number Publication Date
DE3882266D1 DE3882266D1 (de) 1993-08-19
DE3882266T2 true DE3882266T2 (de) 1994-02-03

Family

ID=21906060

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88303223T Expired - Fee Related DE3882266T2 (de) 1987-04-16 1988-04-11 Abfrageprüfgerät für digitale Systeme mit dynamischem Direktzugriffspeicher.

Country Status (5)

Country Link
US (1) US4827476A (de)
EP (1) EP0287303B1 (de)
JP (1) JP2564601B2 (de)
AU (1) AU607207B2 (de)
DE (1) DE3882266T2 (de)

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JPH0820967B2 (ja) * 1987-09-25 1996-03-04 三菱電機株式会社 集積回路
US5153509A (en) * 1988-05-17 1992-10-06 Zilog, Inc. System for testing internal nodes in receive and transmit FIFO's
US4980888A (en) * 1988-09-12 1990-12-25 Digital Equipment Corporation Memory testing system
GB8823336D0 (en) * 1988-10-05 1989-07-05 British Aerospace Digital communications systems
JP2518039B2 (ja) * 1989-03-06 1996-07-24 日本電気株式会社 デ―タ処理装置の制御記憶ロ―ド方法
US4918378A (en) * 1989-06-12 1990-04-17 Unisys Corporation Method and circuitry for enabling internal test operations in a VLSI chip
DE69029122T2 (de) * 1989-06-16 1997-04-03 Advantest Corp Prüfmustergenerator
JP3118266B2 (ja) * 1990-03-06 2000-12-18 ゼロックス コーポレイション 同期セグメントバスとバス通信方法
US5313623A (en) * 1990-07-03 1994-05-17 Digital Equipment Corporation Method and apparatus for performing diagnosis scanning of a memory unit regardless of the state of the system clock and without affecting the store data
US5255381A (en) * 1990-07-03 1993-10-19 Digital Equipment Corporation Mode switching for a memory system with diagnostic scan
US5155732A (en) * 1990-10-09 1992-10-13 At&T Bell Laboratories Method and apparatus for data transfer to and from devices through a boundary-scan test access port
US5293123A (en) * 1990-10-19 1994-03-08 Tandem Computers Incorporated Pseudo-Random scan test apparatus
US5228042A (en) * 1991-02-07 1993-07-13 Northern Telecom Limited Method and circuit for testing transmission paths
JPH0599993A (ja) * 1991-04-15 1993-04-23 Internatl Business Mach Corp <Ibm> 試験可能な走査ストリングを有する論理回路
US5301156A (en) * 1991-07-18 1994-04-05 Hewlett-Packard Company Configurable self-test for embedded RAMs
US5321661A (en) * 1991-11-20 1994-06-14 Oki Electric Industry Co., Ltd. Self-refreshing memory with on-chip timer test circuit
US5369752A (en) * 1992-06-01 1994-11-29 Motorola, Inc. Method and apparatus for shifting data in an array of storage elements in a data processing system
US5522038A (en) * 1993-04-16 1996-05-28 Micron Technology, Inc. Testing mapped signal sources
US5864565A (en) 1993-06-15 1999-01-26 Micron Technology, Inc. Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
US5410547A (en) * 1993-06-17 1995-04-25 Cirrus Logic, Inc. Video controller IC with built-in test circuit and method of testing
US5450455A (en) * 1993-06-28 1995-09-12 Tandem Computers Incorporated Method and apparatus for including the states of nonscannable parts in a scan chain
US5951703A (en) * 1993-06-28 1999-09-14 Tandem Computers Incorporated System and method for performing improved pseudo-random testing of systems having multi driver buses
US6038622A (en) * 1993-09-29 2000-03-14 Texas Instruments Incorporated Peripheral access with synchronization feature
US6035262A (en) * 1994-06-27 2000-03-07 Tandem Computers Incorporated Real time observation serial scan test architecture
IL110181A (en) * 1994-06-30 1998-02-08 Softchip Israel Ltd Install microprocessor and peripherals
US5506959A (en) * 1994-08-04 1996-04-09 Telecommunication Research Laboratories Method and apparatus for testing electronic memories for the presence of multiple cell coupling faults
US5544107A (en) * 1994-08-22 1996-08-06 Adaptec, Inc. Diagnostic data port for a LSI or VLSI integrated circuit
US5761489A (en) * 1995-04-17 1998-06-02 Motorola Inc. Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system
US5758063A (en) * 1995-05-04 1998-05-26 Micron Technology, Inc. Testing mapped signal sources
US5754557A (en) * 1996-10-10 1998-05-19 Hewlett-Packard Co. Method for refreshing a memory, controlled by a memory controller in a computer system, in a self-refresh mode while scanning the memory controller
TW306627U (en) * 1996-12-12 1997-05-21 Holtek Semiconductor Inc Differentiation device of test mode
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
JPH11154103A (ja) * 1997-11-20 1999-06-08 Mitsubishi Electric Corp 半導体集積回路装置
US6049505A (en) * 1998-05-22 2000-04-11 Micron Technology, Inc. Method and apparatus for generating memory addresses for testing memory devices
WO2001039254A2 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US6327687B1 (en) * 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US8533547B2 (en) * 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6684358B1 (en) * 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US6874109B1 (en) * 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US6353842B1 (en) * 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
US6557129B1 (en) * 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6725387B1 (en) * 2000-04-28 2004-04-20 Hewlett-Packard Development Company, L.P. Method and apparatus for causing computer system interconnection to be in the same state each time test code is executed
DE10125022A1 (de) * 2001-05-22 2002-12-12 Infineon Technologies Ag Dynamischer Speicher und Verfahren zum Testen eines dynamischen Speichers
US8438432B2 (en) * 2010-08-25 2013-05-07 Vixs Systems, Inc. DRAM memory controller with built-in self test and methods for use therewith
TWI640996B (zh) * 2017-12-21 2018-11-11 新唐科技股份有限公司 記憶體電路及其測試方法
US10747611B2 (en) * 2018-01-15 2020-08-18 Microchip Technology Incorporated Safety enhancement for memory controllers

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IT1047437B (it) * 1975-10-08 1980-09-10 Cselt Centro Studi Lab Telecom Procedimento e dispositivo per il controllo in linea di memorie logiche sequenziali operanti a divisione di tempo
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
JPS58182200A (ja) * 1982-04-20 1983-10-25 Nec Corp 記憶装置
JPS6013396A (ja) * 1983-07-01 1985-01-23 Hitachi Micro Comput Eng Ltd ダイナミツク型ｒａｍ
US4601034A (en) * 1984-03-30 1986-07-15 Texas Instruments Incorporated Method and apparatus for testing very large scale integrated memory circuits
US4622668A (en) * 1984-05-09 1986-11-11 International Business Machines Corporation Process and apparatus for testing a microprocessor and dynamic ram
US4654827A (en) * 1984-08-14 1987-03-31 Texas Instruments Incorporated High speed testing of semiconductor memory devices
US4757503A (en) * 1985-01-18 1988-07-12 The University Of Michigan Self-testing dynamic ram

Also Published As

Publication number Publication date
EP0287303B1 (de) 1993-07-14
EP0287303A3 (en) 1990-08-16
JP2564601B2 (ja) 1996-12-18
US4827476A (en) 1989-05-02
AU607207B2 (en) 1991-02-28
EP0287303A2 (de) 1988-10-19
DE3882266D1 (de) 1993-08-19
JPS6446293A (en) 1989-02-20
AU1459888A (en) 1988-10-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee