DE3883132T2 - Synchrone Halbleiterspeichervorrichtung. - Google Patents

Synchrone Halbleiterspeichervorrichtung.

Info

Publication number
DE3883132T2
DE3883132T2 DE88402442T DE3883132T DE3883132T2 DE 3883132 T2 DE3883132 T2 DE 3883132T2 DE 88402442 T DE88402442 T DE 88402442T DE 3883132 T DE3883132 T DE 3883132T DE 3883132 T2 DE3883132 T2 DE 3883132T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
synchronous semiconductor
synchronous
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88402442T
Other languages
English (en)
Other versions
DE3883132D1 (de
Inventor
Chikai Ohno
Michiyuki Hirata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Publication of DE3883132D1 publication Critical patent/DE3883132D1/de
Application granted granted Critical
Publication of DE3883132T2 publication Critical patent/DE3883132T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
DE88402442T 1987-09-29 1988-09-27 Synchrone Halbleiterspeichervorrichtung. Expired - Fee Related DE3883132T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62244695A JPS6488662A (en) 1987-09-29 1987-09-29 Semiconductor memory

Publications (2)

Publication Number Publication Date
DE3883132D1 DE3883132D1 (de) 1993-09-16
DE3883132T2 true DE3883132T2 (de) 1993-12-02

Family

ID=17122561

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88402442T Expired - Fee Related DE3883132T2 (de) 1987-09-29 1988-09-27 Synchrone Halbleiterspeichervorrichtung.

Country Status (5)

Country Link
US (1) US4882712A (de)
EP (1) EP0310496B1 (de)
JP (1) JPS6488662A (de)
KR (1) KR910005585B1 (de)
DE (1) DE3883132T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
US6112287A (en) * 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
US4916670A (en) * 1988-02-02 1990-04-10 Fujitsu Limited Semiconductor memory device having function of generating write signal internally
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5995443A (en) * 1990-04-18 1999-11-30 Rambus Inc. Synchronous memory device
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5649160A (en) * 1995-05-23 1997-07-15 Microunity Systems Engineering, Inc. Noise reduction in integrated circuits and circuit assemblies
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6343352B1 (en) 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6963626B1 (en) 1998-10-02 2005-11-08 The Board Of Trustees Of The Leland Stanford Junior University Noise-reducing arrangement and method for signal processing
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
JP4709641B2 (ja) * 2005-12-20 2011-06-22 大王製紙株式会社 使い捨て紙おむつの製造方法
DE102007051839B4 (de) * 2007-10-30 2015-12-10 Polaris Innovations Ltd. Kontrollschaltung, Speichervorrichtung mit einer Kontrollschaltung und Verfahren zum Durchführen eines Schreibkommandos bzw. zum Betrieb einer Speichervorrichtung mit einer Kontrollschaltung
KR102489320B1 (ko) 2022-06-25 2023-01-18 (주)케이셈테크놀러지 외팔보 쿼드 타입 반도체 다이 본딩장치 및 그 본딩방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5634186A (en) * 1979-08-29 1981-04-06 Hitachi Ltd Bipolar memory circuit
JPS59124075A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd 半導体記憶装置
JPS59151386A (ja) * 1983-01-31 1984-08-29 Fujitsu Ltd 半導体記憶装置
JPS6166292A (ja) * 1984-09-10 1986-04-05 Hitachi Ltd 半導体記憶装置
US4675846A (en) * 1984-12-17 1987-06-23 International Business Machines Corporation Random access memory
JPH0778993B2 (ja) * 1985-11-05 1995-08-23 株式会社日立製作所 半導体メモリ
JP2585602B2 (ja) * 1987-06-10 1997-02-26 株式会社日立製作所 半導体記憶装置

Also Published As

Publication number Publication date
EP0310496A2 (de) 1989-04-05
KR910005585B1 (ko) 1991-07-31
JPS6488662A (en) 1989-04-03
KR890005749A (ko) 1989-05-16
DE3883132D1 (de) 1993-09-16
US4882712A (en) 1989-11-21
EP0310496A3 (de) 1991-03-13
EP0310496B1 (de) 1993-08-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee