DE4403520A1 - Flash EEPROM with three trough region CMOS structure - Google Patents

Abstract

The EEPROM includes a substrate (140) of one conductivity type and a peripheral PMOS region with a well of another conductivity type (111) inside the substrate. A NMOS peripheral region (120) of a different conductivity and a memory cell of the same conductivity is also included in the substrate (130). Both regions and the cell have their respective source, drain (112,123,132) and gate (114,125,134) electrodes above gate oxide films (113,124,133), the cell gate being a floating gate. A control gate (136) is provided above the memory cell floating gate with a border layer (135) in between. A relatively high negative potential is supplied to the control gate by a negative potential source (VG), e.g. -11V to -13V, during an erasure event. Relatively low positive potential sources (0.5V to 5.0V) are supplied to the gates of the PMOS region and the memory cell by respective positive sources (VN,VP). The NMOS region is supplied by a reference potential (VR).

Description

The invention relates to a flash EEPROM (immediately electrical erasable and programmable read-only memory) and on a memory of this type with triple well or triple potential wells CMOS (complementary metal oxide semiconductor) structure.

A distinction is essentially made between semiconductor memories Read only memories (ROMs) and random access memories (RAMs). ROMs are described first, followed by RAMs.

Read-only memories ROMs include so-called mask ROMs (MROMs), in which program data during the manufacturing process in diffusion layers by designing masks for the ion implant tion and contact openings are introduced. The programming takes place electrically after manufacture and assembly of the Spei cherchips. In this case they are programmable ROMs, PROMs.

PROM cells are described in more detail below.

PROMs include erasable PROMs (EPROMs) that contain data can be extinguished by ultraviolet radiation, and so-called electrical erasable PROMs (EEPROMs), in which data is transmitted electronically be deleted.

Figure 1a shows a cross-sectional view of a typical EPROM cell, while Figure 1b shows a cross-sectional view of a typical CMOS / NMOS EPROM.

According to FIG. 1a, the EPROM has a layered n-channel gate structure, consisting of two polysilicon layers 15 and 16 . The first polysilicon layer 15 serves as an unconnected or potentially free floating gate electrode, that is to say as a floating gate electrode, while the second polysilicon layer 16 serves as a control gate electrode.

In this memory cell, a positive high voltage is applied to the gate electrode 16 and to a drain electrode 17 , so that hot electrons which have high energy can be generated in the vicinity of a drain region 12 . These hot electrons enter the floating gate electrode 15 via a potential barrier of the gate oxide film 14 . As a result of the amount of charge of the electrons injected into the floating gate electrode 15 , the threshold voltage of a transistor of the cell changes, as a result of which the programming is ultimately achieved.

If the cell is exposed to ultraviolet radiation, the energy of which is higher than the potential barrier ( 3.3 eV) of the gate oxide film 14 , the electrons accumulated in the floating gate electrode 15 are guided back to the substrate 11 . This phenomenon is briefly described as Programmlöschzu stand. With 12 and 13 drain and source areas are designated.

FIG. 1b shows a CMOS / NMOS-EPROM with an NMOS Zellenbe rich 20 on a p-type substrate 21. With such an EPROM, the position of the cell area 20 with NMOS structure is important, as well as with random access memories (DRAMs). An n-well EPROM structure is preferably used when using NMOS technology, in which the cell region 20 is located on the p-type substrate 21 .

In recent times there are more and more so-called one-time PROM or OTP EPROMs are used in those after which they are programmed once further registered mail is prevented. This OTP EPROMs are located in plastic housings that have no window. Usually EPROMs are in housings with windows.

EEPROMs are described in more detail below.  

With the EEPROMs, which are written and erased electrically a distinction is made between so-called floating gate type memories and Metal nitride oxide semiconductor (MNOS) memory.

In general, the first-mentioned stores have better properties maintenance of memory content while the latter are more permanent with regard to the write / erase rations are.

FIGS. 2a to 2c are cross-sectional views of typical EEPROM cell h len.

A cell of the so-called floating gate tunnel oxide type (FLOTOX type) is depicted in FIG. 2a. In contrast, the cell according to FIG. 2b contains a three-layer polysilicon structure with a textured or structured polysilicon surface, in order to create a tunnel in this way. In contrast, the cell according to FIG. 2c is of the MNOS type.

In both of the cells shown in FIGS. 2a and 2b, use is made of a tunnel phenomenon, described by the Fowler-Nordheim effect (FN effect).

In the cell of Fig. 2c of the MNOS type, a very thin silicon oxide film is 32 (SiO₂) film on a silicon substrate 31. On the silicon oxide film 32 is a silicon nitride film 33 (Si₃N₄ film) with a suitable thickness. Finally, a polysilicon gate 34 comes to rest on this silicon nitride film 33 .

As is well known, there are charge carrier trapping centers (charge carrier traps) in the Si₃N₄ film 33 or at an interface between the Si₃N₄ film 33 and the SiO₂ film 32 . If a voltage is applied to the gate 34 , charge carriers are obtained between the silicon substrate 31 and the trapping point or trap, due to the tunnel effect. Therefore, the threshold of the cell can be varied so that it is possible to store a "0" or a "1".

Instead of the EPROMs that can be erased by ultraviolet radiation, such as already mentioned, electrically erasable EEPROMs can also be used. These EEPROM cells have an erasable gate. You point about it also has a large storage capacity.

All of the cells shown in FIGS . 2a to 2c are produced in NMOS technology. In contrast, CMOS EEPROMs are of the CMOS / NMOS type. These CMOS structures contain NMOS structures, in particular n-wells or n-potential wells.

As already mentioned, MOS memories with CMOS structures have been developed wraps. The CMOS / NMOS structures are like the CMOS structure classified.

In the past, complete CMOS cells were only available in so-called SRAMs with CMOS structure. If not as much as SRAMs also had CMOS structures in MROMs and EEPROMs available.

The so-called flash technology will be discussed in more detail below, with reference to FIGS. 3 to 6.

Figure 3 shows a cross-sectional view of a structure according to US Patent No. 4,698,787. This patent can be considered one of the first in the field of flash technology.

Referring to FIG. 3, the deletion of data which have accumulated in a floating gate 45 takes place, characterized in that charges from the floating gate 45 in the direction of an n⁺-type source region flow 43, taking off of the Fowler-Nordheim tunneling use. The term "n⁺" here means high concentration n type of line.

This process is referred to as the so-called source deletion process net, which is used, for example, by Intel.

When erasing a gate voltage Vg of 0 V is applied to a control gate 46 , as shown in Fig. 3. On the other hand, a source voltage Vs of 13 V is applied to the source region 43 , while a p-type substrate 41 receives a substrate voltage Vsub of 0 V.

Polysilicon is mainly used as the material for the floating gate electrode 45 .

In accordance with the aforementioned U.S. Patent to Excel, issued October 6, 1987, a deeply diffused n ^{- line} type source region 44 is fabricated adjacent to the n Source line type source region 43 such that region 44 surrounds region 43 . to prevent breakdown of the semiconductor junction from occurring during the erase operation. The term "n⁻" here means low-concentration n-type line area.

FIG. 4 shows another example of the Flash technology. Here is a cross section of a structure from U.S. Patent No. 5,077,691 issued to AMD on December 31, 1991.

When erasing data or charges that have accumulated in a floating gate 54 , a low source voltage Vs of 0.5 to 5 V is applied to a source region 53 in accordance with FIG. 4 in order to solve the problem of breakdown of the semiconductor junction already described above To prevent source area. Furthermore, a high negative voltage Vg of -11 V is applied to a control gate 55 . In the AMD patent, it is therefore no longer necessary to form a low-lying transition source region of the n⁺ line type below the n⁺ source region 53 .

This last-described method is called a so-called negative gate Deletion procedure described.

FIGS. 5a and 5b show cross sections through a proposed NEC structure, published in "Journal of Solid State Circuits, Volume 127, no. 11, November 1992, pp 1547-1553". This document is intended to constitute the state of the art in relation to the present invention. It discloses an extinguishing process that differs from that of the two above patents.

In this last-mentioned document from NEC, the Data through an FN tunneling process from the floating gate to a channel area rich and not, as previously described, through an FN tunneling process from the floating gate to the source area.

Fig. 5a shows a flash EEPROM with Dreifachwannen- or three-fold potential troughs CMOS structure. The flash EEPROM according to FIG. 5 a contains a p-type substrate 100 and a peripheral PMOS region 60 . The peripheral PMOS region 60 consists of a flat n-type well 61 in the p-type substrate 100 , of source and drain regions 62 of the p⁺ type, which lie within the n-type well 61 and are uniform from one another are spaced apart from a gate oxide film 63 on the p-type substrate 100 , the gate oxide film 63 coming to lie on the region 61 between the source and drain regions 62 and overlapping with the regions 62 , and from a gate electrode 64 the gate oxide film 63 .

Furthermore, the flash EEPROM includes a peripheral NMOS region 70 with a flat p-type well 71 in the p-type substrate 100 , with source and drain regions 72 of the n + type within the p-type well 71 , which are equally spaced from one another, with a gate oxide film 73 on the p-type substrate 100 , the gate oxide film 73 coming to lie on the area 71 between the source and drain areas 72 and partially overlapping with these, and with a gate electrode 74 on the gate oxide film 73 .

The flash EEPROM then includes a negative voltage NMOS area 80 . This region 80 includes a deep n-type well 81 in the p-type substrate 100 , a flat p-type well 82 in the deep n-type well 81 , source and drain regions 83 of the n + type in the shallow p-type well 82 which are equally spaced from each other, a Gatoxidfilm 84 on the p-type substrate 100 between the source and drain regions 83 of n + type, which overlaps with the source and drain regions 83 and a gate electrode 85 on the gate oxide film 84 .

Finally, the flash EEPROM according to FIG. 5a also contains a memory cell 90 . which has the following: a deep n-type well 91 in the p-type substrate 100 , a flat p-type well 92 in the deep n-type well 91 , source and drain regions 93 of the n⁺-type in the shallow p-type well 92 , which are evenly spaced from each other, a gate oxide film 94 on the p-type substrate 100 between the n + source and drain regions 93 , which overlaps with these regions 93 , a floating gate 95 on the gate oxide film 94 , a control gate 97 above the floating gate 95 , and an interface insulation film 96 between the control gate 97 and the floating gate 95 to isolate the latter from one another.

In the flash EEPROM according to FIG. 5a, a voltage of +5 V is applied to the memory cell 90 for erasing, as can be seen in FIG. 5b. A voltage of +5 V is also applied to the flat p-type well 92 , while a voltage of -11 to -13 V is applied to the control gate 97 .

Since the voltage of 5 V reaches the flat p-type well 92 of the memory cell 90 , it is necessary to make the flat p-type well 71 of the peripheral NMOS region 70 opposite the flat p-type well 92 of the memory cell 90 isolate.

For this reason, the memory cell 90 has a triple well structure formed by the p-type substrate 100 , the deep n-type well 91 and the flat p-type well 92 .

FIG. 5b shows the state of the bias voltages of the memory cell 90 when the EEPROM according to FIG. 5a is erased.

In the flash EEPROMs according to FIGS . 3 to 5b, however, the problems explained below occur.

Two problems arise with the structure according to FIG. 3, since a high voltage of 13 V is applied to the source region 43 when erasing, while the substrate 41 is grounded.

The first problem is to be seen in the fact that the semiconductor junction can break down at the source region 43 .

The second problem is that there is a deep depletion area in an area 48 where floating gate 45 and source area 43 overlap. In the deep depletion area, electron-hole pairs are created, due to a tunnel from band to band. As a result of an existing electric field, the holes produced become hot holes, which are then captured in the gate oxide film 47 . The holes trapped in the gate oxide film 47 contribute to the enlargement of the tunneling current of the electrons during the quenching process. This can lead to excessive deletion or over-deletion.

In order to overcome both problems, according to Figure a source region with tiefgeneigtem transition provided. 3 44 surrounding the shallow source region 43. A double n⁻ / n⁺ diffusion process is required to produce regions 44 and 43 . The formation of such a source region 44 with a strongly inclined or low-lying transition therefore leads to a more complicated production process and to difficulties in scaling or reducing the memory device.

On the other hand, in the structure of FIG. 4, a high positive voltage of about 5 V is applied to the source region 53 , while the control gate 55 receives a high negative voltage of -11 to -13 V in order to solve the problem described above, which occurs when too high a voltage is applied to the source area during the erase operation.

With this negative gate deletion method, too, the generation of hot holes, which arise from tunneling from band to band, is only incompletely prevented, although the risk of a barrier layer breakdown at the source region can already be eliminated. Tunneling from band to band is mainly determined by the voltage difference between the control gate 55 and the source region 53 .

On the other hand, in the structures according to FIGS. 5a and 5b, an extinguishing method is used which makes use of FN tunneling, with charge carriers tunneling from the floating gate to the channel area. As a result, the above problems relating to the generation of hot holes during the erasure can be avoided, so that FN tunneling no longer occurs between the source region and the negative gate.

The canal is in the extinguishing process according to NEC technology rich not in a deep state of impoverishment, but in a hole collecting state, since it consists of p-type silicon. As a result occurs no tunneling from tape to tape, so that no hot holes occur stand.

However, since a voltage of +5 V is applied to the flat p-type well 92 of the memory cell during the erase, the flat p-type well 71 of the peripheral NMOS region 70 should be compared to the flat p-type well 92 of FIG Storage location 90 must be isolated.

For this reason, the memory cell 90 has a triple well structure formed by the substrate 100 , the deep n-type well 91 and the flat p-type well 92 . However, this leads to difficulties in optimizing cell production compared to a structure in which only a single p-type well is required.

The use of a triple well structure for a memory cell array also makes it difficult to make contact for the deep n-type well 91 that lies between the flat p-type well 92 of the cell 90 and the substrate 100 because of the memory cell array occupies at least 50% of the total chip area. The technology therefore leads to an enlargement of the cell array area.

On the other hand, a pump circuit for negative charges must be used in order to be able to supply the control gate 97 with the high negative voltage. For this purpose, the negative voltage NMOS region 80 is on the substrate 100 between the NMOS region 70 and the memory cell 90 in the technology proposed by NEC.

However, if a high negative voltage is applied to the flat p-type well 82 of the negative voltage NMOS region 80 , the flat p-type well 82 must be isolated from the flat p-type well 71 of the peripheral NMOS region 70 his. This also leads to the formation of a triple well structure, now in the negative voltage NMOS region 80 .

The invention has for its object in connection with the Disadvantages described to overcome and a To create EEPROM with triple well CMOS structure, in which in a Loads accumulated in a floating gate through FN tunnels into a Ka nal area can be deleted, and also a triple wall structure for the formation of a peripheral NMOS region comes to reduce the total needed in this way  chip area and to optimize or simplify the cells position procedure to come.

The solution to the problem is in the characterizing part of the patent claim 1 specified. Advantageous embodiments of the invention are can be found in the subclaims.

A flash EEPROM (immediately electrically erasable, programmable ROM) according to the invention is characterized by:

• - a substrate of a first conductivity type;
• a peripheral PMOS area with a flat first A second type of tub within the silicon sub strats of the first conductivity type, first source and drain regions in the flat first tub of the second conduction type, which is the same mig are spaced from each other, a first gate oxide film the substrate of the first conductivity type, which matches the first Source and drain areas overlap, as well as with a first Gate electrode on the gate oxide film;
• - A peripheral NMOS area with a deep second well of the second line type in the silicon substrate of the first line typs, a flat third tub of the first conduction type in the tie fen second tub, second source and drain areas in the fla Chen third tub that is evenly spaced apart are, a second gate oxide film on the silicon substrate, the overlaps second source and drain regions, and with a two th gate electrode on the second gate oxide film;
• - A memory cell with a flat fourth tub of the first Line type within the silicon substrate of the first line typs, third source and drain areas within the flat fourth trough, which are evenly spaced from each other, a third gate oxide film on the silicon substrate that coincides with overlaps the third source and drain regions, a floating gate or not connected gate on the third gate oxide film, a control gate above the floating gate, and with a  Interface or intermediate insulation film between the tax gate and floating gate to isolate both from each other;
• a negative voltage source for supplying a relatively high negative voltage V _G to the control gate of the memory cell during a flash erase operation (a fast erase operation);
• a first positive voltage source for supplying a relatively low positive voltage V _N to the flat first well of the peripheral PMOS region and to the deep second well of the NMOS region during the flash erase process;
• a reference voltage source for supplying a reference voltage V _R of 0 V to the flat third well of the peripheral NMOS region; and
• - A second positive voltage source for supplying a voltage V _P , which is not higher than the positive voltage of the first positive voltage source, to the flat fourth well of the memory cell during the flash erase process.

The invention is described below with reference to the drawing explained in more detail. Show it:

FIG. 1a is a cross section through a conventional EEPROM cell;

FIG. 1b a cross section of a conventional EEPROM cell CMOS / NMOS type;

Figs. 2a and 2b EEPROM cells that are deleted in accordance with Fowler-Nordheim;

Fig. 2c shows a cross section through a conventional MNOS cell;

Fig. 3 is a cross section of a conventional flash EEPROM cell;

Fig. 4 shows a cross section through another conven tional flash EEPROM cell;

FIG. 5a is a cross-sectional view of a flash EEPROM cell with conventional Dreifachwannen- CMOS structure;

Figure 5b is a detail from Figure 5a for explaining bias voltages which are applied during erasure of a memory cell of the flash EEPROM cell..;

FIG. 6a shows a cross section matching with a flash EEPROM having triple well CMOS structure in accordance with an embodiment of the invention; and

Fig. 6b the flash EEPROM according to Fig. 6a with applied voltage before deletion.

Fig. 6a shows a cross section through a flash EEPROM with triple wells or triple potential wells CMOS structure in accordance with the invention.

In this flash EEPROM according to the invention, signals are thereby deleted that accumulated charges in a floating gate Tunnels (Fowler-Nordheim tunnels) discharged into a channel area become. Furthermore, there is a flash EEPROM according to the invention Triple well structure or triple potential well structure for be A peripheral NMOS area is used while its memory cell only a single tub structure is used, namely a p-type tub  or potential well structure.

Referring to FIG. 6a, the flash EEPROM of the invention includes a peri eral NMOS region 120 having a Dreifachwannen- or triple potential well structure consisting of a p-type substrate 140, ei ner deep n-type well 121 and a flat p-type tub 122 . The flash EEPROM also includes a memory cell 130 that has only a flat p-type well 131 .

When erased, a voltage of +5 V is applied to the deep n-type well 121 of the peripheral NMOS region 120 , which is identical to that applied to the p-substrate 140 , so that the flat p- Type well 122 of the peripheral NMOS region 120 can be separated from the p-type well 131 of the memory cell 130 .

In addition, the flash EEPROM according to the invention includes a peripheral PMOS region 110 with a flat n-type well 111 inside the substrate 140 , with source and drain regions 112 of the p⁺-type inside the n-type well 111 , with a gate insulation film 113 and with a gate electrode 114 on the gate insulation film 113 , which lies in the area between the source and drain region 112 on the substrate 140 and partially overlaps the source and drain regions.

The peripheral NMOS region 120 consists of the deep n-type well 121 , which is located within the substrate 140 , of the flat p-type well 122 , which lies within the deep n-type well 121 , from the source - And drain regions 123 of the n⁺-type, which are located at a distance from one another within the p-type well 122 , from a gate insulation film 124 on the substrate 140 , the gate insulation film 124 lying between the source and drain regions 123 and itself partially overlapped with these, and from a gate electrode 125 on the gate insulation film 124 .

The areas 111 and 121 are connected to a common voltage connection, while the area 122 is connected to a separate voltage connection.

The memory cell 130 further includes a flat p-type well 131 , which lies within the substrate 140 , source and drain regions 132 of the n + type, which lie at a distance from one another within the p-type well 131 , a gate insulation film 133 between the areas 132 on the substrate 140 , which partially overlaps with the source and drain areas 132 , a floating gate 134 on the gate insulation film 133 , a control gate 136 above the floating gate 134 and an interface insulation film 135 between the control gate 136 and the floating gate 134 to isolate the two from each other.

The control gate 136 is connected to a voltage connection, while the region 131 is also connected to a voltage connection.

In the flash EEPROM according to the invention with the structure described above, a high negative voltage of -11 to -13 V is applied to the memory cell 130 during erasure, according to FIG. 6b, more precisely to the control gate 136 , which receives the voltage V _G. Furthermore, a low positive voltage Vcc of approximately +5 V is applied to the flat n-type well 111 of the peripheral PMOS region 110 and to the deep n-type well 121 of the peripheral NMOS region 120 . On the other hand, a reference voltage of 0 V gets to the flat p-type well 122 of the peripheral NMOS region 120 , while a voltage identical to or less than the voltage Vcc applied to the flat n-type well 111 and the deep one n-type well 121 has also been applied to the flat p-type well 131 of the memory cell 130 . The source and drain regions 112 , 123 and 132 are meanwhile at floating potential or remain unconnected. Signals or charges that have accumulated in the floating gate 134 can therefore be deleted in this way by FN tunnels into the channel area.

A number of advantages can be achieved according to the invention.

First, the cell production can be simplified or optimized, since the memory cell has only a single p-type well structure. It It is therefore easy to control the doping profile of the cell channel deliver.

Second, the total chip area required can be reduced since the memory cell, which requires at least 50% of the total chip area, has only a single or p-type well structure. This also facilitates the formation of contact with the deep n-type well of the peripheral NMOS region 120 .

Third is a pump circuit for generating a negative charge used to create a high negative voltage during the erase process to be able to deliver to the gate is the p-type well, which is that of the pump circuit generated high negative voltage receives, against which p-type well of the peripheral NMOS region isolated. As a result, it is not required for the pump circuit generating the negative charge to provide a triple tray structure.

Claims (3)

1. Immediately electrically erasable, programmable read-only memory (Flash EEPROM), characterized by :

• - a substrate ( 140 ) of a first conductivity type;
• - A peripheral PMOS area ( 110 ) with a flat first well ( 111 ) of a second conductivity type within the silicon substrate ( 140 ) of the first conductivity type, first source and drain areas ( 112 ) in the flat first well ( 111 ) of the second Conduction type, which are uniformly spaced from each other, a first gate oxide film ( 113 ) on the substrate ( 140 ) of the first conduction type, which overlaps with the first source and drain regions ( 112 ), and with a first gate electrode ( 114 ) on the Gate oxide film ( 113 );
• - A peripheral NMOS region ( 120 ) with a deep second well of the second conductivity type in the silicon substrate ( 140 ) of the first conductivity type, a flat third well ( 122 ) of the first conductivity type in the deep second well ( 121 ), second source and drain regions ( 123 ) in the flat third well ( 122 ), which are evenly spaced from one another, a second gate oxide film ( 124 ) on the silicon substrate ( 140 ), which overlaps the second source and drain regions ( 123 ), and with a second gate electrode ( 125 ) on the second gate oxide film ( 124 );
• - A memory cell ( 130 ) with a flat fourth well ( 131 ) of the first conductivity type within the silicon substrate ( 140 ) of the first conductivity type, third source and drain regions ( 132 ) within the flat fourth well ( 131 ), which are evenly spaced from one another , a third gate oxide film ( 133 ) on the silicon substrate, which overlaps with the third source and drain regions ( 132 ), a floating gate ( 134 ) or non-connected gate on the third gate oxide film ( 133 ), a control gate ( 136 ) above the floating gate ( 134 ), and with an interface film ( 135 ) between the control gate ( 136 ) and the floating gate ( 134 ) to isolate the two from each other;
• - a negative voltage source (V _G ) for supplying a relatively high negative voltage to the control gate ( 136 ) of the memory cell ( 130 ) during a flash erase process (a fast erase process);
• - a first positive voltage source for supplying a relatively never positive voltage to the flat first well ( 111 ) of the peripheral PMOS region ( 110 ) and to the deep second well ( 121 ) of the NMOS region ( 120 ) during the flash erase operation;
• - a reference voltage source for supplying a reference voltage of 0 V to the flat third well ( 122 ) of the peripheral NMOS region ( 120 ); and
• - A second positive voltage source for supplying a voltage that is not higher than the positive voltage of the first positive voltage source, to the flat fourth well ( 131 ) of the memory cell ( 130 ) during the flash erase process.

2. Flash EEPROM according to claim 1, characterized in that the negative voltage supplied by the negative voltage source to the control gate ( 136 ) is in the range from -11 V to -13 V. 3. Flash EEPROM according to claim 1, characterized in that the positive voltage applied to the first well ( 111 ) of the peripheral PMOS area ( 110 ) and to the second well ( 121 ) of the peripheral NMOS area ( 120 ) is in the range of +0.5 V to +5.0 V.