DE50211238D1 - SOI-Scheibe - Google Patents
SOI-ScheibeInfo
- Publication number
- DE50211238D1 DE50211238D1 DE50211238T DE50211238T DE50211238D1 DE 50211238 D1 DE50211238 D1 DE 50211238D1 DE 50211238 T DE50211238 T DE 50211238T DE 50211238 T DE50211238 T DE 50211238T DE 50211238 D1 DE50211238 D1 DE 50211238D1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- silicon
- semiconductor material
- hollow chambers
- soi wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Magnetic Record Carriers (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Manufacturing Of Electric Cables (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10131249A DE10131249A1 (de) | 2001-06-28 | 2001-06-28 | Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material |
Publications (1)
Publication Number | Publication Date |
---|---|
DE50211238D1 true DE50211238D1 (de) | 2007-12-27 |
Family
ID=7689811
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10131249A Withdrawn DE10131249A1 (de) | 2001-06-28 | 2001-06-28 | Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material |
DE50211238T Expired - Lifetime DE50211238D1 (de) | 2001-06-28 | 2002-06-27 | SOI-Scheibe |
DE50206581T Expired - Lifetime DE50206581D1 (de) | 2001-06-28 | 2002-06-27 | Film oder schicht aus halbleitendem material und verfahren zur herstellung des films oder der schicht |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10131249A Withdrawn DE10131249A1 (de) | 2001-06-28 | 2001-06-28 | Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE50206581T Expired - Lifetime DE50206581D1 (de) | 2001-06-28 | 2002-06-27 | Film oder schicht aus halbleitendem material und verfahren zur herstellung des films oder der schicht |
Country Status (9)
Country | Link |
---|---|
US (2) | US7052948B2 (de) |
EP (2) | EP1626440B1 (de) |
JP (1) | JP4331593B2 (de) |
KR (1) | KR100587997B1 (de) |
CN (1) | CN100372060C (de) |
AT (1) | ATE324670T1 (de) |
DE (3) | DE10131249A1 (de) |
TW (1) | TW575910B (de) |
WO (1) | WO2003003430A2 (de) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4277481B2 (ja) * | 2002-05-08 | 2009-06-10 | 日本電気株式会社 | 半導体基板の製造方法、半導体装置の製造方法 |
JP2004039735A (ja) * | 2002-07-01 | 2004-02-05 | Fujitsu Ltd | 半導体基板及びその製造方法 |
EP2280412A3 (de) * | 2002-11-29 | 2011-02-16 | STMicroelectronics S.r.l. | Halbleitersubstrat mit mindestens einem vergrabenen Hohlraum |
TW582099B (en) * | 2003-03-13 | 2004-04-01 | Ind Tech Res Inst | Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate |
DE10326578B4 (de) * | 2003-06-12 | 2006-01-19 | Siltronic Ag | Verfahren zur Herstellung einer SOI-Scheibe |
DE10336271B4 (de) * | 2003-08-07 | 2008-02-07 | Siltronic Ag | Siliciumscheibe und Verfahren zu deren Herstellung |
KR100605497B1 (ko) * | 2003-11-27 | 2006-07-28 | 삼성전자주식회사 | 에스오아이 기판들을 제조하는 방법들, 이를 사용하여반도체 소자들을 제조하는 방법들 및 그에 의해 제조된반도체 소자들 |
EP1577656B1 (de) * | 2004-03-19 | 2010-06-09 | STMicroelectronics Srl | Halbleiterdrucksensor und Verfahren zur Herstellung |
JP4626175B2 (ja) * | 2004-04-09 | 2011-02-02 | 株式会社Sumco | Soi基板の製造方法 |
DE102004021113B4 (de) * | 2004-04-29 | 2006-04-20 | Siltronic Ag | SOI-Scheibe und Verfahren zu ihrer Herstellung |
DE102004030612B3 (de) * | 2004-06-24 | 2006-04-20 | Siltronic Ag | Halbleitersubstrat und Verfahren zu dessen Herstellung |
KR100555569B1 (ko) | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
US20100117152A1 (en) * | 2007-06-28 | 2010-05-13 | Chang-Woo Oh | Semiconductor devices |
KR100843717B1 (ko) * | 2007-06-28 | 2008-07-04 | 삼성전자주식회사 | 플로팅 바디 소자 및 벌크 바디 소자를 갖는 반도체소자 및그 제조방법 |
DE102004041378B4 (de) | 2004-08-26 | 2010-07-08 | Siltronic Ag | Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung |
DE602004010117D1 (de) * | 2004-09-16 | 2007-12-27 | St Microelectronics Srl | Verfahren zur Hestellung von zusammengestzten Halbleiterplättchen mittels Schichtübertragung |
DE102004054564B4 (de) * | 2004-11-11 | 2008-11-27 | Siltronic Ag | Halbleitersubstrat und Verfahren zu dessen Herstellung |
DE102004062356A1 (de) * | 2004-12-23 | 2006-07-13 | Siltronic Ag | Halbleiterscheibe mit einer Halbleiterschicht und einer darunter liegenden elektrisch isolierenden Schicht sowie Verfahren zu deren Herstellung |
DE102005000826A1 (de) | 2005-01-05 | 2006-07-20 | Siltronic Ag | Halbleiterscheibe mit Silicium-Germanium-Schicht und Verfahren zu deren Herstellung |
FR2884647B1 (fr) * | 2005-04-15 | 2008-02-22 | Soitec Silicon On Insulator | Traitement de plaques de semi-conducteurs |
EP1719993A1 (de) * | 2005-05-06 | 2006-11-08 | STMicroelectronics S.r.l. | Integrierter Differenzdrucksensor und Verfahren zu dessen Herstellung |
CN1312328C (zh) * | 2005-05-16 | 2007-04-25 | 浙江大学 | 用于纳米光子技术的单晶硅纳米膜的制备方法 |
US7629209B2 (en) * | 2005-10-17 | 2009-12-08 | Chunghwa Picture Tubes, Ltd. | Methods for fabricating polysilicon film and thin film transistors |
JP4342503B2 (ja) * | 2005-10-20 | 2009-10-14 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置および半導体装置の検査方法 |
KR101171189B1 (ko) * | 2005-10-21 | 2012-08-06 | 삼성전자주식회사 | 더미 글래스 기판과 표시장치의 제조방법 |
FR2895563B1 (fr) * | 2005-12-22 | 2008-04-04 | Soitec Silicon On Insulator | Procede de simplification d'une sequence de finition et structure obtenue par le procede |
US7799640B2 (en) * | 2006-09-28 | 2010-09-21 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device having trench charge compensation regions |
KR100882932B1 (ko) * | 2007-06-11 | 2009-02-10 | 삼성전자주식회사 | 반도체 기판 및 그 제조 방법, 반도체 소자의 제조 방법 및이미지 센서의 제조 방법 |
US20090280588A1 (en) * | 2008-05-06 | 2009-11-12 | Leo Mathew | Method of forming an electronic device including removing a differential etch layer |
EP2161741B1 (de) * | 2008-09-03 | 2014-06-11 | Soitec | Verfahren zur Herstellung eines Halbleiters auf einem Isoliersubstrat mit verringerter SECCO-Fehlerdichte |
US20100187572A1 (en) * | 2009-01-26 | 2010-07-29 | Cho Hans S | Suspended mono-crystalline structure and method of fabrication from a heteroepitaxial layer |
DE102009030298B4 (de) | 2009-06-24 | 2012-07-12 | Siltronic Ag | Verfahren zur lokalen Politur einer Halbleiterscheibe |
JP5585056B2 (ja) * | 2009-11-19 | 2014-09-10 | 富士電機株式会社 | Son半導体基板の製造方法 |
JP5891597B2 (ja) * | 2011-04-07 | 2016-03-23 | 富士電機株式会社 | 半導体基板または半導体装置の製造方法 |
CN102294655A (zh) * | 2011-08-10 | 2011-12-28 | 开化美盛电子科技有限公司 | 一种粘固硅棒的载体的制作方法 |
US9406551B2 (en) * | 2012-09-27 | 2016-08-02 | Infineon Technologies Austria Ag | Method for manufacturing a semiconductor substrate, and method for manufacturing semiconductor devices integrated in a semiconductor substrate |
DE102015209889B4 (de) | 2015-05-29 | 2018-12-06 | Siltronic Ag | Strukturierte Halbleiterscheibe und Verfahren zu deren Herstellung |
US10833175B2 (en) * | 2015-06-04 | 2020-11-10 | International Business Machines Corporation | Formation of dislocation-free SiGe finFET using porous silicon |
US10933634B2 (en) | 2016-08-03 | 2021-03-02 | Hewlett-Packard Development Company, L.P. | Conductive wire disposed in a layer |
DE102019106124A1 (de) | 2018-03-22 | 2019-09-26 | Infineon Technologies Ag | Bilden von Halbleitervorrichtungen in Siliciumcarbid |
US10943813B2 (en) | 2018-07-13 | 2021-03-09 | Globalwafers Co., Ltd. | Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability |
FR3091000B1 (fr) * | 2018-12-24 | 2020-12-04 | Soitec Silicon On Insulator | Procede de fabrication d’un substrat pour un capteur d’image de type face avant |
US11710656B2 (en) * | 2019-09-30 | 2023-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor-on-insulator (SOI) substrate |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP2901031B2 (ja) * | 1992-01-30 | 1999-06-02 | キヤノン株式会社 | 半導体基材及びその作製方法 |
DE69333619T2 (de) * | 1992-01-30 | 2005-09-29 | Canon K.K. | Herstellungsverfahren für Halbleitersubstrate |
US5427055A (en) | 1992-01-31 | 1995-06-27 | Canon Kabushiki Kaisha | Method for controlling roughness on surface of monocrystal |
FR2715503B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Substrat pour composants intégrés comportant une couche mince et son procédé de réalisation. |
JP3352340B2 (ja) | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | 半導体基体とその製造方法 |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
DE19637182A1 (de) * | 1996-09-12 | 1998-03-19 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung von Halbleiterscheiben aus Silicium mit geringer Defektdichte |
SG65697A1 (en) | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
US6162705A (en) | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
US6255731B1 (en) * | 1997-07-30 | 2001-07-03 | Canon Kabushiki Kaisha | SOI bonding structure |
JP3324469B2 (ja) | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP3472171B2 (ja) * | 1997-12-26 | 2003-12-02 | キヤノン株式会社 | 半導体基材のエッチング方法及びエッチング装置並びにそれを用いた半導体基材の作製方法 |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3618254B2 (ja) * | 1998-06-02 | 2005-02-09 | 信越半導体株式会社 | Soi基板の製造方法 |
JP3762144B2 (ja) * | 1998-06-18 | 2006-04-05 | キヤノン株式会社 | Soi基板の作製方法 |
TW465101B (en) * | 1998-09-04 | 2001-11-21 | Canon Kk | Semiconductor substrate and method for producing the same |
EP0996145A3 (de) * | 1998-09-04 | 2000-11-08 | Canon Kabushiki Kaisha | Verfahren zur Herstellung von Halbleitersubstraten |
JP2000188269A (ja) * | 1998-10-16 | 2000-07-04 | Canon Inc | 部材の分離方法及び分離装置並びに基板の製造方法 |
JP2000124092A (ja) * | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
US6326279B1 (en) * | 1999-03-26 | 2001-12-04 | Canon Kabushiki Kaisha | Process for producing semiconductor article |
JP3453544B2 (ja) * | 1999-03-26 | 2003-10-06 | キヤノン株式会社 | 半導体部材の作製方法 |
JP4074051B2 (ja) * | 1999-08-31 | 2008-04-09 | 株式会社東芝 | 半導体基板およびその製造方法 |
JP3994602B2 (ja) * | 1999-11-12 | 2007-10-24 | 信越半導体株式会社 | シリコン単結晶ウエーハおよびその製造方法並びにsoiウエーハ |
US6660606B2 (en) * | 2000-09-29 | 2003-12-09 | Canon Kabushiki Kaisha | Semiconductor-on-insulator annealing method |
US6489217B1 (en) * | 2001-07-03 | 2002-12-03 | Maxim Integrated Products, Inc. | Method of forming an integrated circuit on a low loss substrate |
-
2001
- 2001-06-28 DE DE10131249A patent/DE10131249A1/de not_active Withdrawn
-
2002
- 2002-06-27 EP EP05021844A patent/EP1626440B1/de not_active Expired - Lifetime
- 2002-06-27 EP EP02758281A patent/EP1402567B1/de not_active Expired - Lifetime
- 2002-06-27 KR KR1020037016800A patent/KR100587997B1/ko active IP Right Grant
- 2002-06-27 TW TW91114122A patent/TW575910B/zh not_active IP Right Cessation
- 2002-06-27 JP JP2003509512A patent/JP4331593B2/ja not_active Expired - Lifetime
- 2002-06-27 CN CNB028131630A patent/CN100372060C/zh not_active Expired - Lifetime
- 2002-06-27 DE DE50211238T patent/DE50211238D1/de not_active Expired - Lifetime
- 2002-06-27 AT AT02758281T patent/ATE324670T1/de not_active IP Right Cessation
- 2002-06-27 US US10/481,537 patent/US7052948B2/en not_active Expired - Lifetime
- 2002-06-27 DE DE50206581T patent/DE50206581D1/de not_active Expired - Lifetime
- 2002-06-27 WO PCT/EP2002/007125 patent/WO2003003430A2/de active IP Right Grant
-
2006
- 2006-03-20 US US11/384,887 patent/US7417297B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1522461A (zh) | 2004-08-18 |
DE10131249A1 (de) | 2002-05-23 |
US20040142542A1 (en) | 2004-07-22 |
US7052948B2 (en) | 2006-05-30 |
DE50206581D1 (de) | 2006-06-01 |
JP4331593B2 (ja) | 2009-09-16 |
ATE324670T1 (de) | 2006-05-15 |
KR100587997B1 (ko) | 2006-06-08 |
WO2003003430A2 (de) | 2003-01-09 |
US20060202310A1 (en) | 2006-09-14 |
EP1402567A2 (de) | 2004-03-31 |
KR20040015282A (ko) | 2004-02-18 |
JP2004533726A (ja) | 2004-11-04 |
EP1402567B1 (de) | 2006-04-26 |
CN100372060C (zh) | 2008-02-27 |
EP1626440A1 (de) | 2006-02-15 |
WO2003003430A3 (de) | 2003-03-20 |
TW575910B (en) | 2004-02-11 |
US7417297B2 (en) | 2008-08-26 |
EP1626440B1 (de) | 2007-11-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |