DE60118490D1 - Logisches Allzweckmodul und Zelle mit einem solchen Modul - Google Patents

Logisches Allzweckmodul und Zelle mit einem solchen Modul

Info

Publication number
DE60118490D1
DE60118490D1 DE60118490T DE60118490T DE60118490D1 DE 60118490 D1 DE60118490 D1 DE 60118490D1 DE 60118490 T DE60118490 T DE 60118490T DE 60118490 T DE60118490 T DE 60118490T DE 60118490 D1 DE60118490 D1 DE 60118490D1
Authority
DE
Germany
Prior art keywords
module
cell
general purpose
logical general
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60118490T
Other languages
English (en)
Other versions
DE60118490T2 (de
Inventor
Masaharu Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE60118490D1 publication Critical patent/DE60118490D1/de
Application granted granted Critical
Publication of DE60118490T2 publication Critical patent/DE60118490T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
DE60118490T 2000-10-19 2001-10-18 Logisches Allzweckmodul und Zelle mit einem solchen Modul Expired - Fee Related DE60118490T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2000319269 2000-10-19
JP2000319269 2000-10-19
JP2000349627A JP3555080B2 (ja) 2000-10-19 2000-11-16 汎用ロジックモジュール及びこれを用いたセル
JP2000349627 2000-11-16

Publications (2)

Publication Number Publication Date
DE60118490D1 true DE60118490D1 (de) 2006-05-18
DE60118490T2 DE60118490T2 (de) 2006-11-16

Family

ID=26602401

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60118490T Expired - Fee Related DE60118490T2 (de) 2000-10-19 2001-10-18 Logisches Allzweckmodul und Zelle mit einem solchen Modul

Country Status (5)

Country Link
US (2) US6674307B2 (de)
EP (1) EP1199802B1 (de)
JP (1) JP3555080B2 (de)
DE (1) DE60118490T2 (de)
TW (1) TWI247483B (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3555080B2 (ja) * 2000-10-19 2004-08-18 Ｎｅｃエレクトロニクス株式会社 汎用ロジックモジュール及びこれを用いたセル
JP4156864B2 (ja) * 2002-05-17 2008-09-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
JP2003338750A (ja) * 2002-05-20 2003-11-28 Nec Electronics Corp 汎用ロジックセル、これを用いた汎用ロジックセルアレイ、及びこの汎用ロジックセルアレイを用いたａｓｉｃ
JP2004112653A (ja) 2002-09-20 2004-04-08 Nec Electronics Corp 半導体装置
US6919647B2 (en) * 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7015547B2 (en) * 2003-07-03 2006-03-21 American Semiconductor, Inc. Multi-configurable independently multi-gated MOSFET
US7019342B2 (en) * 2003-07-03 2006-03-28 American Semiconductor, Inc. Double-gated transistor circuit
JP4368722B2 (ja) 2004-03-31 2009-11-18 Ｎｅｃエレクトロニクス株式会社 汎用ロジックセルを備えた半導体装置
JP4471776B2 (ja) 2004-08-16 2010-06-02 Ｎｅｃエレクトロニクス株式会社 半導体装置、半導体装置の製造方法
US7411424B2 (en) * 2006-01-27 2008-08-12 Klp International, Ltd. Programmable logic function generator using non-volatile programmable memory switches
JP2007299800A (ja) 2006-04-27 2007-11-15 Nec Electronics Corp 半導体集積回路装置
CN101878592B (zh) 2007-12-28 2012-11-07 夏普株式会社 半导体装置和显示装置
CN101861617B (zh) 2007-12-28 2012-11-28 夏普株式会社 显示驱动电路和显示装置
WO2009084269A1 (ja) 2007-12-28 2009-07-09 Sharp Kabushiki Kaisha 半導体装置及び表示装置
JP4970552B2 (ja) 2007-12-28 2012-07-11 シャープ株式会社 補助容量配線駆動回路および表示装置
JP5058856B2 (ja) * 2008-03-17 2012-10-24 セイコーＮｐｃ株式会社 発振回路
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
CN106030824B (zh) * 2014-03-27 2020-07-28 英特尔公司 利用具有隧穿场效应晶体管(tfet)的电路实施的复用器逻辑功能

Family Cites Families (24)

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Publication number Priority date Publication date Assignee Title
US4910417A (en) 1986-09-19 1990-03-20 Actel Corporation Universal logic module comprising multiplexers
US5243208A (en) 1987-05-27 1993-09-07 Hitachi, Ltd. Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array
JPH02222217A (ja) 1989-02-22 1990-09-05 Toshiba Corp プログラマブル論理回路
US5055718A (en) 1990-05-11 1991-10-08 Actel Corporation Logic module with configurable combinational and sequential blocks
JPH05167048A (ja) 1991-12-13 1993-07-02 Kawasaki Steel Corp ゲートアレー
US5898636A (en) 1993-06-21 1999-04-27 Hitachi, Ltd. Semiconductor integrated circuit device with interleaved memory and logic blocks
EP0824791B1 (de) 1995-05-03 2003-10-15 Btr, Inc. Skalierbare vielstufige verbindungsarchitektur
US5684412A (en) 1995-08-18 1997-11-04 Chip Express (Israel) Ltd. Cell forming part of a customizable logic array
US5646558A (en) * 1995-09-27 1997-07-08 Intel Corporation Plurality of distinct multiplexers that operate as a single multiplexer
US5955912A (en) 1995-10-25 1999-09-21 Texas Instruments Incorporated Multiplexer circuits
JPH09148916A (ja) 1995-11-24 1997-06-06 Nec Corp 半導体集積回路
KR0170723B1 (ko) 1995-12-29 1999-03-30 김광호 단일 ras 신호에 의해 동시 동작이 가능한 이중 뱅크를 갖는 반도체 메모리 장치
JPH1074843A (ja) 1996-06-28 1998-03-17 Toshiba Corp 多電源集積回路および多電源集積回路システム
JP3180700B2 (ja) 1997-02-03 2001-06-25 日本電気株式会社 半導体集積回路装置
TW399319B (en) 1997-03-19 2000-07-21 Hitachi Ltd Semiconductor device
US6014038A (en) 1997-03-21 2000-01-11 Lightspeed Semiconductor Corporation Function block architecture for gate array
US6242767B1 (en) 1997-11-10 2001-06-05 Lightspeed Semiconductor Corp. Asic routing architecture
JPH11265998A (ja) 1998-01-13 1999-09-28 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
US6020772A (en) * 1998-02-05 2000-02-01 International Business Machines Corporation Flash output LSSD latch
JP3986036B2 (ja) * 1999-04-16 2007-10-03 株式会社日立製作所 半導体集積回路装置
JP2001148464A (ja) 1999-11-18 2001-05-29 Toshiba Microelectronics Corp 半導体集積回路
JP3555080B2 (ja) * 2000-10-19 2004-08-18 Ｎｅｃエレクトロニクス株式会社 汎用ロジックモジュール及びこれを用いたセル
US6580289B2 (en) 2001-06-08 2003-06-17 Viasic, Inc. Cell architecture to reduce customization in a semiconductor device
US6873185B2 (en) 2002-06-19 2005-03-29 Viasic, Inc. Logic array devices having complex macro-cell architecture and methods facilitating use of same

Also Published As

Publication number Publication date
TWI247483B (en) 2006-01-11
DE60118490T2 (de) 2006-11-16
JP2002198801A (ja) 2002-07-12
US6924671B2 (en) 2005-08-02
US20030201798A1 (en) 2003-10-30
EP1199802B1 (de) 2006-04-05
JP3555080B2 (ja) 2004-08-18
US6674307B2 (en) 2004-01-06
EP1199802A3 (de) 2003-01-02
US20020047727A1 (en) 2002-04-25
EP1199802A2 (de) 2002-04-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee