DE602004001948D1 - Verfahren zum Trennen von Platten, die miteinander geklebt sind und eine gestapelte Struktur bilden - Google Patents
Verfahren zum Trennen von Platten, die miteinander geklebt sind und eine gestapelte Struktur bildenInfo
- Publication number
- DE602004001948D1 DE602004001948D1 DE602004001948T DE602004001948T DE602004001948D1 DE 602004001948 D1 DE602004001948 D1 DE 602004001948D1 DE 602004001948 T DE602004001948 T DE 602004001948T DE 602004001948 T DE602004001948 T DE 602004001948T DE 602004001948 D1 DE602004001948 D1 DE 602004001948D1
- Authority
- DE
- Germany
- Prior art keywords
- stacked structure
- glued together
- separating plates
- plane
- force
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000000926 separation method Methods 0.000 abstract 2
- 238000005452 bending Methods 0.000 abstract 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B43/00—Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
- B32B43/006—Delaminating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0350619 | 2003-09-30 | ||
FR0350619A FR2860178B1 (fr) | 2003-09-30 | 2003-09-30 | Procede de separation de plaques collees entre elles pour constituer une structure empilee. |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004001948D1 true DE602004001948D1 (de) | 2006-09-28 |
DE602004001948T2 DE602004001948T2 (de) | 2007-08-30 |
Family
ID=34307542
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004001948T Active DE602004001948T2 (de) | 2003-09-30 | 2004-09-23 | Verfahren zum Trennen von Platten, die miteinander geklebt sind und eine gestapelte Struktur bilden |
Country Status (6)
Country | Link |
---|---|
US (1) | US7264996B2 (de) |
EP (1) | EP1520669B1 (de) |
JP (1) | JP5165830B2 (de) |
AT (1) | ATE336344T1 (de) |
DE (1) | DE602004001948T2 (de) |
FR (1) | FR2860178B1 (de) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2880184B1 (fr) | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
US20060275954A1 (en) * | 2005-06-06 | 2006-12-07 | Triquint Semiconductor, Inc. | Method for removing a cover from a semiconductor wafer |
US7601271B2 (en) * | 2005-11-28 | 2009-10-13 | S.O.I.Tec Silicon On Insulator Technologies | Process and equipment for bonding by molecular adhesion |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8366873B2 (en) * | 2010-04-15 | 2013-02-05 | Suss Microtec Lithography, Gmbh | Debonding equipment and methods for debonding temporary bonded wafers |
US8950459B2 (en) | 2009-04-16 | 2015-02-10 | Suss Microtec Lithography Gmbh | Debonding temporarily bonded semiconductor wafers |
JP5902406B2 (ja) * | 2010-06-25 | 2016-04-13 | 株式会社半導体エネルギー研究所 | 分離方法および半導体装置の作製方法 |
US8524572B2 (en) * | 2011-10-06 | 2013-09-03 | Micron Technology, Inc. | Methods of processing units comprising crystalline materials, and methods of forming semiconductor-on-insulator constructions |
JP2013191746A (ja) * | 2012-03-14 | 2013-09-26 | Toshiba Corp | 半導体装置の製造方法、半導体製造装置 |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
US20160225613A1 (en) * | 2013-09-25 | 2016-08-04 | Shibaura Mechatronics Corporation | Substrate treatment device, peeling method for laminated substrate, and method for removing adhesive |
US20180323105A1 (en) * | 2017-05-02 | 2018-11-08 | Psemi Corporation | Simultaneous Break and Expansion System for Integrated Circuit Wafers |
US10573547B1 (en) * | 2018-11-05 | 2020-02-25 | Honeywell Federal Manufacturing & Technologies, Llc | Apparatus and method for facilitating planar delayering of integrated circuit die |
FR3129622B1 (fr) * | 2021-11-26 | 2023-10-27 | Nelumbo Digital | Système pour déformer une structure utile |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3507426A (en) * | 1968-02-23 | 1970-04-21 | Rca Corp | Method of dicing semiconductor wafers |
JPS61145839A (ja) * | 1984-12-20 | 1986-07-03 | Toshiba Corp | 半導体ウエ−ハの接着方法および接着治具 |
JP3262470B2 (ja) * | 1993-12-28 | 2002-03-04 | キヤノン株式会社 | 半導体基板およびその作製方法 |
FR2725074B1 (fr) * | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat |
KR0165467B1 (ko) * | 1995-10-31 | 1999-02-01 | 김광호 | 웨이퍼 디본더 및 이를 이용한 웨이퍼 디본딩법 |
FR2767604B1 (fr) * | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
FR2789518B1 (fr) * | 1999-02-10 | 2003-06-20 | Commissariat Energie Atomique | Structure multicouche a contraintes internes controlees et procede de realisation d'une telle structure |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
JP3580227B2 (ja) * | 2000-06-21 | 2004-10-20 | 三菱住友シリコン株式会社 | 複合基板の分離方法及び分離装置 |
FR2835095B1 (fr) * | 2002-01-22 | 2005-03-18 | Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique | |
US6979630B2 (en) * | 2002-08-08 | 2005-12-27 | Isonics Corporation | Method and apparatus for transferring a thin layer of semiconductor material |
AU2002349422A1 (en) * | 2002-12-05 | 2004-06-23 | Mimasu Semiconductor Industory Co., Ltd. | Wafer separation apparatus |
-
2003
- 2003-09-30 FR FR0350619A patent/FR2860178B1/fr not_active Expired - Fee Related
-
2004
- 2004-09-23 EP EP04104612A patent/EP1520669B1/de active Active
- 2004-09-23 US US10/947,134 patent/US7264996B2/en active Active
- 2004-09-23 DE DE602004001948T patent/DE602004001948T2/de active Active
- 2004-09-23 AT AT04104612T patent/ATE336344T1/de not_active IP Right Cessation
- 2004-09-29 JP JP2004285138A patent/JP5165830B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
US20050112847A1 (en) | 2005-05-26 |
JP2005109503A (ja) | 2005-04-21 |
EP1520669B1 (de) | 2006-08-16 |
JP5165830B2 (ja) | 2013-03-21 |
ATE336344T1 (de) | 2006-09-15 |
DE602004001948T2 (de) | 2007-08-30 |
FR2860178A1 (fr) | 2005-04-01 |
EP1520669A1 (de) | 2005-04-06 |
US7264996B2 (en) | 2007-09-04 |
FR2860178B1 (fr) | 2005-11-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |