DE602004011353D1 - Verfahren zur Herstellung einer verspannten Silizium-Schicht auf einem Substrat und Zwischenprodukt - Google Patents
Verfahren zur Herstellung einer verspannten Silizium-Schicht auf einem Substrat und ZwischenproduktInfo
- Publication number
- DE602004011353D1 DE602004011353D1 DE602004011353T DE602004011353T DE602004011353D1 DE 602004011353 D1 DE602004011353 D1 DE 602004011353D1 DE 602004011353 T DE602004011353 T DE 602004011353T DE 602004011353 T DE602004011353 T DE 602004011353T DE 602004011353 D1 DE602004011353 D1 DE 602004011353D1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- strained silicon
- intermediate product
- auxiliary sige
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04292482A EP1650794B1 (de) | 2004-10-19 | 2004-10-19 | Verfahren zur Herstellung einer verspannten Silizium-Schicht auf einem Substrat und Zwischenprodukt |
Publications (2)
Publication Number | Publication Date |
---|---|
DE602004011353D1 true DE602004011353D1 (de) | 2008-03-06 |
DE602004011353T2 DE602004011353T2 (de) | 2008-05-15 |
Family
ID=34931465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004011353T Active DE602004011353T2 (de) | 2004-10-19 | 2004-10-19 | Verfahren zur Herstellung einer verspannten Silizium-Schicht auf einem Substrat und Zwischenprodukt |
Country Status (8)
Country | Link |
---|---|
US (1) | US7465646B2 (de) |
EP (1) | EP1650794B1 (de) |
JP (1) | JP5026685B2 (de) |
KR (1) | KR100747710B1 (de) |
CN (1) | CN100369191C (de) |
AT (1) | ATE384336T1 (de) |
DE (1) | DE602004011353T2 (de) |
SG (1) | SG122004A1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2773261B1 (fr) | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
FR2861497B1 (fr) | 2003-10-28 | 2006-02-10 | Soitec Silicon On Insulator | Procede de transfert catastrophique d'une couche fine apres co-implantation |
FR2891281B1 (fr) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | Procede de fabrication d'un element en couches minces. |
FR2902233B1 (fr) * | 2006-06-09 | 2008-10-17 | Soitec Silicon On Insulator | Procede de limitation de diffusion en mode lacunaire dans une heterostructure |
FR2947098A1 (fr) * | 2009-06-18 | 2010-12-24 | Commissariat Energie Atomique | Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince |
CN103165420B (zh) * | 2011-12-14 | 2015-11-18 | 中国科学院上海微系统与信息技术研究所 | 一种SiGe中嵌入超晶格制备应变Si的方法 |
US8946054B2 (en) | 2013-04-19 | 2015-02-03 | International Business Machines Corporation | Crack control for substrate separation |
RU2546858C1 (ru) * | 2013-11-29 | 2015-04-10 | Юрий Георгиевич Шретер | Способ изготовления полупроводниковых приборных структур, основанный на клонировании исходных подложек (варианты) |
FR3051595B1 (fr) * | 2016-05-17 | 2022-11-18 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat de type semi-conducteur contraint sur isolant |
CN106098608B (zh) * | 2016-06-20 | 2018-11-16 | 西安电子科技大学 | 基于氮化硅应力薄膜与尺度效应的SiN埋绝缘层上晶圆级单轴应变SiGe的制作方法 |
CN106098612B (zh) * | 2016-06-20 | 2020-01-31 | 西安电子科技大学 | 基于氮化硅应力薄膜与尺度效应的SiN埋绝缘层上晶圆级单轴应变Ge的制作方法 |
CN106067441B (zh) * | 2016-06-20 | 2019-01-29 | 西安电子科技大学 | 基于非晶化与尺度效应的晶圆级单轴应变sgoi的制作方法 |
CN106098610B (zh) * | 2016-06-20 | 2019-01-08 | 西安电子科技大学 | 基于氮化硅应力薄膜与尺度效应的AlN埋绝缘层上晶圆级单轴应变Ge的制作方法 |
CN105938814B (zh) * | 2016-06-20 | 2018-09-11 | 西安电子科技大学 | 基于氮化硅应力薄膜与尺度效应的AlN埋绝缘层上晶圆级单轴应变Si的制作方法 |
CN106098611B (zh) * | 2016-06-20 | 2019-01-08 | 西安电子科技大学 | 基于氮化硅应力薄膜与尺度效应的晶圆级单轴应变sgoi的制作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4804633A (en) | 1988-02-18 | 1989-02-14 | Northern Telecom Limited | Silicon-on-insulator substrates annealed in polysilicon tube |
JP2752799B2 (ja) | 1991-03-27 | 1998-05-18 | 三菱マテリアル株式会社 | Soi基板の製造方法 |
US5461243A (en) * | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
US5788763A (en) | 1995-03-09 | 1998-08-04 | Toshiba Ceramics Co., Ltd. | Manufacturing method of a silicon wafer having a controlled BMD concentration |
FR2777115B1 (fr) | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
JP2002305293A (ja) * | 2001-04-06 | 2002-10-18 | Canon Inc | 半導体部材の製造方法及び半導体装置の製造方法 |
JP3927778B2 (ja) | 2001-07-09 | 2007-06-13 | 住友電気工業株式会社 | エピタキシャルウエハとその製造方法 |
JP2003158250A (ja) * | 2001-10-30 | 2003-05-30 | Sharp Corp | SiGe/SOIのCMOSおよびその製造方法 |
US6805962B2 (en) * | 2002-01-23 | 2004-10-19 | International Business Machines Corporation | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
WO2004019404A2 (en) * | 2002-08-26 | 2004-03-04 | S.O.I.Tec Silicon On Insulator Technologies | Recycling a wafer comprising a buffer layer, after having taken off a thin layer therefrom |
WO2004021420A2 (en) * | 2002-08-29 | 2004-03-11 | Massachusetts Institute Of Technology | Fabrication method for a monocrystalline semiconductor layer on a substrate |
US6774015B1 (en) * | 2002-12-19 | 2004-08-10 | International Business Machines Corporation | Strained silicon-on-insulator (SSOI) and method to form the same |
-
2004
- 2004-10-19 DE DE602004011353T patent/DE602004011353T2/de active Active
- 2004-10-19 AT AT04292482T patent/ATE384336T1/de not_active IP Right Cessation
- 2004-10-19 EP EP04292482A patent/EP1650794B1/de active Active
-
2005
- 2005-03-14 US US11/080,936 patent/US7465646B2/en active Active
- 2005-09-16 JP JP2005270891A patent/JP5026685B2/ja active Active
- 2005-09-26 CN CNB2005101050831A patent/CN100369191C/zh active Active
- 2005-10-18 KR KR1020050098130A patent/KR100747710B1/ko active IP Right Grant
- 2005-10-19 SG SG200506799A patent/SG122004A1/en unknown
Also Published As
Publication number | Publication date |
---|---|
DE602004011353T2 (de) | 2008-05-15 |
CN1767148A (zh) | 2006-05-03 |
CN100369191C (zh) | 2008-02-13 |
ATE384336T1 (de) | 2008-02-15 |
KR100747710B1 (ko) | 2007-08-08 |
SG122004A1 (en) | 2006-05-26 |
EP1650794A1 (de) | 2006-04-26 |
US20060081847A1 (en) | 2006-04-20 |
US7465646B2 (en) | 2008-12-16 |
JP5026685B2 (ja) | 2012-09-12 |
EP1650794B1 (de) | 2008-01-16 |
KR20060054079A (ko) | 2006-05-22 |
JP2006121055A (ja) | 2006-05-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
R082 | Change of representative |
Ref document number: 1650794 Country of ref document: EP Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE |
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R081 | Change of applicant/patentee |
Ref document number: 1650794 Country of ref document: EP Owner name: SOITEC, FR Free format text: FORMER OWNER: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A., BERNIN, FR Effective date: 20120905 |
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R082 | Change of representative |
Ref document number: 1650794 Country of ref document: EP Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE Effective date: 20120905 |