DE602006014156D1 - Stromsparverfahren und -vorrichtungen für anweisungen variabler länge - Google Patents

Stromsparverfahren und -vorrichtungen für anweisungen variabler länge

Info

Publication number
DE602006014156D1
DE602006014156D1 DE602006014156T DE602006014156T DE602006014156D1 DE 602006014156 D1 DE602006014156 D1 DE 602006014156D1 DE 602006014156 T DE602006014156 T DE 602006014156T DE 602006014156 T DE602006014156 T DE 602006014156T DE 602006014156 D1 DE602006014156 D1 DE 602006014156D1
Authority
DE
Germany
Prior art keywords
instructions
processor
instruction cache
variable length
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006014156T
Other languages
English (en)
Inventor
Brian Michael Stempel
James Norris Dieffenderfer
Jeffrey Todd Bridges
Rodney Wayne Smith
Thomas Andrew Sartorius
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE602006014156D1 publication Critical patent/DE602006014156D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G06F9/30152—Determining start or end of instruction; determining instruction length
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE602006014156T 2005-03-04 2006-03-03 Stromsparverfahren und -vorrichtungen für anweisungen variabler länge Active DE602006014156D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/073,284 US7421568B2 (en) 2005-03-04 2005-03-04 Power saving methods and apparatus to selectively enable cache bits based on known processor state
PCT/US2006/007758 WO2006096568A2 (en) 2005-03-04 2006-03-03 Power saving methods and apparatus for variable length instructions

Publications (1)

Publication Number Publication Date
DE602006014156D1 true DE602006014156D1 (de) 2010-06-17

Family

ID=36695266

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006014156T Active DE602006014156D1 (de) 2005-03-04 2006-03-03 Stromsparverfahren und -vorrichtungen für anweisungen variabler länge

Country Status (11)

Country Link
US (1) US7421568B2 (de)
EP (1) EP1904922B1 (de)
JP (1) JP4791495B2 (de)
KR (1) KR100942408B1 (de)
CN (1) CN101164040B (de)
AT (1) ATE467170T1 (de)
DE (1) DE602006014156D1 (de)
ES (1) ES2341993T3 (de)
IL (1) IL185594A0 (de)
MX (1) MX2007010773A (de)
WO (1) WO2006096568A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7769983B2 (en) 2005-05-18 2010-08-03 Qualcomm Incorporated Caching instructions for a multiple-state processor
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
US7836285B2 (en) * 2007-08-08 2010-11-16 Analog Devices, Inc. Implementation of variable length instruction encoding using alias addressing
US8898437B2 (en) * 2007-11-02 2014-11-25 Qualcomm Incorporated Predecode repair cache for instructions that cross an instruction cache line
US10055227B2 (en) 2012-02-07 2018-08-21 Qualcomm Incorporated Using the least significant bits of a called function's address to switch processor modes
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
US10235232B2 (en) * 2014-02-10 2019-03-19 Via Alliance Semiconductor Co., Ltd Processor with approximate computing execution unit that includes an approximation control register having an approximation mode flag, an approximation amount, and an error threshold, where the approximation control register is writable by an instruction set instruction
US9588845B2 (en) 2014-02-10 2017-03-07 Via Alliance Semiconductor Co., Ltd. Processor that recovers from excessive approximate computing error
US9916251B2 (en) 2014-12-01 2018-03-13 Samsung Electronics Co., Ltd. Display driving apparatus and cache managing method thereof
US9727353B2 (en) 2015-10-30 2017-08-08 International Business Machines Corporation Simultaneously capturing status information for multiple operating modes
CN115878187B (zh) * 2023-01-16 2023-05-02 北京微核芯科技有限公司 支持压缩指令的处理器指令处理装置和方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115500A (en) * 1988-01-11 1992-05-19 International Business Machines Corporation Plural incompatible instruction format decode method and apparatus
JPH04257948A (ja) * 1991-02-13 1992-09-14 Fujitsu Ltd キャッシュメモリ、該キャッシュメモリを備えたシステムおよび該システムにおける命令デコード方式
US5499204A (en) * 1994-07-05 1996-03-12 Motorola, Inc. Memory cache with interlaced data and method of operation
US5640526A (en) 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
AU7168496A (en) * 1995-10-06 1997-04-28 Advanced Micro Devices Inc. Instruction predecode and multiple instruction decode
US6141745A (en) 1998-04-30 2000-10-31 Advanced Micro Devices, Inc. Functional bit identifying a prefix byte via a particular state regardless of type of instruction
US6092182A (en) * 1998-06-24 2000-07-18 Advanced Micro Devices, Inc. Using ECC/parity bits to store predecode information
US6253309B1 (en) * 1998-09-21 2001-06-26 Advanced Micro Devices, Inc. Forcing regularity into a CISC instruction set by padding instructions
US6275927B2 (en) * 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes
US6496923B1 (en) * 1999-12-17 2002-12-17 Intel Corporation Length decode to detect one-byte prefixes and branch
US6804799B2 (en) * 2001-06-26 2004-10-12 Advanced Micro Devices, Inc. Using type bits to track storage of ECC and predecode bits in a level two cache
US7058827B2 (en) * 2001-07-18 2006-06-06 Intel Corporation Power saving circuit has an input line coupled to an external host and a keeper to hold the line in a weakly held state
US6901490B2 (en) 2002-12-02 2005-05-31 Lsi Logic Corporation Read/modify/write registers

Also Published As

Publication number Publication date
WO2006096568A2 (en) 2006-09-14
EP1904922B1 (de) 2010-05-05
KR20070116058A (ko) 2007-12-06
KR100942408B1 (ko) 2010-02-17
EP1904922A2 (de) 2008-04-02
ES2341993T3 (es) 2010-06-30
CN101164040A (zh) 2008-04-16
JP2008532187A (ja) 2008-08-14
US7421568B2 (en) 2008-09-02
CN101164040B (zh) 2010-04-14
JP4791495B2 (ja) 2011-10-12
MX2007010773A (es) 2007-11-08
ATE467170T1 (de) 2010-05-15
IL185594A0 (en) 2008-01-06
US20060200686A1 (en) 2006-09-07
WO2006096568A3 (en) 2007-01-11

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