DE60210658D1 - Fehlerkorrigierende speicher und verfahren zu seiner nutzung - Google Patents
Fehlerkorrigierende speicher und verfahren zu seiner nutzungInfo
- Publication number
- DE60210658D1 DE60210658D1 DE60210658T DE60210658T DE60210658D1 DE 60210658 D1 DE60210658 D1 DE 60210658D1 DE 60210658 T DE60210658 T DE 60210658T DE 60210658 T DE60210658 T DE 60210658T DE 60210658 D1 DE60210658 D1 DE 60210658D1
- Authority
- DE
- Germany
- Prior art keywords
- write
- memory
- ecc
- penalty
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/003,602 US7051264B2 (en) | 2001-11-14 | 2001-11-14 | Error correcting memory and method of operating same |
US3602 | 2001-11-14 | ||
PCT/GB2002/005123 WO2003042826A2 (en) | 2001-11-14 | 2002-11-13 | Error correcting memory and method of operating same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60210658D1 true DE60210658D1 (de) | 2006-05-24 |
DE60210658T2 DE60210658T2 (de) | 2007-04-05 |
Family
ID=21706644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60210658T Expired - Lifetime DE60210658T2 (de) | 2001-11-14 | 2002-11-13 | Fehlerkorrigierende speicher und verfahren zu seiner nutzung |
Country Status (5)
Country | Link |
---|---|
US (2) | US7051264B2 (de) |
EP (1) | EP1449082B1 (de) |
DE (1) | DE60210658T2 (de) |
TW (1) | TW580709B (de) |
WO (1) | WO2003042826A2 (de) |
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-
2001
- 2001-11-14 US US10/003,602 patent/US7051264B2/en not_active Expired - Lifetime
-
2002
- 2002-11-08 TW TW091132971A patent/TW580709B/zh not_active IP Right Cessation
- 2002-11-13 DE DE60210658T patent/DE60210658T2/de not_active Expired - Lifetime
- 2002-11-13 EP EP02779675A patent/EP1449082B1/de not_active Expired - Lifetime
- 2002-11-13 WO PCT/GB2002/005123 patent/WO2003042826A2/en not_active Application Discontinuation
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Also Published As
Publication number | Publication date |
---|---|
DE60210658T2 (de) | 2007-04-05 |
TW200300258A (en) | 2003-05-16 |
US20030093744A1 (en) | 2003-05-15 |
US7051264B2 (en) | 2006-05-23 |
WO2003042826A3 (en) | 2004-04-22 |
WO2003042826A2 (en) | 2003-05-22 |
EP1449082A2 (de) | 2004-08-25 |
US7353438B2 (en) | 2008-04-01 |
TW580709B (en) | 2004-03-21 |
US20050044467A1 (en) | 2005-02-24 |
EP1449082B1 (de) | 2006-04-12 |
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