DE60301112D1 - Digitale Speicheranordnung - Google Patents

Digitale Speicheranordnung

Info

Publication number
DE60301112D1
DE60301112D1 DE60301112T DE60301112T DE60301112D1 DE 60301112 D1 DE60301112 D1 DE 60301112D1 DE 60301112 T DE60301112 T DE 60301112T DE 60301112 T DE60301112 T DE 60301112T DE 60301112 D1 DE60301112 D1 DE 60301112D1
Authority
DE
Germany
Prior art keywords
digital memory
memory arrangement
arrangement
digital
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60301112T
Other languages
English (en)
Other versions
DE60301112T2 (de
Inventor
Lung T Tran
Manoj K Bhattacharyya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60301112D1 publication Critical patent/DE60301112D1/de
Application granted granted Critical
Publication of DE60301112T2 publication Critical patent/DE60301112T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002Characteristic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006Current
DE60301112T 2002-09-03 2003-09-02 Digitale Speicheranordnung Expired - Lifetime DE60301112T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US232363 1994-04-25
US10/232,363 US6791865B2 (en) 2002-09-03 2002-09-03 Memory device capable of calibration and calibration methods therefor

Publications (2)

Publication Number Publication Date
DE60301112D1 true DE60301112D1 (de) 2005-09-01
DE60301112T2 DE60301112T2 (de) 2006-03-30

Family

ID=31976986

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60301112T Expired - Lifetime DE60301112T2 (de) 2002-09-03 2003-09-02 Digitale Speicheranordnung

Country Status (6)

Country Link
US (2) US6791865B2 (de)
EP (1) EP1403874B1 (de)
JP (1) JP2004095157A (de)
CN (1) CN100520957C (de)
DE (1) DE60301112T2 (de)
TW (1) TW200404307A (de)

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US7116576B2 (en) * 2003-07-07 2006-10-03 Hewlett-Packard Development Company, L.P. Sensing the state of a storage cell including a magnetic element
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US7369428B2 (en) * 2003-09-29 2008-05-06 Samsung Electronics Co., Ltd. Methods of operating a magnetic random access memory device and related devices and structures
KR100568512B1 (ko) * 2003-09-29 2006-04-07 삼성전자주식회사 열발생층을 갖는 자기열 램셀들 및 이를 구동시키는 방법들
US6990030B2 (en) * 2003-10-21 2006-01-24 Hewlett-Packard Development Company, L.P. Magnetic memory having a calibration system
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US7054185B2 (en) * 2003-11-30 2006-05-30 Union Semiconductor Technology Corporation Optimized MRAM current sources
US7113422B2 (en) * 2003-11-30 2006-09-26 Union Semiconductor Technology Corporation Method for optimizing MRAM circuit performance
US6850430B1 (en) * 2003-12-02 2005-02-01 Hewlett-Packard Development Company, L.P. Regulating a magnetic memory cell write current
US6980455B2 (en) * 2004-02-03 2005-12-27 Hewlett-Packard Development Company, L.P. Remote sensed pre-amplifier for cross-point arrays
US7079438B2 (en) * 2004-02-17 2006-07-18 Hewlett-Packard Development Company, L.P. Controlled temperature, thermal-assisted magnetic memory device
KR100541557B1 (ko) * 2004-04-13 2006-01-10 삼성전자주식회사 메모리 모듈 및 이 모듈의 반도체 메모리 장치의 임피던스교정 방법
US7635993B2 (en) * 2004-05-18 2009-12-22 Nxp B.V. Digital magnetic current sensor and logic
US7304905B2 (en) 2004-05-24 2007-12-04 Intel Corporation Throttling memory in response to an internal temperature of a memory device
US7222052B2 (en) * 2004-06-25 2007-05-22 Intel Corporation Temperature adaptive ferro-electric memory access parameters
US7085183B2 (en) * 2004-07-13 2006-08-01 Headway Technologies, Inc. Adaptive algorithm for MRAM manufacturing
KR100660539B1 (ko) * 2004-07-29 2006-12-22 삼성전자주식회사 자기 기억 소자 및 그 형성 방법
US7523285B2 (en) * 2004-08-20 2009-04-21 Intel Corporation Thermal memory control
US7068533B2 (en) * 2004-09-30 2006-06-27 Infineon Technologies Ag Resistive memory cell configuration and method for sensing resistance values
KR100564640B1 (ko) 2005-02-16 2006-03-28 삼성전자주식회사 온도측정기 동작지시신호 발생기 및 이를 구비하는 반도체메모리 장치
US7246022B2 (en) * 2005-06-20 2007-07-17 Intel Corporation Initiation of differential link retraining upon temperature excursion
US7511990B2 (en) * 2005-09-30 2009-03-31 Everspin Technologies, Inc. Magnetic tunnel junction temperature sensors
JP4830437B2 (ja) * 2005-10-03 2011-12-07 日本電気株式会社 磁気ランダムアクセスメモリ
KR101434398B1 (ko) * 2007-05-03 2014-09-23 삼성전자주식회사 고전압 발생 회로를 포함하는 플래시 메모리 장치 및그것의 동작 방법
US8100228B2 (en) * 2007-10-12 2012-01-24 D B Industries, Inc. Portable anchorage assembly
US7719884B2 (en) * 2008-05-19 2010-05-18 Qimonda Ag Integrated circuit, cell arrangement, method of manufacturing an integrated circuit, method of operating an integrated circuit, and memory module
KR101434400B1 (ko) * 2008-07-09 2014-08-27 삼성전자주식회사 불휘발성 메모리 장치 및 메모리 시스템 및 그것의 관리방법
US7804709B2 (en) * 2008-07-18 2010-09-28 Seagate Technology Llc Diode assisted switching spin-transfer torque memory unit
US8054677B2 (en) 2008-08-07 2011-11-08 Seagate Technology Llc Magnetic memory with strain-assisted exchange coupling switch
US8223532B2 (en) 2008-08-07 2012-07-17 Seagate Technology Llc Magnetic field assisted STRAM cells
JP5188328B2 (ja) * 2008-08-29 2013-04-24 株式会社日立製作所 半導体装置
US7746687B2 (en) 2008-09-30 2010-06-29 Seagate Technology, Llc Thermally assisted multi-bit MRAM
US8487390B2 (en) * 2008-10-08 2013-07-16 Seagate Technology Llc Memory cell with stress-induced anisotropy
US20100091564A1 (en) * 2008-10-10 2010-04-15 Seagate Technology Llc Magnetic stack having reduced switching current
US8217478B2 (en) * 2008-10-10 2012-07-10 Seagate Technology Llc Magnetic stack with oxide to reduce switching current
US8053255B2 (en) * 2009-03-03 2011-11-08 Seagate Technology Llc STRAM with compensation element and method of making the same
KR101161745B1 (ko) * 2009-06-05 2012-07-02 에스케이하이닉스 주식회사 반도체 메모리 장치
US8472274B2 (en) * 2011-03-02 2013-06-25 Apple Inc. Using temperature sensors with a memory device
US8462537B2 (en) * 2011-03-21 2013-06-11 Intel Corporation Method and apparatus to reset a phase change memory and switch (PCMS) memory cell
US8924765B2 (en) * 2011-07-03 2014-12-30 Ambiq Micro, Inc. Method and apparatus for low jitter distributed clock calibration
CN103023280B (zh) * 2012-08-27 2015-04-01 常熟开关制造有限公司(原常熟开关厂) 带散热器的变换器失电后的热记忆方法
JP2017139399A (ja) * 2016-02-05 2017-08-10 Tdk株式会社 磁気メモリ
US9728242B1 (en) 2016-03-04 2017-08-08 Kabushiki Kaisha Toshiba Memory device

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Also Published As

Publication number Publication date
EP1403874A1 (de) 2004-03-31
TW200404307A (en) 2004-03-16
DE60301112T2 (de) 2006-03-30
CN1487525A (zh) 2004-04-07
US6791874B2 (en) 2004-09-14
CN100520957C (zh) 2009-07-29
EP1403874B1 (de) 2005-07-27
JP2004095157A (ja) 2004-03-25
US20040141370A1 (en) 2004-07-22
US20040042262A1 (en) 2004-03-04
US6791865B2 (en) 2004-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SAMSUNG ELECTRONICS CO., LTD., SUWON, GYEONGGI, KR