DE60332613D1 - Verfahren zur manipulation von halbleiterschichten zum dünnmachen derselben - Google Patents
Verfahren zur manipulation von halbleiterschichten zum dünnmachen derselbenInfo
- Publication number
- DE60332613D1 DE60332613D1 DE60332613T DE60332613T DE60332613D1 DE 60332613 D1 DE60332613 D1 DE 60332613D1 DE 60332613 T DE60332613 T DE 60332613T DE 60332613 T DE60332613 T DE 60332613T DE 60332613 D1 DE60332613 D1 DE 60332613D1
- Authority
- DE
- Germany
- Prior art keywords
- wafer
- sub
- front face
- face
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
- B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
- B81C2203/033—Thermal bonding
- B81C2203/036—Fusion bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0203909A FR2837981B1 (fr) | 2002-03-28 | 2002-03-28 | Procede de manipulation de couches semiconductrices pour leur amincissement |
PCT/FR2003/000954 WO2003083930A1 (fr) | 2002-03-28 | 2003-03-26 | Procede de manipulation de couches semiconductrices pour leur amincissement |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60332613D1 true DE60332613D1 (de) | 2010-07-01 |
Family
ID=27839282
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60332613T Expired - Lifetime DE60332613D1 (de) | 2002-03-28 | 2003-03-26 | Verfahren zur manipulation von halbleiterschichten zum dünnmachen derselben |
Country Status (7)
Country | Link |
---|---|
US (1) | US7205211B2 (de) |
EP (1) | EP1497857B1 (de) |
JP (1) | JP4593116B2 (de) |
AT (1) | ATE468605T1 (de) |
DE (1) | DE60332613D1 (de) |
FR (1) | FR2837981B1 (de) |
WO (1) | WO2003083930A1 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2774511B1 (fr) * | 1998-01-30 | 2002-10-11 | Commissariat Energie Atomique | Substrat compliant en particulier pour un depot par hetero-epitaxie |
FR2857502B1 (fr) | 2003-07-10 | 2006-02-24 | Soitec Silicon On Insulator | Substrats pour systemes contraints |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
FR2860842B1 (fr) * | 2003-10-14 | 2007-11-02 | Tracit Technologies | Procede de preparation et d'assemblage de substrats |
DE10350036B4 (de) * | 2003-10-27 | 2014-01-23 | Robert Bosch Gmbh | Verfahren zum Vereinzeln von Halbleiterchips und entsprechende Halbleiterchipanordnung |
DE102004010956B9 (de) * | 2004-03-03 | 2010-08-05 | Infineon Technologies Ag | Halbleiterbauteil mit einem dünnen Halbleiterchip und einem steifen Verdrahtungssubstrat sowie Verfahren zur Herstellung und Weiterverarbeitung von dünnen Halbleiterchips |
US7381950B2 (en) * | 2004-09-29 | 2008-06-03 | Texas Instruments Incorporated | Characterizing dimensions of structures via scanning probe microscopy |
US7563691B2 (en) * | 2004-10-29 | 2009-07-21 | Hewlett-Packard Development Company, L.P. | Method for plasma enhanced bonding and bonded structures formed by plasma enhanced bonding |
FR2878076B1 (fr) * | 2004-11-17 | 2007-02-23 | St Microelectronics Sa | Amincissement d'une plaquette semiconductrice |
FR2879183B1 (fr) * | 2004-12-15 | 2007-04-27 | Atmel Grenoble Soc Par Actions | Procede de fabrication collective de microstructures a elements superposes |
JP4349278B2 (ja) * | 2004-12-24 | 2009-10-21 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
CN100383929C (zh) * | 2005-02-01 | 2008-04-23 | 矽品精密工业股份有限公司 | 一种半导体处理制程 |
US20070029043A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Pre-made cleavable substrate method and structure of fabricating devices using one or more films provided by a layer transfer process |
US20070032044A1 (en) * | 2005-08-08 | 2007-02-08 | Silicon Genesis Corporation | Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back |
US7166520B1 (en) | 2005-08-08 | 2007-01-23 | Silicon Genesis Corporation | Thin handle substrate method and structure for fabricating devices using one or more films provided by a layer transfer process |
DE102005048153B4 (de) * | 2005-10-06 | 2010-08-05 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauteils mit Halbleiterchip und Klebstofffolie |
FR2899594A1 (fr) | 2006-04-10 | 2007-10-12 | Commissariat Energie Atomique | Procede d'assemblage de substrats avec traitements thermiques a basses temperatures |
US8124499B2 (en) * | 2006-11-06 | 2012-02-28 | Silicon Genesis Corporation | Method and structure for thick layer transfer using a linear accelerator |
US20080128641A1 (en) * | 2006-11-08 | 2008-06-05 | Silicon Genesis Corporation | Apparatus and method for introducing particles using a radio frequency quadrupole linear accelerator for semiconductor materials |
US20080188011A1 (en) * | 2007-01-26 | 2008-08-07 | Silicon Genesis Corporation | Apparatus and method of temperature conrol during cleaving processes of thick film materials |
FR2919959B1 (fr) * | 2007-08-07 | 2009-12-18 | Commissariat Energie Atomique | Procede de transfert a basse temperature a partir d'une couche de molecules auto-assemblees |
DE102008001738A1 (de) * | 2008-05-14 | 2009-11-26 | Robert Bosch Gmbh | Verfahren zur Herstellung von Chips |
FR2936357B1 (fr) * | 2008-09-24 | 2010-12-10 | Commissariat Energie Atomique | Procede de report de puces sur un substrat. |
FR2938117B1 (fr) * | 2008-10-31 | 2011-04-15 | Commissariat Energie Atomique | Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
FR2953065A1 (fr) * | 2009-11-20 | 2011-05-27 | Commissariat Energie Atomique | Procede de realisation d'empilements sur plusieurs niveaux d'ensembles de puces electroniques |
SG177816A1 (en) * | 2010-07-15 | 2012-02-28 | Soitec Silicon On Insulator | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
US8481406B2 (en) | 2010-07-15 | 2013-07-09 | Soitec | Methods of forming bonded semiconductor structures |
US8461017B2 (en) | 2010-07-19 | 2013-06-11 | Soitec | Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region |
US9481566B2 (en) | 2012-07-31 | 2016-11-01 | Soitec | Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices |
CN105027436B (zh) | 2013-02-19 | 2018-04-24 | 日本碍子株式会社 | 复合基板、弹性波装置及弹性波装置的制造方法 |
US9248466B2 (en) | 2013-05-10 | 2016-02-02 | Infineon Technologies Ag | Application of fluids to substrates |
JP6469070B2 (ja) * | 2016-12-21 | 2019-02-13 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | 第1の基板を第2の基板から剥離する方法および可撓性の基板保持装置の使用 |
CN110838462B (zh) * | 2018-08-15 | 2022-12-13 | 北科天绘(合肥)激光技术有限公司 | 一种器件阵列的巨量转移方法及系统 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3287436B2 (ja) * | 1993-09-27 | 2002-06-04 | キヤノン株式会社 | 半導体装置の作製方法 |
FR2725074B1 (fr) * | 1994-09-22 | 1996-12-20 | Commissariat Energie Atomique | Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat |
FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
FR2767604B1 (fr) * | 1997-08-19 | 2000-12-01 | Commissariat Energie Atomique | Procede de traitement pour le collage moleculaire et le decollage de deux structures |
FR2781925B1 (fr) * | 1998-07-30 | 2001-11-23 | Commissariat Energie Atomique | Transfert selectif d'elements d'un support vers un autre support |
FR2796491B1 (fr) * | 1999-07-12 | 2001-08-31 | Commissariat Energie Atomique | Procede de decollement de deux elements et dispositif pour sa mise en oeuvre |
FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
US6303469B1 (en) * | 2000-06-07 | 2001-10-16 | Micron Technology, Inc. | Thin microelectronic substrates and methods of manufacture |
FR2816445B1 (fr) * | 2000-11-06 | 2003-07-25 | Commissariat Energie Atomique | Procede de fabrication d'une structure empilee comprenant une couche mince adherant a un substrat cible |
US7407869B2 (en) * | 2000-11-27 | 2008-08-05 | S.O.I.Tec Silicon On Insulator Technologies | Method for manufacturing a free-standing substrate made of monocrystalline semiconductor material |
US6989314B2 (en) * | 2003-02-12 | 2006-01-24 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Semiconductor structure and method of making same |
JP2004319538A (ja) * | 2003-04-10 | 2004-11-11 | Seiko Epson Corp | 半導体装置の製造方法、集積回路、電子光学装置及び電子機器 |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
FR2867310B1 (fr) * | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
JP2008513990A (ja) * | 2004-09-21 | 2008-05-01 | エス.オー.アイ.テック シリコン オン インシュレータ テクノロジーズ | 共注入および続いて注入を行うことにより薄層を得るための方法 |
-
2002
- 2002-03-28 FR FR0203909A patent/FR2837981B1/fr not_active Expired - Fee Related
-
2003
- 2003-03-26 DE DE60332613T patent/DE60332613D1/de not_active Expired - Lifetime
- 2003-03-26 US US10/509,007 patent/US7205211B2/en not_active Expired - Lifetime
- 2003-03-26 WO PCT/FR2003/000954 patent/WO2003083930A1/fr active Application Filing
- 2003-03-26 JP JP2003581250A patent/JP4593116B2/ja not_active Expired - Lifetime
- 2003-03-26 AT AT03727614T patent/ATE468605T1/de not_active IP Right Cessation
- 2003-03-26 EP EP03727614A patent/EP1497857B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2005528779A (ja) | 2005-09-22 |
JP4593116B2 (ja) | 2010-12-08 |
WO2003083930A1 (fr) | 2003-10-09 |
EP1497857A1 (de) | 2005-01-19 |
US7205211B2 (en) | 2007-04-17 |
EP1497857B1 (de) | 2010-05-19 |
ATE468605T1 (de) | 2010-06-15 |
FR2837981B1 (fr) | 2005-01-07 |
FR2837981A1 (fr) | 2003-10-03 |
US20050124138A1 (en) | 2005-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE60332613D1 (de) | Verfahren zur manipulation von halbleiterschichten zum dünnmachen derselben | |
EP1884989A3 (de) | Halbleiterbauelement und Herstellungsverfahren dafür | |
TW200509187A (en) | Substrate manufacturing method and substrate processing apparatus | |
EP1950800A3 (de) | Verfahren zur Herstellung eines III-V-Verbindungshalbleitersubstrats | |
TW200723440A (en) | Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same | |
DE602004013163D1 (de) | Verfahren zur Herstellung eines Germanium-On-Insulator-Wafers (GeOI) | |
WO2006039029A3 (en) | A method for forming a thin complete high-permittivity dielectric layer | |
TW200629377A (en) | Use of Cl2 and/or HCl during silicon epitaxial film formation | |
ATE511219T1 (de) | Verfahren zum ätzen von substraten | |
TW200603261A (en) | Method of forming a recessed structure employing a reverse tone process | |
TW200641519A (en) | Reduction of etch mask feature critical dimensions | |
EP1306889A3 (de) | Elektronische Anordnung mit einer Elektrode und ihre Herstellung | |
TW200534512A (en) | Fabrication of reflective layer on semiconductor light emitting diodes | |
CN109496368A (zh) | 微发光二极管装置及其制造方法 | |
EP1398825A3 (de) | Substrat und Herstellungsverfahren dafür | |
EP1467404A3 (de) | Gruppe III-Nitridschichten mit strukturierten Oberflächen | |
CN107039345A (zh) | 元件芯片的制造方法以及元件芯片 | |
EP1321972A3 (de) | Trimmverfahren für eine Struktur aus Photoresist und organischen Antireflexschicht | |
WO2003030238A1 (fr) | Procede de traitement | |
EP1467216A3 (de) | Verfahren zur Herstellung eines Magnetfelddetektors | |
TW200912053A (en) | Method of fabricating semiconductor substrate by use of heterogeneous substrate and recycling heterogeneous substrate during fabrication thereof | |
DE102004017411A1 (de) | In-situ-Metallbarriereablagerung für Sputterätzen auf einer Verbindungsstruktur | |
US20050130409A1 (en) | Controlled dry etch of a film | |
US20030148591A1 (en) | Method of forming semiconductor device | |
JP2006173354A (ja) | Soi基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |