DE68919069D1 - Verfahren und Gerät zur Fehlererkennung und -korrektur in einem nach dem überlappten Steuerungsverfahren arbeitenden Rechnersystem. - Google Patents

Verfahren und Gerät zur Fehlererkennung und -korrektur in einem nach dem überlappten Steuerungsverfahren arbeitenden Rechnersystem.

Info

Publication number
DE68919069D1
DE68919069D1 DE68919069T DE68919069T DE68919069D1 DE 68919069 D1 DE68919069 D1 DE 68919069D1 DE 68919069 T DE68919069 T DE 68919069T DE 68919069 T DE68919069 T DE 68919069T DE 68919069 D1 DE68919069 D1 DE 68919069D1
Authority
DE
Germany
Prior art keywords
execution
instruction
cpu
errors
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68919069T
Other languages
English (en)
Other versions
DE68919069T2 (de
Inventor
Richard C Beaven
Michael B Evans
Ricky C Hetherington
Tryggve Fossum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE68919069D1 publication Critical patent/DE68919069D1/de
Publication of DE68919069T2 publication Critical patent/DE68919069T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0781—Error filtering or prioritizing based on a policy defined by the user or on a policy defined by a hardware/software module, e.g. according to a severity level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
DE68919069T 1989-02-03 1989-09-22 Verfahren und Gerät zur Fehlererkennung und -korrektur in einem nach dem überlappten Steuerungsverfahren arbeitenden Rechnersystem. Expired - Fee Related DE68919069T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,828 US4982402A (en) 1989-02-03 1989-02-03 Method and apparatus for detecting and correcting errors in a pipelined computer system

Publications (2)

Publication Number Publication Date
DE68919069D1 true DE68919069D1 (de) 1994-12-01
DE68919069T2 DE68919069T2 (de) 1995-06-08

Family

ID=23187045

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68919069T Expired - Fee Related DE68919069T2 (de) 1989-02-03 1989-09-22 Verfahren und Gerät zur Fehlererkennung und -korrektur in einem nach dem überlappten Steuerungsverfahren arbeitenden Rechnersystem.

Country Status (6)

Country Link
US (1) US4982402A (de)
EP (1) EP0380858B1 (de)
JP (1) JPH02232737A (de)
AT (1) ATE113399T1 (de)
AU (1) AU628163B2 (de)
DE (1) DE68919069T2 (de)

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US5339399A (en) * 1991-04-12 1994-08-16 Intel Corporation Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
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US5561761A (en) * 1993-03-31 1996-10-01 Ylsi Technology, Inc. Central processing unit data entering and interrogating device and method therefor
US5701479A (en) * 1993-06-15 1997-12-23 Xerox Corporation Pipelined image processing system for a single application environment
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JP3373607B2 (ja) * 1993-09-01 2003-02-04 富士通株式会社 プロセッサの制御機構検証用命令列の自動生成方法及び装置
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US6044456A (en) * 1998-01-05 2000-03-28 Intel Corporation Electronic system and method for maintaining synchronization of multiple front-end pipelines
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US6493819B1 (en) * 1999-11-16 2002-12-10 Advanced Micro Devices, Inc. Merging narrow register for resolution of data dependencies when updating a portion of a register in a microprocessor
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US20040117583A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Apparatus for influencing process scheduling in a data processing system capable of utilizing a virtual memory processing scheme
US20040117590A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Aliasing support for a data processing system having no system memory
US20050055528A1 (en) * 2002-12-12 2005-03-10 International Business Machines Corporation Data processing system having a physically addressed cache of disk memory
US20040117588A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corporation Access request for a data processing system having no system memory
US20040117589A1 (en) * 2002-12-12 2004-06-17 International Business Machines Corp. Interrupt mechanism for a data processing system having hardware managed paging of disk data
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Also Published As

Publication number Publication date
EP0380858A2 (de) 1990-08-08
JPH02232737A (ja) 1990-09-14
AU628163B2 (en) 1992-09-10
EP0380858B1 (de) 1994-10-26
ATE113399T1 (de) 1994-11-15
DE68919069T2 (de) 1995-06-08
EP0380858A3 (de) 1991-08-28
US4982402A (en) 1991-01-01
AU5394590A (en) 1991-12-19

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee