DE68925263T2 - Verfahren zur Ausführung eines kombinierten Schalters zur Unterstützung von Parallelverarbeitung - Google Patents

Verfahren zur Ausführung eines kombinierten Schalters zur Unterstützung von Parallelverarbeitung

Info

Publication number
DE68925263T2
DE68925263T2 DE68925263T DE68925263T DE68925263T2 DE 68925263 T2 DE68925263 T2 DE 68925263T2 DE 68925263 T DE68925263 T DE 68925263T DE 68925263 T DE68925263 T DE 68925263T DE 68925263 T2 DE68925263 T2 DE 68925263T2
Authority
DE
Germany
Prior art keywords
executing
parallel processing
combined switch
support parallel
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68925263T
Other languages
English (en)
Other versions
DE68925263D1 (de
Inventor
William Cain Brantley
Harold Stuart Stone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68925263D1 publication Critical patent/DE68925263D1/de
Application granted granted Critical
Publication of DE68925263T2 publication Critical patent/DE68925263T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17375One dimensional, e.g. linear array, ring
DE68925263T 1988-11-02 1989-07-07 Verfahren zur Ausführung eines kombinierten Schalters zur Unterstützung von Parallelverarbeitung Expired - Fee Related DE68925263T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/266,424 US5163149A (en) 1988-11-02 1988-11-02 Combining switch for reducing accesses to memory and for synchronizing parallel processes

Publications (2)

Publication Number Publication Date
DE68925263D1 DE68925263D1 (de) 1996-02-08
DE68925263T2 true DE68925263T2 (de) 1996-07-11

Family

ID=23014537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68925263T Expired - Fee Related DE68925263T2 (de) 1988-11-02 1989-07-07 Verfahren zur Ausführung eines kombinierten Schalters zur Unterstützung von Parallelverarbeitung

Country Status (4)

Country Link
US (1) US5163149A (de)
EP (1) EP0366865B1 (de)
JP (1) JPH02137438A (de)
DE (1) DE68925263T2 (de)

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JP2526691B2 (ja) * 1990-03-02 1996-08-21 三菱電機株式会社 プログラマブルコントロ―ラの制御方法
US6047112A (en) * 1992-06-30 2000-04-04 Discovision Associates Technique for initiating processing of a data stream of encoded video information
US5768561A (en) * 1992-06-30 1998-06-16 Discovision Associates Tokens-based adaptive video processing arrangement
US6330665B1 (en) 1992-06-30 2001-12-11 Discovision Associates Video parser
DE69229338T2 (de) * 1992-06-30 1999-12-16 Discovision Ass Datenpipelinesystem
US5519877A (en) * 1993-01-12 1996-05-21 Matsushita Electric Industrial Co., Ltd. Apparatus for synchronizing parallel processing among a plurality of processors
US5604863A (en) * 1993-11-01 1997-02-18 International Business Machines Corporation Method for coordinating executing programs in a data processing system
US5495589A (en) * 1993-12-23 1996-02-27 Unisys Corporation Architecture for smart control of bi-directional transfer of data
US5600822A (en) * 1994-04-05 1997-02-04 International Business Machines Corporation Resource allocation synchronization in a parallel processing system
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
US6404752B1 (en) 1999-08-27 2002-06-11 International Business Machines Corporation Network switch using network processor and methods
US6460120B1 (en) 1999-08-27 2002-10-01 International Business Machines Corporation Network processor, memory organization and methods
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US7734868B2 (en) * 2003-12-02 2010-06-08 Nvidia Corporation Universal RAID class driver
WO2005106713A1 (ja) * 2004-04-28 2005-11-10 Shinji Furusho 情報処理方法及び情報処理システム
GB202112936D0 (en) * 2021-09-10 2021-10-27 Graphcore Ltd A network computer with external memory

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US4445171A (en) * 1981-04-01 1984-04-24 Teradata Corporation Data processing systems and methods
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US4495617A (en) * 1982-09-09 1985-01-22 A.B. Dick Company Signal generation and synchronizing circuit for a decentralized ring network
FR2533789B1 (fr) * 1982-09-24 1987-10-23 France Etat Reseau local hybride de communication en modes circuit et paquet a boucle portant un multiplex temporel
DE3270802D1 (en) * 1982-11-26 1986-05-28 Ibm Synchronization in a communication network of interconnected rings
US4677614A (en) * 1983-02-15 1987-06-30 Emc Controls, Inc. Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method
JPS59188256A (ja) * 1983-04-11 1984-10-25 Hitachi Ltd ル−プ伝送システムの伝送方法
US4530091A (en) * 1983-07-08 1985-07-16 At&T Bell Laboratories Synchronization of real-time clocks in a packet switching system
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US4704680A (en) * 1984-08-15 1987-11-03 Tektronix, Inc. Address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle
EP0194674B1 (de) * 1985-03-12 1992-06-24 Honda Giken Kogyo Kabushiki Kaisha Multiplexübertragungssystem
JPS61214694A (ja) * 1985-03-18 1986-09-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション データ伝送のスイッチング装置
JP2642332B2 (ja) * 1985-04-15 1997-08-20 株式会社日立製作所 優先レベル更新制御方法
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KR920001576B1 (ko) * 1987-09-09 1992-02-18 가부시끼가이샤 도시바 토큰패싱 버스 방식을 사용한 네트워크 시스템
US4833468A (en) * 1987-10-14 1989-05-23 Unisys Corporation Layered network
US4989131A (en) * 1988-07-26 1991-01-29 International Business Machines Corporation Technique for parallel synchronization
US4926446A (en) * 1988-11-25 1990-05-15 Alberta Telecommunications Research Centre Method and apparatus for precision time distribution in telecommunication networks

Also Published As

Publication number Publication date
EP0366865A2 (de) 1990-05-09
DE68925263D1 (de) 1996-02-08
JPH02137438A (ja) 1990-05-25
EP0366865B1 (de) 1995-12-27
EP0366865A3 (de) 1992-06-10
US5163149A (en) 1992-11-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee