DE69031978T2 - Einrichtung und Verfahren zum Vermindern von Störungen in zweistufigen Cache-Speichern - Google Patents

Einrichtung und Verfahren zum Vermindern von Störungen in zweistufigen Cache-Speichern

Info

Publication number
DE69031978T2
DE69031978T2 DE69031978T DE69031978T DE69031978T2 DE 69031978 T2 DE69031978 T2 DE 69031978T2 DE 69031978 T DE69031978 T DE 69031978T DE 69031978 T DE69031978 T DE 69031978T DE 69031978 T2 DE69031978 T2 DE 69031978T2
Authority
DE
Germany
Prior art keywords
reducing interference
tier caches
tier
caches
interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031978T
Other languages
English (en)
Other versions
DE69031978D1 (de
Inventor
Charles P Thacker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE69031978D1 publication Critical patent/DE69031978D1/de
Publication of DE69031978T2 publication Critical patent/DE69031978T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
DE69031978T 1989-12-22 1990-11-30 Einrichtung und Verfahren zum Vermindern von Störungen in zweistufigen Cache-Speichern Expired - Fee Related DE69031978T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/454,922 US5136700A (en) 1989-12-22 1989-12-22 Apparatus and method for reducing interference in two-level cache memories

Publications (2)

Publication Number Publication Date
DE69031978D1 DE69031978D1 (de) 1998-02-26
DE69031978T2 true DE69031978T2 (de) 1998-07-09

Family

ID=23806623

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031978T Expired - Fee Related DE69031978T2 (de) 1989-12-22 1990-11-30 Einrichtung und Verfahren zum Vermindern von Störungen in zweistufigen Cache-Speichern

Country Status (5)

Country Link
US (1) US5136700A (de)
EP (1) EP0434250B1 (de)
JP (1) JPH0797354B2 (de)
KR (1) KR100190351B1 (de)
DE (1) DE69031978T2 (de)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
JPH03240127A (ja) * 1990-02-17 1991-10-25 Hitachi Maxell Ltd プログラム制御システム
JPH05108484A (ja) * 1990-06-07 1993-04-30 Intel Corp キヤツシユメモリ
EP0461926B1 (de) * 1990-06-15 1998-09-02 Compaq Computer Corporation Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien
JP2708943B2 (ja) * 1990-08-08 1998-02-04 三菱電機株式会社 キャッシュメモリ制御装置
GB2256512B (en) * 1991-06-04 1995-03-15 Intel Corp Second level cache controller unit and system
US5386540A (en) * 1991-09-18 1995-01-31 Ncr Corporation Method and apparatus for transferring data within a computer using a burst sequence which includes modified bytes and a minimum number of unmodified bytes
EP0533373A3 (en) * 1991-09-18 1993-04-21 Ncr International Inc. Computer system having cache memory
US5649154A (en) * 1992-02-27 1997-07-15 Hewlett-Packard Company Cache memory system having secondary cache integrated with primary cache for use with VLSI circuits
US5457793A (en) * 1992-03-30 1995-10-10 International Business Machines Corporation Software cache management of a shared electronic store in a supplex
US5319766A (en) * 1992-04-24 1994-06-07 Digital Equipment Corporation Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
EP0568231B1 (de) * 1992-04-29 1999-03-10 Sun Microsystems, Inc. Verfahren und Vorrichtung für mehreren ausstehende Operationen in einem cachespeicherkohärenten Multiprozessorsystem
JPH05324468A (ja) * 1992-05-21 1993-12-07 Fujitsu Ltd 階層化キャッシュメモリ
JPH05342101A (ja) * 1992-06-12 1993-12-24 Fujitsu Ltd 階層キャッシュ・メモリ
US5522058A (en) * 1992-08-11 1996-05-28 Kabushiki Kaisha Toshiba Distributed shared-memory multiprocessor system with reduced traffic on shared bus
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
US5511226A (en) * 1992-08-25 1996-04-23 Intel Corporation System for generating snoop addresses and conditionally generating source addresses whenever there is no snoop hit, the source addresses lagging behind the corresponding snoop addresses
US5509135A (en) * 1992-09-25 1996-04-16 Digital Equipment Corporation Multi-index multi-way set-associative cache
EP0608622A1 (de) * 1993-01-29 1994-08-03 International Business Machines Corporation Mehrrechnersystem mit mehrstufigen Cachespeichern
US5689679A (en) * 1993-04-28 1997-11-18 Digital Equipment Corporation Memory system and method for selective multi-level caching using a cache level code
US5640531A (en) * 1993-06-22 1997-06-17 Unisys Corporation Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache
FR2707776B1 (fr) 1993-07-15 1995-08-18 Bull Sa Procédé de gestion de mémoires d'un système informatique, système informatique mémoire et support d'enregistrement mettant en Óoeuvre le procédé.
FR2707778B1 (fr) * 1993-07-15 1995-08-18 Bull Sa NÓoeud de processeurs.
FR2707777B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Ensemble informatique à mémoire partagée.
FR2707774B1 (fr) * 1993-07-15 1995-08-18 Bull Sa Procédé de gestion cohérente des échanges entre des niveaux d'une hiérarchie de mémoires à au moins trois niveaux.
JPH0784881A (ja) * 1993-09-13 1995-03-31 Mitsubishi Electric Corp キャッシュメモリ
US5809525A (en) * 1993-09-17 1998-09-15 International Business Machines Corporation Multi-level computer cache system providing plural cache controllers associated with memory address ranges and having cache directories
JP2566733B2 (ja) * 1993-12-09 1996-12-25 コナミ株式会社 Ｌａｎシステムのデータ相互伝送方法
US5572704A (en) * 1993-12-15 1996-11-05 Silicon Graphics, Inc. System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes
US6088768A (en) * 1993-12-28 2000-07-11 International Business Machines Corporation Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
US5832534A (en) * 1994-01-04 1998-11-03 Intel Corporation Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
US6049851A (en) * 1994-02-14 2000-04-11 Hewlett-Packard Company Method and apparatus for checking cache coherency in a computer architecture
US5561779A (en) * 1994-05-04 1996-10-01 Compaq Computer Corporation Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
US5551001A (en) * 1994-06-29 1996-08-27 Exponential Technology, Inc. Master-slave cache system for instruction and data cache memories
US5644752A (en) * 1994-06-29 1997-07-01 Exponential Technology, Inc. Combined store queue for a master-slave cache system
US5692152A (en) * 1994-06-29 1997-11-25 Exponential Technology, Inc. Master-slave cache system with de-coupled data and tag pipelines and loop-back
US5577227A (en) * 1994-08-04 1996-11-19 Finnell; James S. Method for decreasing penalty resulting from a cache miss in multi-level cache system
US5813031A (en) * 1994-09-21 1998-09-22 Industrial Technology Research Institute Caching tag for a large scale cache computer memory system
US5640534A (en) * 1994-10-05 1997-06-17 International Business Machines Corporation Method and system for concurrent access in a data cache array utilizing multiple match line selection paths
US6047357A (en) * 1995-01-27 2000-04-04 Digital Equipment Corporation High speed method for maintaining cache coherency in a multi-level, set associative cache hierarchy
US5740400A (en) * 1995-06-05 1998-04-14 Advanced Micro Devices Inc. Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache by using an inclusion field
US5850534A (en) * 1995-06-05 1998-12-15 Advanced Micro Devices, Inc. Method and apparatus for reducing cache snooping overhead in a multilevel cache system
US5740399A (en) * 1995-08-23 1998-04-14 International Business Machines Corporation Modified L1/L2 cache inclusion for aggressive prefetch
US5758119A (en) * 1995-08-23 1998-05-26 International Business Machines Corp. System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache
US6223260B1 (en) * 1996-01-25 2001-04-24 Unisys Corporation Multi-bus data processing system in which all data words in high level cache memories have any one of four states and all data words in low level cache memories have any one of three states
US6070233A (en) * 1996-01-26 2000-05-30 Unisys Corporation Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache
US5802563A (en) * 1996-07-01 1998-09-01 Sun Microsystems, Inc. Efficient storage of data in computer system with multiple cache levels
US6065097A (en) * 1996-08-29 2000-05-16 Sun Microsystems, Inc. Apparatus and method for sharing a unified memory bus between external cache memory and primary memory
US5752261A (en) * 1996-11-07 1998-05-12 Ncr Corporation Method and apparatus for detecting thrashing in a cache memory
US6202125B1 (en) 1996-11-25 2001-03-13 Intel Corporation Processor-cache protocol using simple commands to implement a range of cache configurations
US6021261A (en) * 1996-12-05 2000-02-01 International Business Machines Corporation Method and system for testing a multiprocessor data processing system utilizing a plurality of event tracers
US6122711A (en) 1997-01-07 2000-09-19 Unisys Corporation Method of and apparatus for store-in second level cache flush
US5987577A (en) * 1997-04-24 1999-11-16 International Business Machines Dual word enable method and apparatus for memory arrays
US6209072B1 (en) 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
US6000015A (en) * 1997-09-16 1999-12-07 Unisys Corporation Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache
US6122709A (en) * 1997-12-19 2000-09-19 Sun Microsystems, Inc. Cache with reduced tag information storage
KR100272165B1 (ko) * 1998-05-20 2000-11-15 윤종용 캐쉬 메모리 시스템 및 그의 운영 방법
US7013305B2 (en) 2001-10-01 2006-03-14 International Business Machines Corporation Managing the state of coupling facility structures, detecting by one or more systems coupled to the coupling facility, the suspended state of the duplexed command, detecting being independent of message exchange
KR100344065B1 (ko) * 2000-02-15 2002-07-24 전주식 다단계 캐시 구조의 공유 메모리 다중 프로세서 장치
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7412569B2 (en) * 2003-04-10 2008-08-12 Intel Corporation System and method to track changes in memory
CN101981545B (zh) 2008-01-31 2014-08-20 甲骨文国际公司 用于事务缓存的系统和方法
US8935485B2 (en) 2011-08-08 2015-01-13 Arm Limited Snoop filter and non-inclusive shared cache memory
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US4442487A (en) * 1981-12-31 1984-04-10 International Business Machines Corporation Three level memory hierarchy using write and share flags
US4807110A (en) * 1984-04-06 1989-02-21 International Business Machines Corporation Prefetching system for a cache having a second directory for sequentially accessed blocks
US4823259A (en) * 1984-06-29 1989-04-18 International Business Machines Corporation High speed buffer store arrangement for quick wide transfer of data
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4797814A (en) * 1986-05-01 1989-01-10 International Business Machines Corporation Variable address mode cache
FR2609195A1 (fr) * 1986-12-31 1988-07-01 Thomson Csf Procede de gestion d'antememoires associees a des processeurs dans une architecture multiprocesseur a bus unique et systeme de traitement de donnees fonctionnant suivant ce procede
US4831622A (en) * 1987-12-22 1989-05-16 Honeywell Bull Inc. Apparatus for forcing a reload from main memory upon cache memory error
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage

Also Published As

Publication number Publication date
JPH0797354B2 (ja) 1995-10-18
KR100190351B1 (ko) 1999-06-01
EP0434250A3 (en) 1992-01-08
EP0434250A2 (de) 1991-06-26
EP0434250B1 (de) 1998-01-21
DE69031978D1 (de) 1998-02-26
US5136700A (en) 1992-08-04
JPH05127992A (ja) 1993-05-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee