DE69033331T2 - Sprungvorhersage - Google Patents

Sprungvorhersage

Info

Publication number
DE69033331T2
DE69033331T2 DE69033331T DE69033331T DE69033331T2 DE 69033331 T2 DE69033331 T2 DE 69033331T2 DE 69033331 T DE69033331 T DE 69033331T DE 69033331 T DE69033331 T DE 69033331T DE 69033331 T2 DE69033331 T2 DE 69033331T2
Authority
DE
Germany
Prior art keywords
branch
cache
instruction
target address
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69033331T
Other languages
English (en)
Other versions
DE69033331D1 (de
Inventor
David B Fite
John E Murray
Dwight P Manley
Michael M Mckeon
Elaine H Fite
Ronald M Salett
Tryggve Fossum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE69033331D1 publication Critical patent/DE69033331D1/de
Publication of DE69033331T2 publication Critical patent/DE69033331T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842Speculative instruction execution
    • G06F9/3844Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
DE69033331T 1989-02-03 1990-01-30 Sprungvorhersage Expired - Lifetime DE69033331T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,760 US5142634A (en) 1989-02-03 1989-02-03 Branch prediction

Publications (2)

Publication Number Publication Date
DE69033331D1 DE69033331D1 (de) 1999-12-02
DE69033331T2 true DE69033331T2 (de) 2000-04-13

Family

ID=23186714

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69033331T Expired - Lifetime DE69033331T2 (de) 1989-02-03 1990-01-30 Sprungvorhersage

Country Status (6)

Country Link
US (1) US5142634A (de)
EP (1) EP0381444B1 (de)
JP (1) JPH02260033A (de)
AT (1) ATE186132T1 (de)
AU (1) AU631419B2 (de)
DE (1) DE69033331T2 (de)

Families Citing this family (172)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0404068A3 (de) * 1989-06-20 1991-12-27 Fujitsu Limited Vorrichtung zur Ausführung eines Verzweigungsbefehls
KR940000968B1 (ko) * 1989-08-28 1994-02-07 니뽄 덴끼 가부시끼가이샤 마이크로프로세서
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
CA2045790A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch prediction in high-performance processor
US5283873A (en) * 1990-06-29 1994-02-01 Digital Equipment Corporation Next line prediction apparatus for a pipelined computed system
CA2045791A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Branch performance in high speed processor
JP2504312B2 (ja) * 1990-08-29 1996-06-05 三菱電機株式会社 プライオリティエンコ―ダ及びそれを備えたデ―タ処理装置
WO1992006426A1 (en) * 1990-10-09 1992-04-16 Nexgen Microsystems Method and apparatus for parallel decoding of instructions with branch prediction look-up
JPH0820950B2 (ja) * 1990-10-09 1996-03-04 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチ予測型分岐予測機構
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
US5257354A (en) * 1991-01-16 1993-10-26 International Business Machines Corporation System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results
US5276825A (en) * 1991-03-12 1994-01-04 Chips & Technologies, Inc. Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction
US5394530A (en) * 1991-03-15 1995-02-28 Nec Corporation Arrangement for predicting a branch target address in the second iteration of a short loop
US5414822A (en) * 1991-04-05 1995-05-09 Kabushiki Kaisha Toshiba Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5301295A (en) * 1991-05-22 1994-04-05 Analog Devices, Inc. Data processor apparatus and method with selective caching of instructions
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5649097A (en) * 1991-10-25 1997-07-15 International Business Machines Corporation Synchronizing a prediction RAM
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
JP2761688B2 (ja) * 1992-02-07 1998-06-04 三菱電機株式会社 データ処理装置
WO1993018459A1 (en) * 1992-03-06 1993-09-16 Rambus Inc. Prefetching into a cache to minimize main memory access time and cache size in a computer system
DE69311330T2 (de) 1992-03-31 1997-09-25 Seiko Epson Corp Befehlsablauffolgeplanung von einem risc-superskalarprozessor
WO1993022722A1 (en) 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US5692167A (en) * 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
EP0586057B1 (de) * 1992-08-31 2000-03-01 Sun Microsystems, Inc. Schnelles Vorausholen und Zuteilung von Befehlen mittels vorausschauender Anmerkungen von früher vorausgeholten
US5442766A (en) * 1992-10-09 1995-08-15 International Business Machines Corporation Method and system for distributed instruction address translation in a multiscalar data processing system
JP3254019B2 (ja) * 1992-11-30 2002-02-04 富士通株式会社 データ先読み制御装置
JP3531166B2 (ja) 1992-12-31 2004-05-24 セイコーエプソン株式会社 レジスタ・リネーミングのシステム及び方法
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5421020A (en) * 1993-01-08 1995-05-30 International Business Machines Corporation Counter register implementation for speculative execution of branch on count instructions
US5737561A (en) * 1993-01-22 1998-04-07 Intel Corporation Method and apparatus for executing an instruction with multiple brancing options in one cycle
US5717908A (en) * 1993-02-25 1998-02-10 Intel Corporation Pattern recognition system using a four address arithmetic logic unit
US5825921A (en) * 1993-03-19 1998-10-20 Intel Corporation Memory transfer apparatus and method useful within a pattern recognition system
KR100310581B1 (ko) * 1993-05-14 2001-12-17 피터 엔. 데트킨 분기목표버퍼의추측기록메카니즘
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
AU6701794A (en) * 1993-05-14 1994-12-12 Intel Corporation Speculative history mechanism in a branch target buffer
US5463748A (en) 1993-06-30 1995-10-31 Intel Corporation Instruction buffer for aligning instruction sets using boundary detection
JP2596712B2 (ja) * 1993-07-01 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション 近接した分岐命令を含む命令の実行を管理するシステム及び方法
US5454117A (en) * 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
JP3417984B2 (ja) * 1993-09-10 2003-06-16 株式会社日立製作所 キャッシュ競合削減コンパイル方法
US5918046A (en) * 1994-01-03 1999-06-29 Intel Corporation Method and apparatus for a branch instruction pointer table
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
US5659722A (en) * 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
US5592634A (en) * 1994-05-16 1997-01-07 Motorola Inc. Zero-cycle multi-state branch cache prediction data processing system and method thereof
US5777614A (en) * 1994-10-14 1998-07-07 Hitachi, Ltd. Editing support system including an interactive interface
US5742784A (en) * 1995-01-25 1998-04-21 International Business Machines Corporation System for reordering of instructions before placement into cache to reduce dispatch latency
US5574937A (en) * 1995-01-30 1996-11-12 Intel Corporation Method and apparatus for improving instruction tracing operations in a computer system
US5790845A (en) * 1995-02-24 1998-08-04 Hitachi, Ltd. System with reservation instruction execution to store branch target address for use upon reaching the branch point
US5680598A (en) * 1995-03-31 1997-10-21 International Business Machines Corporation Millicode extended memory addressing using operand access control register to control extended address concatenation
US6185674B1 (en) * 1995-04-05 2001-02-06 International Business Machines Corporation Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor
US5764946A (en) * 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5848433A (en) * 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5754825A (en) * 1995-05-19 1998-05-19 Compaq Computer Corporation Lower address line prediction and substitution
US6237074B1 (en) * 1995-05-26 2001-05-22 National Semiconductor Corp. Tagged prefetch and instruction decoder for variable length instruction set and method of operation
US5878255A (en) * 1995-06-07 1999-03-02 Advanced Micro Devices, Inc. Update unit for providing a delayed update to a branch prediction array
US5875324A (en) * 1995-06-07 1999-02-23 Advanced Micro Devices, Inc. Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
US5819079A (en) * 1995-09-11 1998-10-06 Intel Corporation Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch
GB9521978D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Computer instruction supply
US5898877A (en) * 1996-02-29 1999-04-27 Sanyo Electric Co., Ltd. Processor using special instruction set to enhance exception handling
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
AU3666697A (en) * 1996-08-20 1998-03-06 Idea Corporation A method for identifying hard-to-predict branches to enhance processor performance
US5805876A (en) * 1996-09-30 1998-09-08 International Business Machines Corporation Method and system for reducing average branch resolution time and effective misprediction penalty in a processor
US6631454B1 (en) 1996-11-13 2003-10-07 Intel Corporation Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies
US5966544A (en) * 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6253316B1 (en) 1996-11-19 2001-06-26 Advanced Micro Devices, Inc. Three state branch history using one bit in a branch prediction mechanism
US5954816A (en) * 1996-11-19 1999-09-21 Advanced Micro Devices, Inc. Branch selector prediction
US5978906A (en) * 1996-11-19 1999-11-02 Advanced Micro Devices, Inc. Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
US5995749A (en) 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US6073230A (en) * 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US5964869A (en) * 1997-06-19 1999-10-12 Sun Microsystems, Inc. Instruction fetch mechanism with simultaneous prediction of control-flow instructions
US5935238A (en) * 1997-06-19 1999-08-10 Sun Microsystems, Inc. Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
US5974542A (en) * 1997-10-30 1999-10-26 Advanced Micro Devices, Inc. Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
US6256728B1 (en) 1997-11-17 2001-07-03 Advanced Micro Devices, Inc. Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction
US6219784B1 (en) 1997-11-17 2001-04-17 Advanced Micro Devices, Inc. Processor with N adders for parallel target addresses calculation
US6047351A (en) * 1997-12-12 2000-04-04 Scenix Semiconductor, Inc. Jitter free instruction execution
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6016533A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
US6016545A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
US6463522B1 (en) * 1997-12-16 2002-10-08 Intel Corporation Memory system for ordering load and store instructions in a processor that performs multithread execution
US6240509B1 (en) 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation
US6772324B2 (en) 1997-12-17 2004-08-03 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6108774A (en) * 1997-12-19 2000-08-22 Advanced Micro Devices, Inc. Branch prediction with added selector bits to increase branch prediction capacity and flexibility with minimal added bits
US6151672A (en) * 1998-02-23 2000-11-21 Hewlett-Packard Company Methods and apparatus for reducing interference in a branch history table of a microprocessor
US6150724A (en) * 1998-03-02 2000-11-21 Motorola, Inc. Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces
US6223280B1 (en) * 1998-07-16 2001-04-24 Advanced Micro Devices, Inc. Method and circuit for preloading prediction circuits in microprocessors
US6243805B1 (en) * 1998-08-11 2001-06-05 Advanced Micro Devices, Inc. Programming paradigm and microprocessor architecture for exact branch targeting
US6230260B1 (en) 1998-09-01 2001-05-08 International Business Machines Corporation Circuit arrangement and method of speculative instruction execution utilizing instruction history caching
US6223338B1 (en) 1998-09-30 2001-04-24 International Business Machines Corporation Method and system for software instruction level tracing in a data processing system
US6289442B1 (en) 1998-10-05 2001-09-11 Advanced Micro Devices, Inc. Circuit and method for tagging and invalidating speculatively executed instructions
US6332191B1 (en) 1999-01-19 2001-12-18 Advanced Micro Devices, Inc. System for canceling speculatively fetched instructions following a branch mis-prediction in a microprocessor
US6233676B1 (en) * 1999-03-18 2001-05-15 Ip-First, L.L.C. Apparatus and method for fast forward branch
US6308322B1 (en) 1999-04-06 2001-10-23 Hewlett-Packard Company Method and apparatus for reduction of indirect branch instruction overhead through use of target address hints
US6842457B1 (en) * 1999-05-21 2005-01-11 Broadcom Corporation Flexible DMA descriptor support
US6385719B1 (en) * 1999-06-30 2002-05-07 International Business Machines Corporation Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor
US6484256B1 (en) * 1999-08-09 2002-11-19 International Business Machines Corporation Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table
US6408381B1 (en) * 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6976157B1 (en) 1999-11-04 2005-12-13 International Business Machines Corporation Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables
US6633974B1 (en) 1999-11-04 2003-10-14 International Business Machines Corporation Apparatus and method for controlling link stack corruption during speculative instruction branching using multiple stacks
US6526503B1 (en) 1999-11-04 2003-02-25 International Business Machines Corporation Apparatus and method for accessing a memory device during speculative instruction branching
US6421774B1 (en) * 1999-11-05 2002-07-16 Ip First L.L.C. Static branch predictor using opcode of instruction preceding conditional branch
US6502188B1 (en) 1999-11-16 2002-12-31 Advanced Micro Devices, Inc. Dynamic classification of conditional branches in global history branch prediction
US6823446B1 (en) 2000-04-13 2004-11-23 International Business Machines Corporation Apparatus and method for performing branch predictions using dual branch history tables and for updating such branch history tables
US6910124B1 (en) 2000-05-02 2005-06-21 International Business Machines Corporation Apparatus and method for recovering a link stack from mis-speculation
US6745323B1 (en) 2000-08-03 2004-06-01 International Business Machines Corporation Global history vector recovery circuits and methods and systems using the same
US7000096B1 (en) 2000-08-03 2006-02-14 International Business Machines Corporation Branch prediction circuits and methods and systems using the same
US7051193B2 (en) * 2001-03-28 2006-05-23 Intel Corporation Register rotation prediction and precomputation
US6886093B2 (en) * 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US7165168B2 (en) * 2003-01-14 2007-01-16 Ip-First, Llc Microprocessor with branch target address cache update queue
US6895498B2 (en) * 2001-05-04 2005-05-17 Ip-First, Llc Apparatus and method for target address replacement in speculative branch target address cache
US20020194461A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Speculative branch target address cache
US7165169B2 (en) * 2001-05-04 2007-01-16 Ip-First, Llc Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
US20020194462A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line
US7707397B2 (en) * 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US7234045B2 (en) * 2001-07-03 2007-06-19 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7203824B2 (en) * 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US6823444B1 (en) * 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
US6687794B2 (en) * 2001-10-18 2004-02-03 International Business Machines Corporation Prefetching mechanism for data caches
US6948053B2 (en) * 2002-02-25 2005-09-20 International Business Machines Corporation Efficiently calculating a branch target address
US7159097B2 (en) * 2002-04-26 2007-01-02 Ip-First, Llc Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
JP3851235B2 (ja) * 2002-06-28 2006-11-29 富士通株式会社 分岐予測装置および分岐予測方法
US20040049657A1 (en) * 2002-09-10 2004-03-11 Kling Ralph M. Extended register space apparatus and methods for processors
US7185186B2 (en) * 2003-01-14 2007-02-27 Ip-First, Llc Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
US7152154B2 (en) * 2003-01-16 2006-12-19 Ip-First, Llc. Apparatus and method for invalidation of redundant branch target address cache entries
US7143269B2 (en) * 2003-01-14 2006-11-28 Ip-First, Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
US7178010B2 (en) * 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7266676B2 (en) * 2003-03-21 2007-09-04 Analog Devices, Inc. Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050050278A1 (en) * 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20050071821A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically select instructions for selective counting
US20050071611A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for counting data accesses and instruction executions that exceed a threshold
US20050071516A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically profile applications
US7395527B2 (en) * 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US20050071816A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically count instruction execution for applications
US7373637B2 (en) 2003-09-30 2008-05-13 International Business Machines Corporation Method and apparatus for counting instruction and memory location ranges
US20050071609A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus to autonomically take an exception on specified instructions
US20050071612A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for generating interrupts upon execution of marked instructions and upon access to marked memory locations
US7937691B2 (en) * 2003-09-30 2011-05-03 International Business Machines Corporation Method and apparatus for counting execution of specific instructions and accesses to specific data locations
US20050071610A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Method and apparatus for debug support for individual instructions and memory locations
US7421681B2 (en) 2003-10-09 2008-09-02 International Business Machines Corporation Method and system for autonomic monitoring of semaphore operation in an application
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7895382B2 (en) 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7415705B2 (en) 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US7392370B2 (en) 2004-01-14 2008-06-24 International Business Machines Corporation Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics
US7526757B2 (en) * 2004-01-14 2009-04-28 International Business Machines Corporation Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program
US7290255B2 (en) * 2004-01-14 2007-10-30 International Business Machines Corporation Autonomic method and apparatus for local program code reorganization using branch count per instruction hardware
US20050155018A1 (en) * 2004-01-14 2005-07-14 International Business Machines Corporation Method and apparatus for generating interrupts based on arithmetic combinations of performance counter values
US7293164B2 (en) * 2004-01-14 2007-11-06 International Business Machines Corporation Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
US7421684B2 (en) 2004-03-22 2008-09-02 International Business Machines Corporation Method and apparatus for autonomic test case feedback using hardware assistance for data coverage
US7487334B2 (en) * 2005-02-03 2009-02-03 International Business Machines Corporation Branch encoding before instruction cache write
US7461243B2 (en) * 2005-12-22 2008-12-02 Sun Microsystems, Inc. Deferred branch history update scheme
US20080005619A1 (en) * 2006-06-29 2008-01-03 Tamarah Arons Validation of software execution paths
US7533252B2 (en) * 2006-08-31 2009-05-12 Intel Corporation Overriding a static prediction with a level-two predictor
JP2008158806A (ja) * 2006-12-22 2008-07-10 Matsushita Electric Ind Co Ltd 複数プロセッサエレメントを備えるプロセッサ用プログラム及びそのプログラムの生成方法及び生成装置
US20120311308A1 (en) * 2011-06-01 2012-12-06 Polychronis Xekalakis Branch Predictor with Jump Ahead Logic to Jump Over Portions of Program Code Lacking Branches
CN103984525B (zh) * 2013-02-08 2017-10-20 上海芯豪微电子有限公司 指令处理系统及方法
US9654483B1 (en) * 2014-12-23 2017-05-16 Amazon Technologies, Inc. Network communication rate limiter
US9569613B2 (en) * 2014-12-23 2017-02-14 Intel Corporation Techniques for enforcing control flow integrity using binary translation
US9438412B2 (en) * 2014-12-23 2016-09-06 Palo Alto Research Center Incorporated Computer-implemented system and method for multi-party data function computing using discriminative dimensionality-reducing mappings
US11086629B2 (en) * 2018-11-09 2021-08-10 Arm Limited Misprediction of predicted taken branches in a data processing apparatus
US11416397B2 (en) * 2019-10-14 2022-08-16 Intel Corporation Global persistent flush
US11809874B2 (en) 2022-02-01 2023-11-07 Apple Inc. Conditional instructions distribution and execution on pipelines having different latencies for mispredictions

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
US4853840A (en) * 1986-01-07 1989-08-01 Nec Corporation Instruction prefetching device including a circuit for checking prediction of a branch instruction before the instruction is executed
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
JPS6393042A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp デ−タ処理装置
JPS6393038A (ja) * 1986-10-07 1988-04-23 Mitsubishi Electric Corp 計算機
JPS63221427A (ja) * 1987-03-11 1988-09-14 Nec Corp 分岐予測を行う情報処理装置
JPH0715662B2 (ja) * 1987-07-14 1995-02-22 日本電気株式会社 命令の先取りを行なう情報処理装置
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
US4860199A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Hashing indexer for branch cache
US4860197A (en) * 1987-07-31 1989-08-22 Prime Computer, Inc. Branch cache system with instruction boundary determination independent of parcel boundary
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction

Also Published As

Publication number Publication date
EP0381444A3 (de) 1992-08-26
JPH02260033A (ja) 1990-10-22
US5142634A (en) 1992-08-25
ATE186132T1 (de) 1999-11-15
DE69033331D1 (de) 1999-12-02
AU631419B2 (en) 1992-11-26
AU5393790A (en) 1991-12-19
EP0381444A2 (de) 1990-08-08
EP0381444B1 (de) 1999-10-27

Similar Documents

Publication Publication Date Title
DE69033331D1 (de) Sprungvorhersage
KR100395763B1 (ko) 멀티프로세싱 마이크로프로세서에 적합한 분기 예측기
US6697932B1 (en) System and method for early resolution of low confidence branches and safe data cache accesses
KR101059335B1 (ko) 가변 길이 명령 세트 실행 모드들을 가지는 프로세서 내의 bht의 효율적 사용방법
KR100974384B1 (ko) 분기 명령들을 예측하기 위한 방법 및 장치
US4860197A (en) Branch cache system with instruction boundary determination independent of parcel boundary
SE9503951L (sv) Spekulativ historikmekanism i en grenmålsbuffert
US6263427B1 (en) Branch prediction mechanism
KR930002745B1 (ko) 가변길이 명령코우드를 일정한 단어길이만큼 공급하는 캐시장치 및 명령판독장치
US6081887A (en) System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction
US20080114964A1 (en) Apparatus and Method for Cache Maintenance
JP5734945B2 (ja) スライドウィンドウブロックベースの分岐ターゲットアドレスキャッシュ
KR20010074978A (ko) 제2 레벨 분기 예측 테이블을 이용한 분기 예측 방법 및장치
KR101081674B1 (ko) 워킹 글로벌 히스토리 레지스터를 이용하기 위한 시스템 및 방법
JP3565314B2 (ja) 分岐命令実行制御装置
EP0375364A3 (de) Datenprozessor mit Null-Ausführungszyklus für einen oder beide der Befehle: Sprung und Vergleich
US5771377A (en) System for speculatively executing instructions using multiple commit condition code storages with instructions selecting a particular storage
US5822577A (en) Context oriented branch history table
Evers et al. Understanding branches and designing branch predictors for high-performance microprocessors
KR100276138B1 (ko) 브랜치 패턴 필드를 가진 브랜치 이력 테이블을 구비한 디지탈프로세서
US6338120B1 (en) Apparatus for cache use history encoding and decoding including next lru and next mru and method therefor
US6871275B1 (en) Microprocessor having a branch predictor using speculative branch registers
JP2943772B2 (ja) 分岐予測方式
KR900010552A (ko) 명령을 페치(fetch)하기 위한 제어 시스템
JP4533432B2 (ja) Tlb相関型分岐予測器及びその使用方法

Legal Events

Date Code Title Description
8364 No opposition during term of opposition