DE69128209T2 - Löschschaltung und -verfahren für EEPROM-Speichermatrizen - Google Patents

Löschschaltung und -verfahren für EEPROM-Speichermatrizen

Info

Publication number
DE69128209T2
DE69128209T2 DE69128209T DE69128209T DE69128209T2 DE 69128209 T2 DE69128209 T2 DE 69128209T2 DE 69128209 T DE69128209 T DE 69128209T DE 69128209 T DE69128209 T DE 69128209T DE 69128209 T2 DE69128209 T2 DE 69128209T2
Authority
DE
Germany
Prior art keywords
memory arrays
eeprom memory
erase circuit
erase
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69128209T
Other languages
English (en)
Other versions
DE69128209D1 (de
Inventor
Giovani Santin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69128209D1 publication Critical patent/DE69128209D1/de
Application granted granted Critical
Publication of DE69128209T2 publication Critical patent/DE69128209T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
DE69128209T 1990-04-16 1991-03-28 Löschschaltung und -verfahren für EEPROM-Speichermatrizen Expired - Lifetime DE69128209T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/509,432 US5122985A (en) 1990-04-16 1990-04-16 Circuit and method for erasing eeprom memory arrays to prevent over-erased cells

Publications (2)

Publication Number Publication Date
DE69128209D1 DE69128209D1 (de) 1998-01-02
DE69128209T2 true DE69128209T2 (de) 1998-05-14

Family

ID=24026614

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128209T Expired - Lifetime DE69128209T2 (de) 1990-04-16 1991-03-28 Löschschaltung und -verfahren für EEPROM-Speichermatrizen

Country Status (5)

Country Link
US (2) US5122985A (de)
EP (1) EP0452724B1 (de)
JP (1) JP3267309B2 (de)
KR (1) KR100274442B1 (de)
DE (1) DE69128209T2 (de)

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Also Published As

Publication number Publication date
JPH0793983A (ja) 1995-04-07
EP0452724B1 (de) 1997-11-19
EP0452724A3 (en) 1992-12-23
USRE36210E (en) 1999-05-11
DE69128209D1 (de) 1998-01-02
KR910019061A (ko) 1991-11-30
KR100274442B1 (ko) 2001-01-15
US5122985A (en) 1992-06-16
EP0452724A2 (de) 1991-10-23
JP3267309B2 (ja) 2002-03-18

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