DE69129767D1 - Vielfachsegmentbus und Betriebsverfahren - Google Patents

Vielfachsegmentbus und Betriebsverfahren

Info

Publication number
DE69129767D1
DE69129767D1 DE69129767T DE69129767T DE69129767D1 DE 69129767 D1 DE69129767 D1 DE 69129767D1 DE 69129767 T DE69129767 T DE 69129767T DE 69129767 T DE69129767 T DE 69129767T DE 69129767 D1 DE69129767 D1 DE 69129767D1
Authority
DE
Germany
Prior art keywords
operating procedures
segment bus
segment
bus
procedures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69129767T
Other languages
English (en)
Other versions
DE69129767T2 (de
Inventor
Richard H Bruce
Jean Gastinel
William F Gunning
Michael Overton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Publication of DE69129767D1 publication Critical patent/DE69129767D1/de
Application granted granted Critical
Publication of DE69129767T2 publication Critical patent/DE69129767T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/409Mechanical coupling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
DE69129767T 1990-03-06 1991-03-06 Vielfachsegmentbus und Betriebsverfahren Expired - Lifetime DE69129767T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US49011390A 1990-03-06 1990-03-06

Publications (2)

Publication Number Publication Date
DE69129767D1 true DE69129767D1 (de) 1998-08-20
DE69129767T2 DE69129767T2 (de) 1999-02-04

Family

ID=23946685

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129767T Expired - Lifetime DE69129767T2 (de) 1990-03-06 1991-03-06 Vielfachsegmentbus und Betriebsverfahren

Country Status (4)

Country Link
US (3) US5685004A (de)
EP (1) EP0446039B1 (de)
JP (1) JP3118266B2 (de)
DE (1) DE69129767T2 (de)

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AU685615B2 (en) * 1994-03-21 1998-01-22 Intel Corporation Method and apparatus for integrated circuit voltage regulation
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US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6493407B1 (en) * 1997-05-27 2002-12-10 Fusion Micromedia Corporation Synchronous latching bus arrangement for interfacing discrete and/or integrated modules in a digital system and associated method
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US9436631B2 (en) * 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9411532B2 (en) 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US6882082B2 (en) * 2001-03-13 2005-04-19 Micron Technology, Inc. Memory repeater
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US6640331B2 (en) * 2001-11-29 2003-10-28 Sun Microsystems, Inc. Decoupling capacitor assignment technique with respect to leakage power
WO2004088502A2 (de) * 2003-04-04 2004-10-14 Pact Xpp Technologies Ag Verfahren und vorrichtung für die datenverarbeitung
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
JP4388895B2 (ja) 2002-09-06 2009-12-24 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト リコンフィギュアラブルなシーケンサ構造
US6996652B1 (en) * 2002-09-19 2006-02-07 Inapac Technology, Inc. High-speed segmented data bus architecture
CN1732435A (zh) * 2002-12-30 2006-02-08 皇家飞利浦电子股份有限公司 群集的ilp处理器
KR100631673B1 (ko) * 2003-12-30 2006-10-09 엘지전자 주식회사 이동통신용 고주파 모듈 구조
JP2006245336A (ja) * 2005-03-03 2006-09-14 Koito Mfg Co Ltd 発光装置
US20070015464A1 (en) * 2005-07-12 2007-01-18 Mark Disalvo Interactive venue system
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US5119483A (en) * 1988-07-20 1992-06-02 Digital Equipment Corporation Application of state silos for recovery from memory management exceptions
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
US5050066A (en) * 1988-10-14 1991-09-17 Intel Corporation Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
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US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
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Also Published As

Publication number Publication date
EP0446039B1 (de) 1998-07-15
US5685004A (en) 1997-11-04
EP0446039A3 (en) 1991-12-27
JP3118266B2 (ja) 2000-12-18
US5632029A (en) 1997-05-20
DE69129767T2 (de) 1999-02-04
US5978880A (en) 1999-11-02
EP0446039A2 (de) 1991-09-11
JPH06266659A (ja) 1994-09-22

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