DE69130086T2 - Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien - Google Patents

Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien

Info

Publication number
DE69130086T2
DE69130086T2 DE69130086T DE69130086T DE69130086T2 DE 69130086 T2 DE69130086 T2 DE 69130086T2 DE 69130086 T DE69130086 T DE 69130086T DE 69130086 T DE69130086 T DE 69130086T DE 69130086 T2 DE69130086 T2 DE 69130086T2
Authority
DE
Germany
Prior art keywords
level cache
cache controller
data
level
caches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130086T
Other languages
English (en)
Other versions
DE69130086D1 (de
Inventor
Roger E Tipley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69130086D1 publication Critical patent/DE69130086D1/de
Publication of DE69130086T2 publication Critical patent/DE69130086T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE69130086T 1990-06-15 1991-06-14 Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien Expired - Fee Related DE69130086T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53889490A 1990-06-15 1990-06-15

Publications (2)

Publication Number Publication Date
DE69130086D1 DE69130086D1 (de) 1998-10-08
DE69130086T2 true DE69130086T2 (de) 1999-01-21

Family

ID=24148867

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130086T Expired - Fee Related DE69130086T2 (de) 1990-06-15 1991-06-14 Mehrstufeneinschluss in mehrstufigen Cache-Speicherhierarchien

Country Status (6)

Country Link
US (1) US5369753A (de)
EP (1) EP0461926B1 (de)
JP (1) JPH04233048A (de)
AT (1) ATE170642T1 (de)
CA (1) CA2044689A1 (de)
DE (1) DE69130086T2 (de)

Families Citing this family (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146473A (en) 1989-08-14 1992-09-08 International Mobile Machines Corporation Subscriber unit for wireless digital subscriber communication system
EP0549219B1 (de) * 1991-12-24 1998-06-10 Motorola, Inc. Cachesteuerungsschaltung
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
US5524212A (en) * 1992-04-27 1996-06-04 University Of Washington Multiprocessor system with write generate method for updating cache
JPH05324468A (ja) * 1992-05-21 1993-12-07 Fujitsu Ltd 階層化キャッシュメモリ
JPH06110781A (ja) * 1992-09-30 1994-04-22 Nec Corp キャッシュメモリ装置
JP2541771B2 (ja) * 1993-01-29 1996-10-09 インターナショナル・ビジネス・マシーンズ・コーポレイション 原子的メモリ参照方法及びシステム
EP0622738B1 (de) * 1993-04-30 1998-08-05 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren zur Ausführung von an einen mehrstufigen Cachespeicher einer Datenverarbeitungsanlage gerichteten Anforderungen und entsprechend gestalteter Cachespeicher
US5640531A (en) * 1993-06-22 1997-06-17 Unisys Corporation Enhanced computer operational system using auxiliary mini-cache for enhancement to general cache
US5544342A (en) * 1993-06-30 1996-08-06 International Business Machines Corporation System and method for prefetching information in a processing system
US5586270A (en) * 1993-09-30 1996-12-17 Intel Corporation Method and apparatus for upgrading a central processing unit and existing memory structure in a computer system
US5636365A (en) * 1993-10-05 1997-06-03 Nec Corporation Hierarchical buffer memories for selectively controlling data coherence including coherence control request means
US5530832A (en) * 1993-10-14 1996-06-25 International Business Machines Corporation System and method for practicing essential inclusion in a multiprocessor and cache hierarchy
US5522057A (en) * 1993-10-25 1996-05-28 Intel Corporation Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems
US5623627A (en) * 1993-12-09 1997-04-22 Advanced Micro Devices, Inc. Computer memory architecture including a replacement cache
US5692154A (en) * 1993-12-20 1997-11-25 Compaq Computer Corporation Circuit for masking a dirty status indication provided by a cache dirty memory under certain conditions so that a cache memory controller properly controls a cache tag memory
US5832534A (en) * 1994-01-04 1998-11-03 Intel Corporation Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
US5603004A (en) * 1994-02-14 1997-02-11 Hewlett-Packard Company Method for decreasing time penalty resulting from a cache miss in a multi-level cache system
US6006299A (en) * 1994-03-01 1999-12-21 Intel Corporation Apparatus and method for caching lock conditions in a multi-processor system
US5717894A (en) * 1994-03-07 1998-02-10 Dell Usa, L.P. Method and apparatus for reducing write cycle wait states in a non-zero wait state cache system
US5588131A (en) * 1994-03-09 1996-12-24 Sun Microsystems, Inc. System and method for a snooping and snarfing cache in a multiprocessor computer system
JP2778913B2 (ja) * 1994-04-26 1998-07-23 株式会社東芝 マルチプロセッサシステム及びメモリアロケーション方法
US5548742A (en) * 1994-08-11 1996-08-20 Intel Corporation Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory
US5813031A (en) * 1994-09-21 1998-09-22 Industrial Technology Research Institute Caching tag for a large scale cache computer memory system
US5634073A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
US6006312A (en) * 1995-02-27 1999-12-21 Sun Microsystems, Inc. Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses
WO1996033462A1 (de) * 1995-04-18 1996-10-24 International Business Machines Corporation Cache-speicher
US5623632A (en) * 1995-05-17 1997-04-22 International Business Machines Corporation System and method for improving multilevel cache performance in a multiprocessing system
US5740400A (en) * 1995-06-05 1998-04-14 Advanced Micro Devices Inc. Reducing cache snooping overhead in a multilevel cache system with multiple bus masters and a shared level two cache by using an inclusion field
US5850534A (en) * 1995-06-05 1998-12-15 Advanced Micro Devices, Inc. Method and apparatus for reducing cache snooping overhead in a multilevel cache system
DE19524023B4 (de) * 1995-06-30 2004-02-05 Fujitsu Siemens Computers Gmbh Multiprozessorsystem mit einer sehr großen Anzahl von Mikroprozessoren
US5778427A (en) * 1995-07-07 1998-07-07 Sun Microsystems, Inc. Method and apparatus for selecting a way of a multi-way associative cache by storing waylets in a translation structure
US5652859A (en) * 1995-08-17 1997-07-29 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
US5740399A (en) * 1995-08-23 1998-04-14 International Business Machines Corporation Modified L1/L2 cache inclusion for aggressive prefetch
US5758119A (en) * 1995-08-23 1998-05-26 International Business Machines Corp. System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache
JP2964926B2 (ja) * 1995-08-29 1999-10-18 富士ゼロックス株式会社 データベース管理装置及び方法
US5712970A (en) * 1995-09-28 1998-01-27 Emc Corporation Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers
US5809537A (en) * 1995-12-08 1998-09-15 International Business Machines Corp. Method and system for simultaneous processing of snoop and cache operations
US6070233A (en) * 1996-01-26 2000-05-30 Unisys Corporation Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cache
US5832250A (en) * 1996-01-26 1998-11-03 Unisys Corporation Multi set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bits
US5829038A (en) * 1996-06-20 1998-10-27 Intel Corporation Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure
US5835950A (en) * 1996-07-12 1998-11-10 Samsung Electronics Co., Ltd. Self-invalidation method for reducing coherence overheads in a bus-based shared-memory multiprocessor apparatus
US5897656A (en) * 1996-09-16 1999-04-27 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US6049847A (en) * 1996-09-16 2000-04-11 Corollary, Inc. System and method for maintaining memory coherency in a computer system having multiple system buses
US5926830A (en) * 1996-10-07 1999-07-20 International Business Machines Corporation Data processing system and method for maintaining coherency between high and low level caches using inclusive states
US5809526A (en) * 1996-10-28 1998-09-15 International Business Machines Corporation Data processing system and method for selective invalidation of outdated lines in a second level memory in response to a memory request initiated by a store operation
US6202125B1 (en) 1996-11-25 2001-03-13 Intel Corporation Processor-cache protocol using simple commands to implement a range of cache configurations
US5809528A (en) * 1996-12-24 1998-09-15 International Business Machines Corporation Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
US5787478A (en) * 1997-03-05 1998-07-28 International Business Machines Corporation Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy
US5895495A (en) * 1997-03-13 1999-04-20 International Business Machines Corporation Demand-based larx-reserve protocol for SMP system buses
US5943684A (en) * 1997-04-14 1999-08-24 International Business Machines Corporation Method and system of providing a cache-coherency protocol for maintaining cache coherency within a multiprocessor data-processing system
US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US6105112A (en) * 1997-04-14 2000-08-15 International Business Machines Corporation Dynamic folding of cache operations for multiple coherency-size systems
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
FR2762420B1 (fr) * 1997-04-16 1999-05-21 Thomson Multimedia Sa Methode et dispositif d'obtention d'une selection adaptative d'ensembles de donnees stockes dans une memoire de masse
US5987577A (en) * 1997-04-24 1999-11-16 International Business Machines Dual word enable method and apparatus for memory arrays
US6209072B1 (en) 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
US5923898A (en) * 1997-05-14 1999-07-13 International Business Machines Corporation System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched
US6065101A (en) * 1997-06-12 2000-05-16 International Business Machines Corporation Pipelined snooping of multiple L1 cache lines
US5996048A (en) * 1997-06-20 1999-11-30 Sun Microsystems, Inc. Inclusion vector architecture for a level two cache
US6115795A (en) 1997-08-06 2000-09-05 International Business Machines Corporation Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system
US6000015A (en) * 1997-09-16 1999-12-07 Unisys Corporation Processor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cache
US5909697A (en) * 1997-09-30 1999-06-01 Sun Microsystems, Inc. Reducing cache misses by snarfing writebacks in non-inclusive memory systems
US6073212A (en) * 1997-09-30 2000-06-06 Sun Microsystems, Inc. Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags
US6321297B1 (en) * 1998-01-05 2001-11-20 Intel Corporation Avoiding tag compares during writes in multi-level cache hierarchy
US6253291B1 (en) 1998-02-13 2001-06-26 Sun Microsystems, Inc. Method and apparatus for relaxing the FIFO ordering constraint for memory accesses in a multi-processor asynchronous cache system
US6094605A (en) * 1998-07-06 2000-07-25 Storage Technology Corporation Virtual automated cartridge system
US6405322B1 (en) 1999-04-13 2002-06-11 Hewlett-Packard Company System and method for recovery from address errors
US6510493B1 (en) 1999-07-15 2003-01-21 International Business Machines Corporation Method and apparatus for managing cache line replacement within a computer system
US6321305B1 (en) 1999-08-04 2001-11-20 International Business Machines Corporation Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data
US6343347B1 (en) 1999-08-04 2002-01-29 International Business Machines Corporation Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction
US6353875B1 (en) 1999-08-04 2002-03-05 International Business Machines Corporation Upgrading of snooper cache state mechanism for system bus with read/castout (RCO) address transactions
US6324617B1 (en) 1999-08-04 2001-11-27 International Business Machines Corporation Method and system for communicating tags of data access target and castout victim in a single data transfer
US6502171B1 (en) * 1999-08-04 2002-12-31 International Business Machines Corporation Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data
US6349367B1 (en) 1999-08-04 2002-02-19 International Business Machines Corporation Method and system for communication in which a castout operation is cancelled in response to snoop responses
US6338124B1 (en) 1999-08-04 2002-01-08 International Business Machines Corporation Multiprocessor system bus with system controller explicitly updating snooper LRU information
US6343344B1 (en) 1999-08-04 2002-01-29 International Business Machines Corporation System bus directory snooping mechanism for read/castout (RCO) address transaction
US6587923B1 (en) * 2000-05-22 2003-07-01 International Business Machines Corporation Dual line size cache directory
US6725341B1 (en) * 2000-06-28 2004-04-20 Intel Corporation Cache line pre-load and pre-own based on cache coherence speculation
US6848024B1 (en) 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6732234B1 (en) * 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
US6748492B1 (en) * 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6721856B1 (en) * 2000-10-26 2004-04-13 International Business Machines Corporation Enhanced cache management mechanism via an intelligent system bus monitor
US6629210B1 (en) 2000-10-26 2003-09-30 International Business Machines Corporation Intelligent cache management mechanism via processor access sequence analysis
US6631450B1 (en) * 2000-10-26 2003-10-07 International Business Machines Corporation Symmetric multiprocessor address bus protocol with intra-cache line access information
US6763433B1 (en) 2000-10-26 2004-07-13 International Business Machines Corporation High performance cache intervention mechanism for symmetric multiprocessor systems
US6704843B1 (en) 2000-10-26 2004-03-09 International Business Machines Corporation Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange
US6601144B1 (en) 2000-10-26 2003-07-29 International Business Machines Corporation Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis
US7231500B2 (en) 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks
US7233998B2 (en) 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US6826662B2 (en) 2001-03-22 2004-11-30 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US6526491B2 (en) 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US7093104B2 (en) 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
US6809734B2 (en) 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US6662272B2 (en) 2001-09-29 2003-12-09 Hewlett-Packard Development Company, L.P. Dynamic cache partitioning
US7114038B2 (en) * 2001-12-28 2006-09-26 Intel Corporation Method and apparatus for communicating between integrated circuits in a low power mode
US6983348B2 (en) * 2002-01-24 2006-01-03 Intel Corporation Methods and apparatus for cache intervention
US7100001B2 (en) * 2002-01-24 2006-08-29 Intel Corporation Methods and apparatus for cache intervention
US7024519B2 (en) 2002-05-06 2006-04-04 Sony Computer Entertainment Inc. Methods and apparatus for controlling hierarchical cache memory
US7266587B2 (en) * 2002-05-15 2007-09-04 Broadcom Corporation System having interfaces, switch, and memory bridge for CC-NUMA operation
US20040153611A1 (en) * 2003-02-04 2004-08-05 Sujat Jamil Methods and apparatus for detecting an address conflict
US7287126B2 (en) * 2003-07-30 2007-10-23 Intel Corporation Methods and apparatus for maintaining cache coherency
US7093075B2 (en) * 2003-11-07 2006-08-15 International Business Machines Corporation Location-based placement algorithms for set associative cache memory
US7213107B2 (en) * 2003-12-31 2007-05-01 Intel Corporation Dedicated cache memory
US7236918B2 (en) * 2003-12-31 2007-06-26 International Business Machines Corporation Method and system for selective compilation of instrumentation entities into a simulation model of a digital design
US8224639B2 (en) 2004-03-29 2012-07-17 Sony Computer Entertainment Inc. Methods and apparatus for achieving thermal management using processing task scheduling
JP4673584B2 (ja) * 2004-07-29 2011-04-20 富士通株式会社 キャッシュメモリ装置、演算処理装置及びキャッシュメモリ装置の制御方法
US7392169B2 (en) * 2004-10-21 2008-06-24 International Business Machines Corporation Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language
US20060089826A1 (en) * 2004-10-21 2006-04-27 International Business Machines Corporation Method, system and program product for defining and recording minimum and maximum count events of a simulation
US7454325B2 (en) * 2004-12-07 2008-11-18 International Business Machines Corporation Method, system and program product for defining and recording threshold-qualified count events of a simulation by testcases
US7552043B2 (en) * 2005-09-15 2009-06-23 International Business Machines Corporation Method, system and program product for selectively removing instrumentation logic from a simulation model
US7711537B2 (en) * 2006-05-03 2010-05-04 International Business Machines Corporation Signals for simulation result viewing
US7493248B2 (en) * 2006-05-08 2009-02-17 International Business Machines Corporation Method, system and program product supporting phase events in a simulation model of a digital system
US7912694B2 (en) * 2007-01-30 2011-03-22 International Business Machines Corporation Print events in the simulation of a digital system
US7917699B2 (en) * 2007-12-21 2011-03-29 Mips Technologies, Inc. Apparatus and method for controlling the exclusivity mode of a level-two cache
US7890699B2 (en) * 2008-01-10 2011-02-15 International Business Machines Corporation Processing unit incorporating L1 cache bypass
KR20100058825A (ko) * 2008-11-25 2010-06-04 삼성전자주식회사 저항체를 이용한 반도체 장치, 이를 이용한 카드 또는 시스템 및 상기 반도체 장치의 구동 방법
US8782374B2 (en) * 2008-12-02 2014-07-15 Intel Corporation Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor
US8453080B2 (en) * 2008-12-16 2013-05-28 International Business Machines Corporation Model build in the presence of a non-binding reference
JP5440067B2 (ja) * 2009-09-18 2014-03-12 富士通株式会社 キャッシュメモリ制御装置およびキャッシュメモリ制御方法
US8504774B2 (en) 2010-10-13 2013-08-06 Microsoft Corporation Dynamic cache configuration using separate read and write caches
US10102129B2 (en) * 2015-12-21 2018-10-16 Intel Corporation Minimizing snoop traffic locally and across cores on a chip multi-core fabric
US10366008B2 (en) * 2016-12-12 2019-07-30 Advanced Micro Devices, Inc. Tag and data organization in large memory caches
US10635766B2 (en) 2016-12-12 2020-04-28 International Business Machines Corporation Simulation employing level-dependent multitype events
US10417135B2 (en) * 2017-09-28 2019-09-17 Intel Corporation Near memory miss prediction to reduce memory access latency
TWI697902B (zh) 2019-01-24 2020-07-01 瑞昱半導體股份有限公司 電子裝置及電子裝置的管理方法
CN112433961B (zh) * 2020-12-02 2022-07-08 海光信息技术股份有限公司 复合缓存目录系统及其管理方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4464712A (en) * 1981-07-06 1984-08-07 International Business Machines Corporation Second level cache replacement method and apparatus
US4442487A (en) * 1981-12-31 1984-04-10 International Business Machines Corporation Three level memory hierarchy using write and share flags
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US4736293A (en) * 1984-04-11 1988-04-05 American Telephone And Telegraph Company, At&T Bell Laboratories Interleaved set-associative memory
US4823259A (en) * 1984-06-29 1989-04-18 International Business Machines Corporation High speed buffer store arrangement for quick wide transfer of data
US4985829A (en) * 1984-07-31 1991-01-15 Texas Instruments Incorporated Cache hierarchy design for use in a memory management unit
US4774654A (en) * 1984-12-24 1988-09-27 International Business Machines Corporation Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US4783736A (en) * 1985-07-22 1988-11-08 Alliant Computer Systems Corporation Digital computer with multisection cache
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5202972A (en) * 1988-12-29 1993-04-13 International Business Machines Corporation Store buffer apparatus in a multiprocessor system
US5133074A (en) * 1989-02-08 1992-07-21 Acer Incorporated Deadlock resolution with cache snooping
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates
US5136700A (en) * 1989-12-22 1992-08-04 Digital Equipment Corporation Apparatus and method for reducing interference in two-level cache memories
US5253353A (en) * 1990-01-02 1993-10-12 Digital Equipment Corporation System and method for efficiently supporting access to I/O devices through large direct-mapped data caches
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache

Also Published As

Publication number Publication date
JPH04233048A (ja) 1992-08-21
ATE170642T1 (de) 1998-09-15
US5369753A (en) 1994-11-29
CA2044689A1 (en) 1991-12-16
EP0461926A2 (de) 1991-12-18
EP0461926B1 (de) 1998-09-02
DE69130086D1 (de) 1998-10-08
EP0461926A3 (en) 1992-05-06

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