DE69132721T2 - Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle - Google Patents

Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle

Info

Publication number
DE69132721T2
DE69132721T2 DE69132721T DE69132721T DE69132721T2 DE 69132721 T2 DE69132721 T2 DE 69132721T2 DE 69132721 T DE69132721 T DE 69132721T DE 69132721 T DE69132721 T DE 69132721T DE 69132721 T2 DE69132721 T2 DE 69132721T2
Authority
DE
Germany
Prior art keywords
input
output
integrated circuit
high performance
bus interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69132721T
Other languages
English (en)
Other versions
DE69132721D1 (de
Inventor
Michael Farmwald
Mark Horowitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24032637&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69132721(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of DE69132721D1 publication Critical patent/DE69132721D1/de
Publication of DE69132721T2 publication Critical patent/DE69132721T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
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    • G06F12/0215Addressing or allocation; Relocation with look ahead addressing means
    • GPHYSICS
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    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0653Configuration or reconfiguration with centralised address assignment
    • G06F12/0661Configuration or reconfiguration with centralised address assignment and decentralised selection
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    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0684Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • GPHYSICS
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    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
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    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1678Details of memory controller using bus width
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    • G06F13/1668Details of memory controller
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    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
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    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
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    • G11INFORMATION STORAGE
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    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
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    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/88Masking faults in memories by using spares or by reconfiguring with partially good memories
    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C5/00Details of stores covered by group G11C11/00
    • GPHYSICS
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    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • GPHYSICS
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069I/O lines read out arrangements
    • GPHYSICS
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    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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    • G11INFORMATION STORAGE
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    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
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    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
    • GPHYSICS
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    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225Clock input buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
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    • G11C8/00Arrangements for selecting an address in a digital store
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
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    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/108Wide data ports
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management
DE69132721T 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle Expired - Lifetime DE69132721T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US51089890A 1990-04-18 1990-04-18

Publications (2)

Publication Number Publication Date
DE69132721D1 DE69132721D1 (de) 2001-10-11
DE69132721T2 true DE69132721T2 (de) 2002-05-29

Family

ID=24032637

Family Applications (15)

Application Number Title Priority Date Filing Date
DE69132721T Expired - Lifetime DE69132721T2 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE02000378T Pending DE02000378T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125958T Pending DE06125958T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125954T Pending DE06125954T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133565.6T Expired - Lifetime DE69133565T3 (de) 1990-04-18 1991-04-16 System mit einer Vielzahl von DRAMS und einem Bus
DE69133598T Expired - Lifetime DE69133598D1 (de) 1990-04-18 1991-04-16 Integrierte E/A-Schaltung, die eine Hochleistungsbusschnittstelle benutzt
DE69132121T Revoked DE69132121T2 (de) 1990-04-18 1991-04-16 Halbleiterspeichervorrichtung
DE1022642T Pending DE1022642T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125946T Pending DE06125946T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133572T Expired - Lifetime DE69133572T2 (de) 1990-04-18 1991-04-16 Halbleiterbauelement mit dynamischem Arbeitsspeicher (DRAM)
DE69132501T Expired - Lifetime DE69132501T3 (de) 1990-04-18 1991-04-16 Methode zum Betrieb eines synchronen Speichers mit einer variablen Länge der Ausgabedaten
DE69133611T Expired - Lifetime DE69133611D1 (de) 1990-04-18 1991-04-16 Integrierte E/A-Schaltung, die eine Hochleistungsbusschnittstelle benutzt
DE00100018T Pending DE00100018T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133550T Expired - Lifetime DE69133550T2 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133500T Expired - Lifetime DE69133500T2 (de) 1990-04-18 1991-04-16 DRAM Halbleitervorrichtung

Family Applications After (14)

Application Number Title Priority Date Filing Date
DE02000378T Pending DE02000378T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125958T Pending DE06125958T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125954T Pending DE06125954T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133565.6T Expired - Lifetime DE69133565T3 (de) 1990-04-18 1991-04-16 System mit einer Vielzahl von DRAMS und einem Bus
DE69133598T Expired - Lifetime DE69133598D1 (de) 1990-04-18 1991-04-16 Integrierte E/A-Schaltung, die eine Hochleistungsbusschnittstelle benutzt
DE69132121T Revoked DE69132121T2 (de) 1990-04-18 1991-04-16 Halbleiterspeichervorrichtung
DE1022642T Pending DE1022642T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE06125946T Pending DE06125946T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133572T Expired - Lifetime DE69133572T2 (de) 1990-04-18 1991-04-16 Halbleiterbauelement mit dynamischem Arbeitsspeicher (DRAM)
DE69132501T Expired - Lifetime DE69132501T3 (de) 1990-04-18 1991-04-16 Methode zum Betrieb eines synchronen Speichers mit einer variablen Länge der Ausgabedaten
DE69133611T Expired - Lifetime DE69133611D1 (de) 1990-04-18 1991-04-16 Integrierte E/A-Schaltung, die eine Hochleistungsbusschnittstelle benutzt
DE00100018T Pending DE00100018T1 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133550T Expired - Lifetime DE69133550T2 (de) 1990-04-18 1991-04-16 Eingang/Ausgang einer integrierten Schaltung mit einer Hochleistungsbusschnittstelle
DE69133500T Expired - Lifetime DE69133500T2 (de) 1990-04-18 1991-04-16 DRAM Halbleitervorrichtung

Country Status (7)

Country Link
US (47) US5473575A (de)
EP (7) EP1816570A3 (de)
JP (3) JP3414393B2 (de)
KR (1) KR100201057B1 (de)
DE (15) DE69132721T2 (de)
IL (4) IL96808A (de)
WO (1) WO1991016680A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7191276B2 (en) 2003-06-26 2007-03-13 Infineon Technologies Ag Hub chip for one or more memory modules
DE112004000821B4 (de) * 2003-05-13 2016-12-01 Advanced Micro Devices, Inc. System mit einem Hauptrechner, der mit mehreren Speichermodulen über eine serielle Speicherverbindung verbunden ist

Families Citing this family (741)

* Cited by examiner, † Cited by third party
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DE112004000821B4 (de) * 2003-05-13 2016-12-01 Advanced Micro Devices, Inc. System mit einem Hauptrechner, der mit mehreren Speichermodulen über eine serielle Speicherverbindung verbunden ist
US7191276B2 (en) 2003-06-26 2007-03-13 Infineon Technologies Ag Hub chip for one or more memory modules

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US5841715A (en) 1998-11-24
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US20020016876A1 (en) 2002-02-07
US6067592A (en) 2000-05-23
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US5928343A (en) 1999-07-27
US6032214A (en) 2000-02-29
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EP0525068A1 (de) 1993-02-03
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US5499385A (en) 1996-03-12
US6697295B2 (en) 2004-02-24
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US6038195A (en) 2000-03-14
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US6128696A (en) 2000-10-03
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US5638334A (en) 1997-06-10
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US5408129A (en) 1995-04-18
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US5319755A (en) 1994-06-07
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