DE69132984D1 - Programmierbare Verbindungsarchitektur - Google Patents

Programmierbare Verbindungsarchitektur

Info

Publication number
DE69132984D1
DE69132984D1 DE69132984T DE69132984T DE69132984D1 DE 69132984 D1 DE69132984 D1 DE 69132984D1 DE 69132984 T DE69132984 T DE 69132984T DE 69132984 T DE69132984 T DE 69132984T DE 69132984 D1 DE69132984 D1 DE 69132984D1
Authority
DE
Germany
Prior art keywords
interconnect
conductors
segments
functional circuit
interconnect layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132984T
Other languages
English (en)
Other versions
DE69132984T2 (de
Inventor
John L Mccollum
Gamal Abbas A El
Jonathan W Greene
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi SoC Corp
Original Assignee
Actel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Actel Corp filed Critical Actel Corp
Publication of DE69132984D1 publication Critical patent/DE69132984D1/de
Application granted granted Critical
Publication of DE69132984T2 publication Critical patent/DE69132984T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69132984T 1990-08-01 1991-07-08 Programmierbare Verbindungsarchitektur Expired - Fee Related DE69132984T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/561,110 US5132571A (en) 1990-08-01 1990-08-01 Programmable interconnect architecture having interconnects disposed above function modules

Publications (2)

Publication Number Publication Date
DE69132984D1 true DE69132984D1 (de) 2002-05-16
DE69132984T2 DE69132984T2 (de) 2003-01-23

Family

ID=24240673

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132984T Expired - Fee Related DE69132984T2 (de) 1990-08-01 1991-07-08 Programmierbare Verbindungsarchitektur

Country Status (6)

Country Link
US (1) US5132571A (de)
EP (1) EP0469728B1 (de)
JP (1) JP2761310B2 (de)
AT (1) ATE216131T1 (de)
DE (1) DE69132984T2 (de)
ES (1) ES2174821T3 (de)

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US6407576B1 (en) * 1999-03-04 2002-06-18 Altera Corporation Interconnection and input/output resources for programmable logic integrated circuit devices
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US6331733B1 (en) 1999-08-10 2001-12-18 Easic Corporation Semiconductor device
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US6194912B1 (en) 1999-03-11 2001-02-27 Easic Corporation Integrated circuit device
US6236232B1 (en) * 1999-10-15 2001-05-22 Agilent Technologies, Inc. Multi-purpose transistor array
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US6331790B1 (en) 2000-03-10 2001-12-18 Easic Corporation Customizable and programmable cell array
US6756811B2 (en) * 2000-03-10 2004-06-29 Easic Corporation Customizable and programmable cell array
US7283381B2 (en) 2000-08-17 2007-10-16 David Earl Butz System and methods for addressing a matrix incorporating virtual columns and addressing layers
US6462977B2 (en) 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
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US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6777977B1 (en) * 2002-05-01 2004-08-17 Actel Corporation Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
US6774667B1 (en) 2002-05-09 2004-08-10 Actel Corporation Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays
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US7434080B1 (en) 2002-09-03 2008-10-07 Actel Corporation Apparatus for interfacing and testing a phase locked loop in a field programmable gate array
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US6750674B1 (en) 2002-10-02 2004-06-15 Actel Corporation Carry chain for use between logic modules in a field programmable gate array
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US6885218B1 (en) 2002-10-08 2005-04-26 Actel Corporation Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
US6727726B1 (en) 2002-11-12 2004-04-27 Actel Corporation Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
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US7385420B1 (en) 2002-12-27 2008-06-10 Actel Corporation Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks
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US7375553B1 (en) 2003-05-28 2008-05-20 Actel Corporation Clock tree network in a field programmable gate array
US7385419B1 (en) 2003-05-30 2008-06-10 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
US6867615B1 (en) * 2003-05-30 2005-03-15 Actel Corporation Dedicated input/output first in/first out module for a field programmable gate array
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Also Published As

Publication number Publication date
ES2174821T3 (es) 2002-11-16
ATE216131T1 (de) 2002-04-15
EP0469728A1 (de) 1992-02-05
JP2761310B2 (ja) 1998-06-04
DE69132984T2 (de) 2003-01-23
US5132571A (en) 1992-07-21
EP0469728B1 (de) 2002-04-10
JPH08162535A (ja) 1996-06-21

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee