DE69327387D1 - An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung - Google Patents

An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung

Info

Publication number
DE69327387D1
DE69327387D1 DE69327387T DE69327387T DE69327387D1 DE 69327387 D1 DE69327387 D1 DE 69327387D1 DE 69327387 T DE69327387 T DE 69327387T DE 69327387 T DE69327387 T DE 69327387T DE 69327387 D1 DE69327387 D1 DE 69327387D1
Authority
DE
Germany
Prior art keywords
control circuit
post
packet switched
switched bus
write control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327387T
Other languages
English (en)
Other versions
DE69327387T2 (de
Inventor
Bjorn Liencres
Douglas Lee
Pradeep S Sindhu
Tung Pham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Sun Microsystems Inc
Original Assignee
Xerox Corp
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp, Sun Microsystems Inc filed Critical Xerox Corp
Application granted granted Critical
Publication of DE69327387D1 publication Critical patent/DE69327387D1/de
Publication of DE69327387T2 publication Critical patent/DE69327387T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69327387T 1992-11-09 1993-11-08 An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung Expired - Fee Related DE69327387T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/973,309 US5434993A (en) 1992-11-09 1992-11-09 Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories

Publications (2)

Publication Number Publication Date
DE69327387D1 true DE69327387D1 (de) 2000-01-27
DE69327387T2 DE69327387T2 (de) 2000-08-31

Family

ID=25520741

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327387T Expired - Fee Related DE69327387T2 (de) 1992-11-09 1993-11-08 An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung

Country Status (4)

Country Link
US (1) US5434993A (de)
EP (1) EP0598535B1 (de)
JP (1) JPH076092A (de)
DE (1) DE69327387T2 (de)

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US7360029B2 (en) * 2003-04-11 2008-04-15 Sun Microsystems, Inc. Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node
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Also Published As

Publication number Publication date
JPH076092A (ja) 1995-01-10
DE69327387T2 (de) 2000-08-31
US5434993A (en) 1995-07-18
EP0598535B1 (de) 1999-12-22
EP0598535A1 (de) 1994-05-25

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee