DE69327387T2 - An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung - Google Patents

An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung

Info

Publication number
DE69327387T2
DE69327387T2 DE69327387T DE69327387T DE69327387T2 DE 69327387 T2 DE69327387 T2 DE 69327387T2 DE 69327387 T DE69327387 T DE 69327387T DE 69327387 T DE69327387 T DE 69327387T DE 69327387 T2 DE69327387 T2 DE 69327387T2
Authority
DE
Germany
Prior art keywords
control circuit
post
packet switched
switched bus
write control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327387T
Other languages
English (en)
Other versions
DE69327387D1 (de
Inventor
Bjorn Liencres
Douglas Lee
Pradeep S Sindhu
Tung Pham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Sun Microsystems Inc
Original Assignee
Xerox Corp
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp, Sun Microsystems Inc filed Critical Xerox Corp
Publication of DE69327387D1 publication Critical patent/DE69327387D1/de
Application granted granted Critical
Publication of DE69327387T2 publication Critical patent/DE69327387T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE69327387T 1992-11-09 1993-11-08 An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung Expired - Fee Related DE69327387T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/973,309 US5434993A (en) 1992-11-09 1992-11-09 Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories

Publications (2)

Publication Number Publication Date
DE69327387D1 DE69327387D1 (de) 2000-01-27
DE69327387T2 true DE69327387T2 (de) 2000-08-31

Family

ID=25520741

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327387T Expired - Fee Related DE69327387T2 (de) 1992-11-09 1993-11-08 An einen paketvermittelten Bus gekoppelte Nachschreibsteuerungsschaltung für eine Cachespeichersteuerungsschaltung

Country Status (4)

Country Link
US (1) US5434993A (de)
EP (1) EP0598535B1 (de)
JP (1) JPH076092A (de)
DE (1) DE69327387T2 (de)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0587918B1 (de) * 1992-08-19 1999-11-03 Siemens Nixdorf Informationssysteme Aktiengesellschaft Multiprozessorsystem mit Cache-Speichern
US6088768A (en) * 1993-12-28 2000-07-11 International Business Machines Corporation Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication
US5832534A (en) * 1994-01-04 1998-11-03 Intel Corporation Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
TW243509B (en) * 1994-01-31 1995-03-21 Ibm Data processor with memory cache and method of operation
JP2778913B2 (ja) * 1994-04-26 1998-07-23 株式会社東芝 マルチプロセッサシステム及びメモリアロケーション方法
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
US5566317A (en) * 1994-06-14 1996-10-15 International Business Machines Corporation Method and apparatus for computer disk drive management
US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking
US6000017A (en) * 1995-01-20 1999-12-07 Intel Corporation Hybrid tag architecture for a cache memory
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5649157A (en) * 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
US5710891A (en) * 1995-03-31 1998-01-20 Sun Microsystems, Inc. Pipelined distributed bus arbitration system
US5907485A (en) * 1995-03-31 1999-05-25 Sun Microsystems, Inc. Method and apparatus for flow control in packet-switched computer system
US5581729A (en) * 1995-03-31 1996-12-03 Sun Microsystems, Inc. Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
US5634068A (en) * 1995-03-31 1997-05-27 Sun Microsystems, Inc. Packet switched cache coherent multiprocessor system
DE69628493T2 (de) * 1995-03-31 2004-05-19 Sun Microsystems, Inc., Santa Clara Cache-kohärentes Computersystem, das Entwertungs- und Rückschreiboperationen minimiert
US5657472A (en) * 1995-03-31 1997-08-12 Sun Microsystems, Inc. Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
DE69628079T2 (de) * 1995-03-31 2004-02-26 Sun Microsystems, Inc., Santa Clara Mechanismus auf Systemebene zum Entwerten von Daten, die im externen Cache eines Prozessors in einem Computersystem gespeichert sind
US5689713A (en) * 1995-03-31 1997-11-18 Sun Microsystems, Inc. Method and apparatus for interrupt communication in a packet-switched computer system
US5684977A (en) * 1995-03-31 1997-11-04 Sun Microsystems, Inc. Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
US5655100A (en) * 1995-03-31 1997-08-05 Sun Microsystems, Inc. Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
US5737756A (en) * 1995-04-28 1998-04-07 Unisys Corporation Dual bus computer network using dual busses with dual spy modules enabling clearing of invalidation queue for processor with store through cache while providing retry cycles for incomplete accesses to invalidation queue
US6076150A (en) * 1995-08-10 2000-06-13 Lsi Logic Corporation Cache controller with improved instruction and data forwarding during refill operation
US5887146A (en) * 1995-08-14 1999-03-23 Data General Corporation Symmetric multiprocessing computer with non-uniform memory access architecture
US6021472A (en) * 1995-08-21 2000-02-01 Canon Kabushiki Kaisha Information processing device and control method thereof
US5778208A (en) * 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
US5829035A (en) * 1995-12-22 1998-10-27 Apple Computer, Inc. System and method for preventing stale data in multiple processor computer systems
EP0976046B1 (de) * 1996-01-25 2001-05-30 Unisys Corporation Verfahren zur ausführung von lese- und schreibbefehlen in einem mehrstufigen verteilten datenverarbeitungssystem
JPH09223118A (ja) * 1996-02-14 1997-08-26 Oki Electric Ind Co Ltd スヌープキャッシュメモリ制御システム
US6385710B1 (en) 1996-02-23 2002-05-07 Sun Microsystems, Inc. Multiple-mode external cache subsystem
US5765196A (en) * 1996-02-27 1998-06-09 Sun Microsystems, Inc. System and method for servicing copyback requests in a multiprocessor system with a shared memory
US5829033A (en) * 1996-07-01 1998-10-27 Sun Microsystems, Inc. Optimizing responses in a coherent distributed electronic system including a computer system
US5911052A (en) * 1996-07-01 1999-06-08 Sun Microsystems, Inc. Split transaction snooping bus protocol
US5860117A (en) * 1996-05-31 1999-01-12 Sun Microsystems, Inc. Apparatus and method to improve primary memory latencies using an eviction buffer to store write requests
US5893165A (en) * 1996-07-01 1999-04-06 Sun Microsystems, Inc. System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO
JPH1078934A (ja) * 1996-07-01 1998-03-24 Sun Microsyst Inc パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
US5809548A (en) * 1996-08-30 1998-09-15 International Business Machines Corporation System and method for zeroing pages with cache line invalidate instructions in an LRU system having data cache with time tags
US6202125B1 (en) 1996-11-25 2001-03-13 Intel Corporation Processor-cache protocol using simple commands to implement a range of cache configurations
US5829029A (en) * 1996-12-18 1998-10-27 Bull Hn Information Systems Inc. Private cache miss and access management in a multiprocessor system with shared memory
US6122711A (en) * 1997-01-07 2000-09-19 Unisys Corporation Method of and apparatus for store-in second level cache flush
US6061755A (en) * 1997-04-14 2000-05-09 International Business Machines Corporation Method of layering cache and architectural specific functions to promote operation symmetry
US6032226A (en) * 1997-04-14 2000-02-29 International Business Machines Corporation Method and apparatus for layering cache and architectural specific functions to expedite multiple design
US6209072B1 (en) 1997-05-06 2001-03-27 Intel Corporation Source synchronous interface between master and slave using a deskew latch
US6434639B1 (en) * 1998-11-13 2002-08-13 Intel Corporation System for combining requests associated with one or more memory locations that are collectively associated with a single cache line to furnish a single memory operation
US6859399B1 (en) 2000-05-17 2005-02-22 Marvell International, Ltd. Memory architecture and system and multiport interface protocol
US7472230B2 (en) * 2001-09-14 2008-12-30 Hewlett-Packard Development Company, L.P. Preemptive write back controller
US6785779B2 (en) * 2002-01-09 2004-08-31 International Business Machines Company Multi-level classification method for transaction address conflicts for ensuring efficient ordering in a two-level snoopy cache architecture
US20050005075A1 (en) * 2003-04-11 2005-01-06 Sun Microsystems, Inc. Multi-node computer system employing multiple memory response states
US20050010615A1 (en) * 2003-04-11 2005-01-13 Sun Microsystems, Inc. Multi-node computer system implementing memory-correctable speculative proxy transactions
WO2004092958A2 (en) * 2003-04-11 2004-10-28 Sun Microsystems, Inc. Multi-node computer system with proxy transaction to read data from a non-owning memory device
US20050013294A1 (en) * 2003-04-11 2005-01-20 Sun Microsystems, Inc. Multi-node computer system with active devices employing promise arrays for outstanding transactions
US7945738B2 (en) * 2003-04-11 2011-05-17 Oracle America, Inc. Multi-node computer system employing a reporting mechanism for multi-node transactions
WO2004093408A2 (en) * 2003-04-11 2004-10-28 Sun Microsystems, Inc. Multi-node computer system implementing global access state dependent transactions
US7814278B2 (en) * 2003-04-11 2010-10-12 Oracle America, Inc. Multi-node system with response information in memory
US7360029B2 (en) * 2003-04-11 2008-04-15 Sun Microsystems, Inc. Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node
US8559443B2 (en) 2005-07-22 2013-10-15 Marvell International Ltd. Efficient message switching in a switching apparatus
DE112013004094B4 (de) * 2012-10-22 2018-03-29 Intel Corporation Hochleistungs-Zusammenschaltungs-Bitübertragungsschicht

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5247648A (en) * 1990-04-12 1993-09-21 Sun Microsystems, Inc. Maintaining data coherency between a central cache, an I/O cache and a memory
EP0468831B1 (de) * 1990-06-29 1997-10-15 Digital Equipment Corporation Busprotokoll für Prozessor mit write-back cache
US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5265235A (en) * 1990-11-30 1993-11-23 Xerox Corporation Consistency protocols for shared memory multiprocessors
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5265233A (en) * 1991-05-17 1993-11-23 Sun Microsystems, Inc. Method and apparatus for providing total and partial store ordering for a memory in multi-processor system
US5313609A (en) * 1991-05-23 1994-05-17 International Business Machines Corporation Optimum write-back strategy for directory-based cache coherence protocols
US5325504A (en) * 1991-08-30 1994-06-28 Compaq Computer Corporation Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort

Also Published As

Publication number Publication date
US5434993A (en) 1995-07-18
DE69327387D1 (de) 2000-01-27
EP0598535A1 (de) 1994-05-25
EP0598535B1 (de) 1999-12-22
JPH076092A (ja) 1995-01-10

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8339 Ceased/non-payment of the annual fee