DE69414764D1 - Verfahren zum Steuern der Dicke des Gate-Oxyds für die Herstellung von Halbleiterbauelementen - Google Patents
Verfahren zum Steuern der Dicke des Gate-Oxyds für die Herstellung von HalbleiterbauelementenInfo
- Publication number
- DE69414764D1 DE69414764D1 DE69414764T DE69414764T DE69414764D1 DE 69414764 D1 DE69414764 D1 DE 69414764D1 DE 69414764 T DE69414764 T DE 69414764T DE 69414764 T DE69414764 T DE 69414764T DE 69414764 D1 DE69414764 D1 DE 69414764D1
- Authority
- DE
- Germany
- Prior art keywords
- thickness
- controlling
- production
- semiconductor devices
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/118—Oxide films
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/163—Thick-thin oxides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/077,570 US5330920A (en) | 1993-06-15 | 1993-06-15 | Method of controlling gate oxide thickness in the fabrication of semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69414764D1 true DE69414764D1 (de) | 1999-01-07 |
DE69414764T2 DE69414764T2 (de) | 1999-06-10 |
Family
ID=22138850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69414764T Expired - Fee Related DE69414764T2 (de) | 1993-06-15 | 1994-06-07 | Verfahren zum Steuern der Dicke des Gate-Oxyds für die Herstellung von Halbleiterbauelementen |
Country Status (3)
Country | Link |
---|---|
US (1) | US5330920A (de) |
EP (1) | EP0631308B1 (de) |
DE (1) | DE69414764T2 (de) |
Families Citing this family (75)
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US6081449A (en) * | 1987-05-12 | 2000-06-27 | Altera Corporation | High-density nonvolatile memory cell |
US5532177A (en) * | 1993-07-07 | 1996-07-02 | Micron Display Technology | Method for forming electron emitters |
US5596218A (en) * | 1993-10-18 | 1997-01-21 | Digital Equipment Corporation | Hot carrier-hard gate oxides by nitrogen implantation before gate oxidation |
KR0136935B1 (ko) * | 1994-04-21 | 1998-04-24 | 문정환 | 메모리 소자의 제조방법 |
US5498577A (en) * | 1994-07-26 | 1996-03-12 | Advanced Micro Devices, Inc. | Method for fabricating thin oxides for a semiconductor technology |
US5480828A (en) * | 1994-09-30 | 1996-01-02 | Taiwan Semiconductor Manufacturing Corp. Ltd. | Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process |
TW344897B (en) * | 1994-11-30 | 1998-11-11 | At&T Tcorporation | A process for forming gate oxides possessing different thicknesses on a semiconductor substrate |
US5672521A (en) * | 1995-11-21 | 1997-09-30 | Advanced Micro Devices, Inc. | Method of forming multiple gate oxide thicknesses on a wafer substrate |
US5937310A (en) * | 1996-04-29 | 1999-08-10 | Advanced Micro Devices, Inc. | Reduced bird's beak field oxidation process using nitrogen implanted into active region |
TW328147B (en) * | 1996-05-07 | 1998-03-11 | Lucent Technologies Inc | Semiconductor device fabrication |
US5998263A (en) * | 1996-05-16 | 1999-12-07 | Altera Corporation | High-density nonvolatile memory cell |
JPH1070197A (ja) * | 1996-07-12 | 1998-03-10 | Texas Instr Inc <Ti> | スプリット・ゲート酸化物を備えた高集積度cmos回路及びその作成法 |
US5942780A (en) * | 1996-08-09 | 1999-08-24 | Advanced Micro Devices, Inc. | Integrated circuit having, and process providing, different oxide layer thicknesses on a substrate |
US5882993A (en) * | 1996-08-19 | 1999-03-16 | Advanced Micro Devices, Inc. | Integrated circuit with differing gate oxide thickness and process for making same |
US6033943A (en) * | 1996-08-23 | 2000-03-07 | Advanced Micro Devices, Inc. | Dual gate oxide thickness integrated circuit and process for making same |
US5970350A (en) * | 1996-12-05 | 1999-10-19 | Advanced Micro Devices | Semiconductor device having a thin gate oxide and method of manufacture thereof |
GB2327810B (en) * | 1997-02-07 | 1999-06-09 | United Microelectronics Corp | Manufacturing integrated circuit devices with different gate oxide thicknesses |
US5872376A (en) * | 1997-03-06 | 1999-02-16 | Advanced Micro Devices, Inc. | Oxide formation technique using thin film silicon deposition |
US6051510A (en) * | 1997-05-02 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of using a hard mask to grow dielectrics with varying characteristics |
US6037224A (en) * | 1997-05-02 | 2000-03-14 | Advanced Micro Devices, Inc. | Method for growing dual oxide thickness using nitrided oxides for oxidation suppression |
US6110783A (en) * | 1997-06-27 | 2000-08-29 | Sun Microsystems, Inc. | Method for forming a notched gate oxide asymmetric MOS device |
US5866445A (en) * | 1997-07-11 | 1999-02-02 | Texas Instruments Incorporated | High density CMOS circuit with split gate oxide |
NL1006803C2 (nl) * | 1997-08-20 | 1999-02-23 | United Microelectronics Corp | Differentiële gate-oxidedikte door stikstofimplantatie voor gemengde- modus- en ingebedde vlsi-schakelingen. |
US6054374A (en) * | 1997-11-26 | 2000-04-25 | Advanced Micro Devices | Method of scaling dielectric thickness in a semiconductor process with ion implantation |
US5963839A (en) * | 1997-12-08 | 1999-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of polysilicon contact resistance by nitrogen implantation |
US6080682A (en) * | 1997-12-18 | 2000-06-27 | Advanced Micro Devices, Inc. | Methodology for achieving dual gate oxide thicknesses |
US5918133A (en) * | 1997-12-18 | 1999-06-29 | Advanced Micro Devices | Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof |
KR100252856B1 (ko) * | 1997-12-26 | 2000-04-15 | 김영환 | 반도체 소자의 제조 방법 |
KR19990060472A (ko) | 1997-12-31 | 1999-07-26 | 구본준 | 반도체소자의 산화막 형성방법 |
US5962914A (en) * | 1998-01-14 | 1999-10-05 | Advanced Micro Devices, Inc. | Reduced bird's beak field oxidation process using nitrogen implanted into active region |
KR100272528B1 (ko) * | 1998-02-04 | 2000-12-01 | 김영환 | 반도체소자 및 이의 제조방법 |
KR100258882B1 (ko) * | 1998-02-27 | 2000-06-15 | 김영환 | 반도체 소자의 제조 방법 |
US6077749A (en) * | 1998-03-03 | 2000-06-20 | Advanced Micro Devices, Inc. | Method of making dual channel gate oxide thickness for MOSFET transistor design |
US6093659A (en) * | 1998-03-25 | 2000-07-25 | Texas Instruments Incorporated | Selective area halogen doping to achieve dual gate oxide thickness on a wafer |
US6124620A (en) * | 1998-05-14 | 2000-09-26 | Advanced Micro Devices, Inc. | Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation |
JP2000003965A (ja) * | 1998-06-15 | 2000-01-07 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6531364B1 (en) | 1998-08-05 | 2003-03-11 | Advanced Micro Devices, Inc. | Advanced fabrication technique to form ultra thin gate dielectric using a sacrificial polysilicon seed layer |
US6784115B1 (en) | 1998-12-18 | 2004-08-31 | Mosel Vitelic, Inc. | Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities |
US6335262B1 (en) | 1999-01-14 | 2002-01-01 | International Business Machines Corporation | Method for fabricating different gate oxide thicknesses within the same chip |
EP1035567A3 (de) * | 1999-03-12 | 2001-01-24 | Lucent Technologies Inc. | Verfahren zur Herstellung von einem Bauelement mit flachen Übergängen |
JP2000269361A (ja) * | 1999-03-15 | 2000-09-29 | Nec Corp | 不揮発性半導体記憶装置およびその製造方法 |
US6165918A (en) * | 1999-05-06 | 2000-12-26 | Integrated Device Technology, Inc. | Method for forming gate oxides of different thicknesses |
US6147008A (en) * | 1999-11-19 | 2000-11-14 | Chartered Semiconductor Manufacturing Ltd. | Creation of multiple gate oxide with high thickness ratio in flash memory process |
US6399448B1 (en) | 1999-11-19 | 2002-06-04 | Chartered Semiconductor Manufacturing Ltd. | Method for forming dual gate oxide |
US6150670A (en) * | 1999-11-30 | 2000-11-21 | International Business Machines Corporation | Process for fabricating a uniform gate oxide of a vertical transistor |
US6174787B1 (en) * | 1999-12-30 | 2001-01-16 | White Oak Semiconductor Partnership | Silicon corner rounding by ion implantation for shallow trench isolation |
US6583011B1 (en) | 2000-01-11 | 2003-06-24 | Chartered Semiconductor Manufacturing Ltd. | Method for forming damascene dual gate for improved oxide uniformity and control |
US6724053B1 (en) | 2000-02-23 | 2004-04-20 | International Business Machines Corporation | PMOSFET device with localized nitrogen sidewall implantation |
US6225167B1 (en) * | 2000-03-13 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method of generating multiple oxide thicknesses by one oxidation step using NH3 nitridation followed by re-oxidation |
DE10021095A1 (de) * | 2000-04-20 | 2001-10-31 | Infineon Technologies Ag | Verfahren zum Bilden eines Dielektrikums auf einem Halbleitersubstrat |
DE10029286C2 (de) | 2000-06-14 | 2003-10-02 | Infineon Technologies Ag | Verfahren zur Überwachung von Stickstoffprozessen |
US6686298B1 (en) * | 2000-06-22 | 2004-02-03 | Micron Technology, Inc. | Methods of forming structures over semiconductor substrates, and methods of forming transistors associated with semiconductor substrates |
US6649543B1 (en) | 2000-06-22 | 2003-11-18 | Micron Technology, Inc. | Methods of forming silicon nitride, methods of forming transistor devices, and transistor devices |
US6833329B1 (en) * | 2000-06-22 | 2004-12-21 | Micron Technology, Inc. | Methods of forming oxide regions over semiconductor substrates |
KR100326317B1 (ko) * | 2000-07-06 | 2002-03-08 | 윤종용 | 실리카 미세 구조물의 제작 방법 |
US6660657B1 (en) | 2000-08-07 | 2003-12-09 | Micron Technology, Inc. | Methods of incorporating nitrogen into silicon-oxide-containing layers |
US6521469B1 (en) | 2000-09-25 | 2003-02-18 | International Business Machines Corporation | Line monitoring of negative bias temperature instabilities by hole injection methods |
US6261972B1 (en) * | 2000-11-06 | 2001-07-17 | Infineon Technologies Ag | Dual gate oxide process for uniform oxide thickness |
US6967147B1 (en) | 2000-11-16 | 2005-11-22 | Infineon Technologies Ag | Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor |
US6521549B1 (en) * | 2000-11-28 | 2003-02-18 | Lsi Logic Corporation | Method of reducing silicon oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit |
US6660593B2 (en) * | 2000-12-21 | 2003-12-09 | Winbond Electronics Corp. | Method for fabricating oxide layers with different thicknesses |
US6531731B2 (en) * | 2001-06-15 | 2003-03-11 | Motorola, Inc. | Integration of two memory types on the same integrated circuit |
SE522714C2 (sv) | 2001-07-13 | 2004-03-02 | Ericsson Telefon Ab L M | Framställning av lågbrusig MOS-anordning |
US6878585B2 (en) | 2001-08-29 | 2005-04-12 | Micron Technology, Inc. | Methods of forming capacitors |
US6723599B2 (en) * | 2001-12-03 | 2004-04-20 | Micron Technology, Inc. | Methods of forming capacitors and methods of forming capacitor dielectric layers |
US6569781B1 (en) * | 2002-01-22 | 2003-05-27 | International Business Machines Corporation | Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation |
DE10206374A1 (de) * | 2002-02-15 | 2003-09-04 | Infineon Technologies Ag | Verfahren zur Herstellung planarer NROM-Zellen |
US7026217B1 (en) * | 2003-10-29 | 2006-04-11 | Lsi Logic Corporation | Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate |
US20050191807A1 (en) * | 2004-02-26 | 2005-09-01 | Nanya Technology Corporation | Method for forming shallow trench in deep trench structure |
US7755162B2 (en) | 2004-05-06 | 2010-07-13 | Sidense Corp. | Anti-fuse memory cell |
US8735297B2 (en) | 2004-05-06 | 2014-05-27 | Sidense Corporation | Reverse optical proximity correction method |
EP1743380B1 (de) * | 2004-05-06 | 2016-12-28 | Sidense Corp. | Antifuse-anordnungsarchitektur mit geteiltem kanal |
US9123572B2 (en) | 2004-05-06 | 2015-09-01 | Sidense Corporation | Anti-fuse memory cell |
DE102008035805B4 (de) * | 2008-07-31 | 2013-01-31 | Advanced Micro Devices, Inc. | Herstellung von Gatedielektrika in PMOS- und NMOS-Transistoren |
JP2011014824A (ja) * | 2009-07-06 | 2011-01-20 | Elpida Memory Inc | 半導体装置の製造方法 |
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US3982967A (en) * | 1975-03-26 | 1976-09-28 | Ibm Corporation | Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths |
US4098618A (en) * | 1977-06-03 | 1978-07-04 | International Business Machines Corporation | Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation |
JPS5650532A (en) * | 1979-10-01 | 1981-05-07 | Hitachi Ltd | Manufacture of semiconductor device |
JPS5737830A (en) * | 1980-08-19 | 1982-03-02 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS5854638A (ja) * | 1981-09-28 | 1983-03-31 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS6116576A (ja) * | 1984-07-03 | 1986-01-24 | Ricoh Co Ltd | 半導体装置の製造方法 |
JPS63300518A (ja) * | 1987-05-29 | 1988-12-07 | Fujitsu Ltd | 誘電体膜の形成方法 |
DE68915508T2 (de) * | 1988-10-25 | 1994-12-15 | Matsushita Electronics Corp | Verfahren zur Herstellung einer nicht-flüchtigen Speicheranordnung. |
JPH0340431A (ja) * | 1989-07-07 | 1991-02-21 | Fuji Electric Co Ltd | シリコン半導体装置の酸化膜形成方法 |
-
1993
- 1993-06-15 US US08/077,570 patent/US5330920A/en not_active Expired - Lifetime
-
1994
- 1994-06-07 EP EP94108709A patent/EP0631308B1/de not_active Expired - Lifetime
- 1994-06-07 DE DE69414764T patent/DE69414764T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0631308B1 (de) | 1998-11-25 |
DE69414764T2 (de) | 1999-06-10 |
EP0631308A2 (de) | 1994-12-28 |
US5330920A (en) | 1994-07-19 |
EP0631308A3 (de) | 1996-06-12 |
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