DE69434234D1 - Chipkarte und Herstellungsmethode - Google Patents

Chipkarte und Herstellungsmethode

Info

Publication number
DE69434234D1
DE69434234D1 DE69434234T DE69434234T DE69434234D1 DE 69434234 D1 DE69434234 D1 DE 69434234D1 DE 69434234 T DE69434234 T DE 69434234T DE 69434234 T DE69434234 T DE 69434234T DE 69434234 D1 DE69434234 D1 DE 69434234D1
Authority
DE
Germany
Prior art keywords
manufacturing
chip card
card
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69434234T
Other languages
English (en)
Other versions
DE69434234T2 (de
Inventor
Mitsuo Usami
Takashi Tase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE69434234D1 publication Critical patent/DE69434234D1/de
Application granted granted Critical
Publication of DE69434234T2 publication Critical patent/DE69434234T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07728—Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
DE69434234T 1993-08-04 1994-07-28 Chipkarte und Herstellungsmethode Expired - Fee Related DE69434234T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP19326793 1993-08-04
JP19326793 1993-08-04

Publications (2)

Publication Number Publication Date
DE69434234D1 true DE69434234D1 (de) 2005-02-17
DE69434234T2 DE69434234T2 (de) 2005-12-08

Family

ID=16305104

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69434234T Expired - Fee Related DE69434234T2 (de) 1993-08-04 1994-07-28 Chipkarte und Herstellungsmethode

Country Status (4)

Country Link
US (4) US5689136A (de)
EP (3) EP0637841A3 (de)
KR (3) KR100332282B1 (de)
DE (1) DE69434234T2 (de)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689136A (en) * 1993-08-04 1997-11-18 Hitachi, Ltd. Semiconductor device and fabrication method
US5719437A (en) * 1996-04-19 1998-02-17 Lucent Technologies Inc. Smart cards having thin die
US6027958A (en) * 1996-07-11 2000-02-22 Kopin Corporation Transferred flexible integrated circuit
FR2756955B1 (fr) * 1996-12-11 1999-01-08 Schlumberger Ind Sa Procede de realisation d'un circuit electronique pour une carte a memoire sans contact
EP1034942A4 (de) * 1996-12-26 2005-07-06 Hitachi Ltd Halbleiteranordnung und herstellungsverfahren dafür
FR2761498B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Module electronique et son procede de fabrication et carte a puce comportant un tel module
US6031269A (en) * 1997-04-18 2000-02-29 Advanced Micro Devices, Inc. Quadruple gate field effect transistor structure for use in integrated circuit devices
US5889302A (en) * 1997-04-21 1999-03-30 Advanced Micro Devices, Inc. Multilayer floating gate field effect transistor structure for use in integrated circuit devices
US5936280A (en) 1997-04-21 1999-08-10 Advanced Micro Devices, Inc. Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices
DE19750316A1 (de) * 1997-11-13 1999-05-27 Siemens Ag Siliziumfolie als Träger von Halbleiterschaltungen als Teil von Karten
JP2000099678A (ja) * 1998-09-18 2000-04-07 Hitachi Ltd Ｉｃカード及びその製造方法
US6358782B1 (en) 1998-10-20 2002-03-19 Citizen Watch Co., Ltd. Method of fabricating a semiconductor device having a silicon-on-insulator substrate and an independent metal electrode connected to the support substrate
US6246010B1 (en) * 1998-11-25 2001-06-12 3M Innovative Properties Company High density electronic package
DE69941548D1 (de) * 1998-11-30 2009-11-26 Hitachi Ltd Verfahren zur Montage eines elektronischen Schaltungschips
TW460927B (en) * 1999-01-18 2001-10-21 Toshiba Corp Semiconductor device, mounting method for semiconductor device and manufacturing method for semiconductor device
JP4460669B2 (ja) * 1999-03-19 2010-05-12 株式会社東芝 半導体装置
US6617671B1 (en) * 1999-06-10 2003-09-09 Micron Technology, Inc. High density stackable and flexible substrate-based semiconductor device modules
FR2796739B1 (fr) * 1999-07-23 2001-11-02 Gemplus Card Int Procede pour la fabrication d'une carte a puce et produit obtenu
FR2798225B1 (fr) * 1999-09-03 2001-10-12 Gemplus Card Int Micromodule electronique et procede de fabrication et d'integration de tels micromodules pour la realisation de dispositifs portatifs
US6197663B1 (en) 1999-12-07 2001-03-06 Lucent Technologies Inc. Process for fabricating integrated circuit devices having thin film transistors
US6320228B1 (en) 2000-01-14 2001-11-20 Advanced Micro Devices, Inc. Multiple active layer integrated circuit and a method of making such a circuit
JP2001203319A (ja) * 2000-01-18 2001-07-27 Sony Corp 積層型半導体装置
US6433414B2 (en) * 2000-01-26 2002-08-13 Casio Computer Co., Ltd. Method of manufacturing flexible wiring board
JP2001222751A (ja) * 2000-02-14 2001-08-17 Toshiba Electric Appliance Co Ltd 自動販売機温度制御装置
JP3604988B2 (ja) * 2000-02-14 2004-12-22 シャープ株式会社 半導体装置およびその製造方法
US6396138B1 (en) * 2000-02-15 2002-05-28 International Rectifier Corporation Chip array with two-sided cooling
US6743680B1 (en) 2000-06-22 2004-06-01 Advanced Micro Devices, Inc. Process for manufacturing transistors having silicon/germanium channel regions
US6429484B1 (en) 2000-08-07 2002-08-06 Advanced Micro Devices, Inc. Multiple active layer structure and a method of making such a structure
JP2002164358A (ja) * 2000-11-28 2002-06-07 Mitsubishi Electric Corp 半導体装置用基材および半導体装置の製造方法
US6429145B1 (en) * 2001-01-26 2002-08-06 International Business Machines Corporation Method of determining electrical properties of silicon-on-insulator wafers
US7086600B2 (en) * 2001-02-02 2006-08-08 Renesas Technology Corporation Electronic device and method of manufacturing the same
DE10111028A1 (de) * 2001-03-07 2002-09-19 Infineon Technologies Ag Chipkartenmodul
DE10113769A1 (de) * 2001-03-21 2002-10-02 Infineon Technologies Ag Halbleiterchip
US6709935B1 (en) 2001-03-26 2004-03-23 Advanced Micro Devices, Inc. Method of locally forming a silicon/geranium channel layer
US8415208B2 (en) * 2001-07-16 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
JP3898077B2 (ja) * 2001-11-13 2007-03-28 株式会社フジクラ フレキシブルプリント配線板の製造方法
JP2004021814A (ja) * 2002-06-19 2004-01-22 Konica Minolta Holdings Inc Ｉｃカードの作成方法及びｉｃカード
JP4062728B2 (ja) * 2002-07-02 2008-03-19 コニカミノルタホールディングス株式会社 Ｉｃカード
JP3866178B2 (ja) * 2002-10-08 2007-01-10 株式会社ルネサステクノロジ Ｉｃカード
EP1420456B1 (de) * 2002-11-13 2013-05-22 Oki Data Corporation Monolithisches Halbleiterbauelement und optischer Druckkopf
US7823777B2 (en) * 2003-01-03 2010-11-02 American Express Travel Related Services Company, Inc. Metal-containing transaction card and method of making same
US8033457B2 (en) 2003-01-03 2011-10-11 American Express Travel Related Services Company, Inc. Metal-containing transaction card and method of making the same
WO2004063977A2 (en) * 2003-01-03 2004-07-29 American Express Travel Related Services Company, Inc. Metal containing transaction card and method of making the same
US7868358B2 (en) * 2003-06-06 2011-01-11 Northrop Grumman Systems Corporation Coiled circuit device with active circuitry and methods for making the same
US20080009687A1 (en) * 2003-06-06 2008-01-10 Smith Joseph T Coiled circuit bio-sensor
US7795647B2 (en) * 2003-06-06 2010-09-14 Northrop Grumman Systems Corporation Curled semiconductor transistor
US7667283B1 (en) 2003-06-06 2010-02-23 Northrop Grumman Systems Corporation Coiled circuit camera
ATE527691T1 (de) * 2003-06-06 2011-10-15 Northrop Grumman Systems Corp Gewundenes schaltkreisbauelement und dessen herstellungsverfahren
EP1494167A1 (de) * 2003-07-04 2005-01-05 Koninklijke Philips Electronics N.V. Flexibles Halbleiter-Bauelement und Identifikationsetikett
US7399274B1 (en) * 2003-08-19 2008-07-15 National Semiconductor Corporation Sensor configuration for a capsule endoscope
JP2007507101A (ja) * 2003-09-24 2007-03-22 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体装置、半導体装置の製造方法、識別ラベル及び情報担体
US7768405B2 (en) 2003-12-12 2010-08-03 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and manufacturing method thereof
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
EP1769468A1 (de) * 2004-07-13 2007-04-04 Koninklijke Philips Electronics N.V. Sicherheitspapier und solches papier enthaltende artikel
US7397066B2 (en) * 2004-08-19 2008-07-08 Micron Technology, Inc. Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
CN101010706B (zh) * 2004-09-03 2012-07-11 株式会社半导体能源研究所 健康数据收集系统及半导体器件
US7190039B2 (en) * 2005-02-18 2007-03-13 Micron Technology, Inc. Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
JP2006277178A (ja) * 2005-03-29 2006-10-12 Aruze Corp ゲーム用カード
US7232740B1 (en) 2005-05-16 2007-06-19 The United States Of America As Represented By The National Security Agency Method for bumping a thin wafer
DE102005038132B4 (de) 2005-08-11 2008-04-03 Infineon Technologies Ag Chipmodul und Chipkarte
US20100047959A1 (en) * 2006-08-07 2010-02-25 Emcore Solar Power, Inc. Epitaxial Lift Off on Film Mounted Inverted Metamorphic Multijunction Solar Cells
KR101378418B1 (ko) * 2007-11-01 2014-03-27 삼성전자주식회사 이미지센서 모듈 및 그 제조방법
DE102009006165B4 (de) 2009-01-26 2022-03-24 Centropix Global Ag Magnetfeldapplikator
US8778199B2 (en) 2009-02-09 2014-07-15 Emoore Solar Power, Inc. Epitaxial lift off in inverted metamorphic multijunction solar cells
US8198739B2 (en) * 2010-08-13 2012-06-12 Endicott Interconnect Technologies, Inc. Semi-conductor chip with compressible contact structure and electronic package utilizing same
JP6331498B2 (ja) * 2014-03-07 2018-05-30 富士通オプティカルコンポーネンツ株式会社 光モジュール
KR102284652B1 (ko) 2014-08-28 2021-08-02 삼성전자 주식회사 반도체 패키지
DE102015014408A1 (de) * 2015-11-06 2017-05-11 Giesecke & Devrient Gmbh Stabile Chipkarte, Spulenanordnung und Verfahren zum Bereitstellen einer Chipkarte
DE102016106698A1 (de) * 2016-04-12 2017-10-12 Infineon Technologies Ag Chipkarte und Verfahren zum Herstellen einer Chipkarte
US10438895B1 (en) 2018-06-08 2019-10-08 American Semiconductor, Inc. Flexible micro-module
US10860914B1 (en) 2019-12-31 2020-12-08 Capital One Services, Llc Contactless card and method of assembly

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4337814A (en) * 1980-09-22 1982-07-06 Caterpillar Tractor Co. Air valve conduit in the track wall of a tire
NL191959B (nl) * 1981-03-24 1996-07-01 Gao Ges Automation Org Identificatiekaart met IC-bouwsteen en dragerelement voor een IC-bouwsteen.
DE3153769C2 (de) * 1981-04-14 1995-10-26 Gao Ges Automation Org Trägerelement zum Einbau in Ausweiskarten
US4409471A (en) * 1981-12-17 1983-10-11 Seiichiro Aigo Information card
DE3151408C1 (de) * 1981-12-24 1983-06-01 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit einem IC-Baustein
JPS60209883A (ja) * 1984-04-02 1985-10-22 Toshiba Corp Ｉｃカ−ド
DE3420051A1 (de) * 1984-05-29 1985-12-05 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Datentraeger mit ic-baustein und verfahren zur herstellung eines derartigen datentraegers
JPS61145696A (ja) * 1984-12-19 1986-07-03 Matsushita Electric Ind Co Ltd Ｉｃカ−ド
US5203078A (en) * 1985-07-17 1993-04-20 Ibiden Co., Ltd. Printed wiring board for IC cards
JPH074995B2 (ja) * 1986-05-20 1995-01-25 株式会社東芝 Ｉｃカ−ド及びその製造方法
JPS63134294A (ja) * 1986-11-27 1988-06-06 株式会社東芝 Ｉｃカ−ド及びその製造方法
FR2616270B1 (fr) * 1987-06-05 1990-10-26 Thomson Csf Reseau de transistors predeposes, procede de realisation de ce reseau et d'un circuit electronique au moyen de ce reseau
JPH01209195A (ja) * 1988-02-18 1989-08-22 Sumitomo Electric Ind Ltd 非接触ｉｃカードとｉｃカードリーダ
US5208450A (en) * 1988-04-20 1993-05-04 Matsushita Electric Industrial Co., Ltd. IC card and a method for the manufacture of the same
GB8901189D0 (en) * 1989-01-19 1989-03-15 Avery W & T Limited Portable electronic token
AU626013B2 (en) * 1988-07-04 1992-07-23 Sony Corporation A thin electronic device having an integrated circuit chip and a power battery and a method for producing same
JPH0218096A (ja) * 1988-07-06 1990-01-22 Matsushita Electric Ind Co Ltd Ｉｃカード
JP2734025B2 (ja) 1988-11-16 1998-03-30 富士通株式会社 大規模集積回路の製造方法
JPH02257626A (ja) * 1989-03-30 1990-10-18 Kyushu Electron Metal Co Ltd 半導体基板の治具の結合装置
US5155068A (en) * 1989-08-31 1992-10-13 Sharp Kabushiki Kaisha Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
JPH0387299A (ja) * 1989-08-31 1991-04-12 Sharp Corp Ｉｃカード
JPH03150872A (ja) * 1989-11-07 1991-06-27 Ricoh Co Ltd 完全密着型イメージセンサ
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
JPH0475379A (ja) * 1990-07-17 1992-03-10 Seiko Epson Corp 半導体基板
US5347154A (en) * 1990-11-15 1994-09-13 Seiko Instruments Inc. Light valve device using semiconductive composite substrate
FR2671417B1 (fr) * 1991-01-04 1995-03-24 Solaic Sa Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue .
JPH04340251A (ja) * 1991-02-07 1992-11-26 Fujitsu Ltd 半導体装置の製造方法
GB2253591A (en) * 1991-03-15 1992-09-16 Gec Avery Ltd Integrated circuit card
JPH05291397A (ja) * 1992-04-07 1993-11-05 Toshiba Corp コレットおよび半導体装置の製造方法
US5689136A (en) * 1993-08-04 1997-11-18 Hitachi, Ltd. Semiconductor device and fabrication method
JP3305843B2 (ja) * 1993-12-20 2002-07-24 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
US6051877A (en) 2000-04-18
EP0862134A2 (de) 1998-09-02
US20020027274A1 (en) 2002-03-07
EP0637841A2 (de) 1995-02-08
DE69434234T2 (de) 2005-12-08
KR950007075A (ko) 1995-03-21
US6486541B2 (en) 2002-11-26
KR100332282B1 (ko) 2002-09-04
EP0637841A3 (de) 1995-11-29
KR100332284B1 (ko) 2002-04-12
US5689136A (en) 1997-11-18
KR100332285B1 (ko) 2002-04-12
US6291877B1 (en) 2001-09-18
EP1523039A1 (de) 2005-04-13
EP0862134A3 (de) 1999-04-14
EP0862134B1 (de) 2005-01-12

Similar Documents

Publication Publication Date Title
DE69434234D1 (de) Chipkarte und Herstellungsmethode
DE69635724D1 (de) Kontaktlose Chipkarte und Herstellungsverfahren
DE69425592T2 (de) Dünne Chipkarte und ihr Herstellungsverfahren.
DE69435045D1 (de) Halbleiter-Anordnung und Herstellungsverfahren dafür
DE69637439D1 (de) Ringoszillatorschaltung und chipkarte
DE69716310T2 (de) Chipkarte und chipkartenmodul
DE69524569T2 (de) Datenformleser und -verfahren
DE69430829T2 (de) Mehrchipmodul und Herstellungsverfahren dafür
DE69732719D1 (de) Chipkarte und chipkartenmodul
KR950034612A (ko) 반도체 구조물 및 그 제조 방법
KR960009110A (ko) 반도체 장치 및 그 제조방법
DE69314867D1 (de) Kontaktlose IC-Karte sowie deren Herstellungs- und Prüfverfahren
DE69413602D1 (de) Halbleiteranordnung und Herstellungsverfahren
DE69510337D1 (de) Halbleiterspeicheranordnungen und herstellungsverfahren
DE69435205D1 (de) Dünne Halbleitervorrichtung und Herstellungsverfahren
EP0683450A3 (de) Kartenartige Halbleiteranordnung und Verfahren zu deren Herstellung.
DE69424728D1 (de) Halbleiteranordnung und zugehörige Herstellungsmethode
KR960009107A (ko) 반도체장치와 그 제조방법
KR960015900A (ko) 반도체 장치 및 그 제조방법
FI941951A0 (fi) Sirutyyppinen piirikomponentti ja menetelmä sen valmistamiseksi
BR9603590A (pt) Chip para cartão eletrónico e cartão eletrónico
DE69420944T2 (de) Halbleitervorrichtung und herstellungsverfahren
KR960012313A (ko) 반도체 장치 및 그 제조방법
DE69314466T2 (de) Chip-Karte
DE69500633T2 (de) Hülsenförmiger-Informationsträger und Herstellungsverfahren

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee