DE69718134D1 - Verfahren zur Herstellung einer hochintegrierten Schaltung - Google Patents

Verfahren zur Herstellung einer hochintegrierten Schaltung

Info

Publication number
DE69718134D1
DE69718134D1 DE69718134T DE69718134T DE69718134D1 DE 69718134 D1 DE69718134 D1 DE 69718134D1 DE 69718134 T DE69718134 T DE 69718134T DE 69718134 T DE69718134 T DE 69718134T DE 69718134 D1 DE69718134 D1 DE 69718134D1
Authority
DE
Germany
Prior art keywords
manufacturing
integrated circuit
highly integrated
highly
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69718134T
Other languages
English (en)
Other versions
DE69718134T2 (de
Inventor
Satoru Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69718134D1 publication Critical patent/DE69718134D1/de
Application granted granted Critical
Publication of DE69718134T2 publication Critical patent/DE69718134T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
DE69718134T 1996-11-29 1997-10-23 Verfahren zur Herstellung einer hochintegrierten Schaltung Expired - Lifetime DE69718134T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP31892896 1996-11-29
JP31892896A JP3938220B2 (ja) 1996-11-29 1996-11-29 大規模集積回路装置の製造方法及び大規模集積回路装置

Publications (2)

Publication Number Publication Date
DE69718134D1 true DE69718134D1 (de) 2003-02-06
DE69718134T2 DE69718134T2 (de) 2009-09-17

Family

ID=18104556

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69718134T Expired - Lifetime DE69718134T2 (de) 1996-11-29 1997-10-23 Verfahren zur Herstellung einer hochintegrierten Schaltung

Country Status (5)

Country Link
US (1) US6012833A (de)
EP (1) EP0845810B1 (de)
JP (1) JP3938220B2 (de)
KR (1) KR100336826B1 (de)
DE (1) DE69718134T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304998B1 (en) * 1997-03-27 2001-10-16 Fujitsu Limited Method of manufacturing integrated circuit device
JP2000011031A (ja) * 1998-06-26 2000-01-14 Mitsubishi Electric Corp 半導体集積回路の論理回路検証装置および論理回路検証方法
US6370675B1 (en) * 1998-08-18 2002-04-09 Advantest Corp. Semiconductor integrated circuit design and evaluation system using cycle base timing
JP2001021624A (ja) * 1999-07-07 2001-01-26 Fujitsu Ltd テストデータ生成システム及び方法並びにテストデータ生成プログラムを記録した記録媒体
US7024640B2 (en) * 2001-06-29 2006-04-04 Koninklijke Philips Electronics N.V. Integrated circuit cell identification
US6567971B1 (en) 2001-12-20 2003-05-20 Logicvision, Inc. Circuit synthesis method using technology parameters extracting circuit
JP2003196341A (ja) * 2001-12-25 2003-07-11 Nec Electronics Corp 半導体装置の設計方法
JP4738719B2 (ja) 2003-05-09 2011-08-03 ルネサスエレクトロニクス株式会社 半導体回路装置の設計方法、設計された半導体回路装置、設計システム、及び記録媒体
US7484193B2 (en) * 2003-08-28 2009-01-27 Sun Microsystems, Inc. Method and software for predicting the timing delay of a circuit path using two different timing models
DE102004017313A1 (de) * 2004-04-06 2005-07-28 Infineon Technologies Ag Halbleiterbauteil mit oberflächenmontierbaren Aussenkontakten und Verfahren zum Anordnen derartiger Aussenkontakte
KR100688525B1 (ko) * 2005-01-26 2007-03-02 삼성전자주식회사 이벤트 구동 스위치 레벨 시뮬레이션 방법 및 시뮬레이터
JP4540540B2 (ja) 2005-05-02 2010-09-08 ルネサスエレクトロニクス株式会社 遅延計算装置
WO2008120322A1 (ja) 2007-03-28 2008-10-09 Fujitsu Microelectronics Limited 信号遅延評価プログラム、信号遅延評価方法、および信号遅延評価装置
JP2009037278A (ja) * 2007-07-31 2009-02-19 Nec Corp 動作タイミング検証装置、方法、及び、プログラム
US8762904B2 (en) 2012-03-28 2014-06-24 Synopsys, Inc. Optimizing logic synthesis for environmental insensitivity

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62189739A (ja) * 1986-02-17 1987-08-19 Hitachi Ltd 半導体集積回路装置
US4849904A (en) * 1987-06-19 1989-07-18 International Business Machines Corporation Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices
US4924430A (en) * 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits
US4954953A (en) * 1988-04-07 1990-09-04 Vlsi Technology, Inc. Machine process for converting one representation of an electronic integrated circuit into another representation
JPH02265268A (ja) * 1989-04-05 1990-10-30 Nec Corp 順序論理回路の設計方法
US5572437A (en) * 1990-04-06 1996-11-05 Lsi Logic Corporation Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models
US5617325A (en) * 1990-06-22 1997-04-01 Vlsi Technology, Inc. Method for estimating interconnect delays in integrated circuits
JP2563663B2 (ja) * 1990-08-20 1996-12-11 松下電器産業株式会社 論理設計処理装置およびタイミング調整方法
JP2643585B2 (ja) * 1990-11-05 1997-08-20 日本電気株式会社 集積回路
US5274568A (en) * 1990-12-05 1993-12-28 Ncr Corporation Method of estimating logic cell delay time
JPH04345051A (ja) * 1991-05-22 1992-12-01 Toshiba Corp セミカスタム集積回路におけるマクロセル形成方法
JPH04372169A (ja) * 1991-06-21 1992-12-25 Mitsubishi Electric Corp マスタスライスｌｓｉ
JP3076410B2 (ja) * 1991-07-08 2000-08-14 株式会社東芝 半導体集積回路の設計方法
JP2854733B2 (ja) * 1991-08-23 1999-02-03 三菱電機株式会社 遅延時間計算装置及び遅延時間計算方法
JP3256597B2 (ja) * 1993-06-21 2002-02-12 株式会社東芝 自動配置設計方法および自動配置設計装置
US5774371A (en) * 1994-08-03 1998-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit and layout designing method for the same

Also Published As

Publication number Publication date
KR100336826B1 (ko) 2002-10-25
EP0845810B1 (de) 2003-01-02
US6012833A (en) 2000-01-11
KR19980042220A (ko) 1998-08-17
DE69718134T2 (de) 2009-09-17
JP3938220B2 (ja) 2007-06-27
JPH10162040A (ja) 1998-06-19
EP0845810A1 (de) 1998-06-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE