DE69722425D1 - Verfahren und vorrichtung zum routing von netzen in einem elektronischen gerät - Google Patents

Verfahren und vorrichtung zum routing von netzen in einem elektronischen gerät

Info

Publication number
DE69722425D1
DE69722425D1 DE69722425T DE69722425T DE69722425D1 DE 69722425 D1 DE69722425 D1 DE 69722425D1 DE 69722425 T DE69722425 T DE 69722425T DE 69722425 T DE69722425 T DE 69722425T DE 69722425 D1 DE69722425 D1 DE 69722425D1
Authority
DE
Germany
Prior art keywords
routing networks
electronic device
routing
networks
electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69722425T
Other languages
English (en)
Other versions
DE69722425T2 (de
Inventor
Gabriel Bracha
Eytan Weisberger
Ilan Algor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69722425D1 publication Critical patent/DE69722425D1/de
Application granted granted Critical
Publication of DE69722425T2 publication Critical patent/DE69722425T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
DE69722425T 1996-10-15 1997-10-13 Verfahren und vorrichtung zum routing von netzen in einem elektronischen gerät Expired - Fee Related DE69722425T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/730,046 US6505331B1 (en) 1996-10-15 1996-10-15 Method for routing of nets in an electronic device
PCT/EP1997/005633 WO1998016891A1 (en) 1996-10-15 1997-10-13 A method for routing of nets in an electronic device

Publications (2)

Publication Number Publication Date
DE69722425D1 true DE69722425D1 (de) 2003-07-03
DE69722425T2 DE69722425T2 (de) 2003-12-18

Family

ID=24933688

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69722425T Expired - Fee Related DE69722425T2 (de) 1996-10-15 1997-10-13 Verfahren und vorrichtung zum routing von netzen in einem elektronischen gerät

Country Status (7)

Country Link
US (1) US6505331B1 (de)
EP (1) EP0932874B1 (de)
JP (1) JP2001505716A (de)
DE (1) DE69722425T2 (de)
HK (1) HK1021664A1 (de)
TW (1) TW354424B (de)
WO (1) WO1998016891A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6898773B1 (en) 2002-01-22 2005-05-24 Cadence Design Systems, Inc. Method and apparatus for producing multi-layer topological routes
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US6957408B1 (en) 2002-01-22 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for routing nets in an integrated circuit layout
US7107564B1 (en) 2001-06-03 2006-09-12 Cadence Design Systems, Inc. Method and apparatus for routing a set of nets
US7069530B1 (en) 2001-06-03 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for routing groups of paths
US6957411B1 (en) 2001-06-03 2005-10-18 Cadence Design Systems, Inc. Gridless IC layout and method and apparatus for generating such a layout
JP2003132106A (ja) * 2001-10-24 2003-05-09 Bogenpfeil:Kk 適切ネットワーク形状である準最小の木の形成・探索・生成方法及びそのプログラムを記録した情報記録媒体
US6973634B1 (en) 2002-01-22 2005-12-06 Cadence Design Systems, Inc. IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout
US7013451B1 (en) 2002-01-22 2006-03-14 Cadence Design Systems, Inc. Method and apparatus for performing routability checking
US7117468B1 (en) 2002-01-22 2006-10-03 Cadence Design Systems, Inc. Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts
US6938234B1 (en) 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7089524B1 (en) 2002-01-22 2006-08-08 Cadence Design Systems, Inc. Topological vias route wherein the topological via does not have a coordinate within the region
US6944841B1 (en) 2002-01-22 2005-09-13 Cadence Design Systems, Inc. Method and apparatus for proportionate costing of vias
US7080329B1 (en) 2002-01-22 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for identifying optimized via locations
US7096449B1 (en) 2002-01-22 2006-08-22 Cadence Design Systems, Inc. Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts
US7047512B1 (en) 2002-06-04 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for specifying a cost function that represents the estimated distance between an external state and a set of states in a space
US7069531B1 (en) 2002-07-15 2006-06-27 Cadence Design Systems, Inc. Method and apparatus for identifying a path between source and target states in a space with more than two dimensions
US6889371B1 (en) 2002-06-04 2005-05-03 Cadence Design Systems, Inc. Method and apparatus for propagating a function
US7073151B1 (en) 2002-06-04 2006-07-04 Cadence Design Systems, Inc. Method and apparatus for identifying a path between a set of source states and a set of target states in a triangulated space
GB2393533A (en) * 2002-09-27 2004-03-31 Zuken Ltd Routing of interconnected regions e.g. of electrical circuits
US7003752B2 (en) 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US6892369B2 (en) 2002-11-18 2005-05-10 Cadence Design Systems, Inc. Method and apparatus for costing routes of nets
US6996789B2 (en) 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7080342B2 (en) 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7093221B2 (en) 2002-11-18 2006-08-15 Cadence Design Systems, Inc. Method and apparatus for identifying a group of routes for a set of nets
US7171635B2 (en) 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
US7216308B2 (en) 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout
US7047513B2 (en) 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7010771B2 (en) 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US6930904B2 (en) * 2002-11-22 2005-08-16 Sun Microsystems, Inc. Circuit topology for high-speed memory access
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US7111267B2 (en) * 2004-08-27 2006-09-19 Lsi Logic Corporation Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths
US7885269B2 (en) * 2008-03-03 2011-02-08 Microsoft Corporation Network analysis with Steiner trees
US20100185994A1 (en) * 2008-08-14 2010-07-22 Pikus Fedor G Topological Pattern Matching
CN103902774B (zh) * 2014-03-31 2017-01-25 福州大学 X结构下超大规模集成电路总体布线方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US5072402A (en) 1989-10-10 1991-12-10 Vlsi Technology, Inc. Routing system and method for integrated circuits
US5491641A (en) 1993-10-04 1996-02-13 Lsi Logic Corporation Towards optical steiner tree routing in the presence of rectilinear obstacles
JP3137178B2 (ja) * 1996-08-14 2001-02-19 日本電気株式会社 集積回路の配線設計方法および装置
US5923646A (en) * 1996-08-30 1999-07-13 Nynex Science & Technology Method for designing or routing a self-healing ring in a communications network and a self-healing ring routed in accordance with the method

Also Published As

Publication number Publication date
WO1998016891A1 (en) 1998-04-23
US6505331B1 (en) 2003-01-07
JP2001505716A (ja) 2001-04-24
EP0932874B1 (de) 2003-05-28
DE69722425T2 (de) 2003-12-18
TW354424B (en) 1999-03-11
HK1021664A1 (en) 2000-06-23
EP0932874A1 (de) 1999-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee