DE69722447T2 - Software-pipeline-verarbeitung einer hyperblock-schleife - Google Patents

Software-pipeline-verarbeitung einer hyperblock-schleife Download PDF

Info

Publication number
DE69722447T2
DE69722447T2 DE69722447T DE69722447T DE69722447T2 DE 69722447 T2 DE69722447 T2 DE 69722447T2 DE 69722447 T DE69722447 T DE 69722447T DE 69722447 T DE69722447 T DE 69722447T DE 69722447 T2 DE69722447 T2 DE 69722447T2
Authority
DE
Germany
Prior art keywords
hyperblock
loop
pipeline processing
software pipeline
software
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69722447T
Other languages
English (en)
Other versions
DE69722447D1 (de
Inventor
Pohua Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE69722447D1 publication Critical patent/DE69722447D1/de
Application granted granted Critical
Publication of DE69722447T2 publication Critical patent/DE69722447T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/445Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G06F8/4452Software pipelining
DE69722447T 1996-03-28 1997-03-13 Software-pipeline-verarbeitung einer hyperblock-schleife Expired - Fee Related DE69722447T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/630,858 US5920724A (en) 1996-03-28 1996-03-28 Software pipelining a hyperblock loop
PCT/US1997/003999 WO1997036228A1 (en) 1996-03-28 1997-03-13 Software pipelining a hyperblock loop

Publications (2)

Publication Number Publication Date
DE69722447D1 DE69722447D1 (de) 2003-07-03
DE69722447T2 true DE69722447T2 (de) 2004-01-15

Family

ID=24528840

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69722447T Expired - Fee Related DE69722447T2 (de) 1996-03-28 1997-03-13 Software-pipeline-verarbeitung einer hyperblock-schleife

Country Status (7)

Country Link
US (2) US5920724A (de)
EP (1) EP0954778B1 (de)
AU (1) AU2324397A (de)
CA (1) CA2250924C (de)
DE (1) DE69722447T2 (de)
TW (1) TW339430B (de)
WO (1) WO1997036228A1 (de)

Families Citing this family (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920724A (en) * 1996-03-28 1999-07-06 Intel Corporation Software pipelining a hyperblock loop
US6226790B1 (en) * 1997-02-28 2001-05-01 Silicon Graphics, Inc. Method for selecting optimal parameters for compiling source code
US6567976B1 (en) 1997-03-20 2003-05-20 Silicon Graphics, Inc. Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code
US5943501A (en) * 1997-06-27 1999-08-24 Wisconsin Alumni Research Foundation Multiple processor, distributed memory computer with out-of-order processing
US6253373B1 (en) * 1997-10-07 2001-06-26 Hewlett-Packard Company Tracking loop entry and exit points in a compiler
DE69837138T2 (de) * 1997-12-31 2007-08-16 Texas Instruments Inc., Dallas Unterbrechbare mehrfache Ausfuehrungseinheitverarbeitung waehrend mehrfacher Zuweisung von Register verwendenden Operationen
US6341370B1 (en) * 1998-04-24 2002-01-22 Sun Microsystems, Inc. Integration of data prefetching and modulo scheduling using postpass prefetch insertion
US6192515B1 (en) * 1998-07-17 2001-02-20 Intel Corporation Method for software pipelining nested loops
US6820250B2 (en) * 1999-06-07 2004-11-16 Intel Corporation Mechanism for software pipelining loop nests
US6438747B1 (en) * 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6594820B1 (en) * 1999-09-28 2003-07-15 Sun Microsystems, Inc. Method and apparatus for testing a process in a computer system
ATE366958T1 (de) * 2000-01-14 2007-08-15 Texas Instruments France Mikroprozessor mit ermässigtem stromverbrauch
US7725885B1 (en) * 2000-05-09 2010-05-25 Hewlett-Packard Development Company, L.P. Method and apparatus for trace based adaptive run time compiler
JP2003005980A (ja) * 2001-06-22 2003-01-10 Matsushita Electric Ind Co Ltd コンパイル装置およびコンパイルプログラム
US7113517B2 (en) 2001-09-27 2006-09-26 International Business Machines Corporation Configurable hardware scheduler calendar search algorithm
JP3974063B2 (ja) * 2003-03-24 2007-09-12 松下電器産業株式会社 プロセッサおよびコンパイラ
CA2433379A1 (en) * 2003-06-25 2004-12-25 Ibm Canada Limited - Ibm Canada Limitee Modulo scheduling of multiple instruction chains
US7321940B1 (en) 2003-06-30 2008-01-22 Cisco Technology, Inc. Iterative architecture for hierarchical scheduling
JP2006338616A (ja) 2005-06-06 2006-12-14 Matsushita Electric Ind Co Ltd コンパイラ装置
US8024714B2 (en) 2006-11-17 2011-09-20 Microsoft Corporation Parallelizing sequential frameworks using transactions
US8010550B2 (en) * 2006-11-17 2011-08-30 Microsoft Corporation Parallelizing sequential frameworks using transactions
US7860847B2 (en) * 2006-11-17 2010-12-28 Microsoft Corporation Exception ordering in contention management to support speculative sequential semantics
US8051411B2 (en) * 2007-08-08 2011-11-01 National Tsing Hua University Method for copy propagations for a processor with distributed register file design
US10698859B2 (en) 2009-09-18 2020-06-30 The Board Of Regents Of The University Of Texas System Data multicasting with router replication and target instruction identification in a distributed multi-core processing architecture
KR101523020B1 (ko) 2010-06-18 2015-05-26 더 보드 오브 리전츠 오브 더 유니버시티 오브 텍사스 시스템 결합된 분기 타깃 및 프레디킷 예측
US9063735B2 (en) * 2010-10-19 2015-06-23 Samsung Electronics Co., Ltd. Reconfigurable processor and method for processing loop having memory dependency
US8752036B2 (en) * 2011-10-31 2014-06-10 Oracle International Corporation Throughput-aware software pipelining for highly multi-threaded systems
US9513922B2 (en) 2012-04-20 2016-12-06 Freescale Semiconductor, Inc. Computer system and a method for generating an optimized program code
US9038042B2 (en) * 2012-06-29 2015-05-19 Analog Devices, Inc. Staged loop instructions
US9239712B2 (en) * 2013-03-29 2016-01-19 Intel Corporation Software pipelining at runtime
WO2014193381A1 (en) * 2013-05-30 2014-12-04 Intel Corporation Dynamic optimization of pipelined software
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
US9740529B1 (en) 2013-12-05 2017-08-22 The Mathworks, Inc. High throughput synchronous resource-constrained scheduling for model-based design
US9329875B2 (en) * 2014-04-28 2016-05-03 International Business Machines Corporation Global entry point and local entry point for callee function
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9940136B2 (en) 2015-06-26 2018-04-10 Microsoft Technology Licensing, Llc Reuse of decoded instructions
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US10719321B2 (en) 2015-09-19 2020-07-21 Microsoft Technology Licensing, Llc Prefetching instruction blocks
US10776115B2 (en) 2015-09-19 2020-09-15 Microsoft Technology Licensing, Llc Debug support for block-based processor
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10198263B2 (en) 2015-09-19 2019-02-05 Microsoft Technology Licensing, Llc Write nullification
US10095519B2 (en) 2015-09-19 2018-10-09 Microsoft Technology Licensing, Llc Instruction block address register
US10452399B2 (en) 2015-09-19 2019-10-22 Microsoft Technology Licensing, Llc Broadcast channel architectures for block-based processors
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US20170083327A1 (en) 2015-09-19 2017-03-23 Microsoft Technology Licensing, Llc Implicit program order
US10031756B2 (en) 2015-09-19 2018-07-24 Microsoft Technology Licensing, Llc Multi-nullification
US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US10936316B2 (en) 2015-09-19 2021-03-02 Microsoft Technology Licensing, Llc Dense read encoding for dataflow ISA
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US10180840B2 (en) 2015-09-19 2019-01-15 Microsoft Technology Licensing, Llc Dynamic generation of null instructions
US10061584B2 (en) 2015-09-19 2018-08-28 Microsoft Technology Licensing, Llc Store nullification in the target field
US11106467B2 (en) 2016-04-28 2021-08-31 Microsoft Technology Licensing, Llc Incremental scheduler for out-of-order block ISA processors
KR20180038875A (ko) * 2016-10-07 2018-04-17 삼성전자주식회사 데이터 입출력 유닛, 전자 장치 및 그 제어 방법들
US11531552B2 (en) 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core
US10628142B2 (en) * 2017-07-20 2020-04-21 Texas Instruments Incorporated Loop break
US10108538B1 (en) 2017-07-31 2018-10-23 Google Llc Accessing prologue and epilogue data
US10963379B2 (en) 2018-01-30 2021-03-30 Microsoft Technology Licensing, Llc Coupling wide memory interface to wide write back paths
US10824429B2 (en) 2018-09-19 2020-11-03 Microsoft Technology Licensing, Llc Commit logic and precise exceptions in explicit dataflow graph execution architectures
US11714620B1 (en) 2022-01-14 2023-08-01 Triad National Security, Llc Decoupling loop dependencies using buffers to enable pipelining of loops

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0475139A (ja) * 1990-07-18 1992-03-10 Toshiba Corp ループ並列化装置
JPH04102926A (ja) * 1990-08-22 1992-04-03 Nec Corp 繰り返しループの展開最適化方式
JP3102027B2 (ja) * 1990-11-20 2000-10-23 日本電気株式会社 ループ制御のネスティング管理機構
JP3032031B2 (ja) * 1991-04-05 2000-04-10 株式会社東芝 ループ最適化方法及び装置
US5386562A (en) * 1992-05-13 1995-01-31 Mips Computer Systems, Inc. Circular scheduling method and apparatus for executing computer programs by moving independent instructions out of a loop
US5367651A (en) * 1992-11-30 1994-11-22 Intel Corporation Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling
US5920724A (en) * 1996-03-28 1999-07-06 Intel Corporation Software pipelining a hyperblock loop

Also Published As

Publication number Publication date
US6016399A (en) 2000-01-18
CA2250924C (en) 2001-01-30
DE69722447D1 (de) 2003-07-03
AU2324397A (en) 1997-10-17
EP0954778A1 (de) 1999-11-10
CA2250924A1 (en) 1997-10-02
EP0954778B1 (de) 2003-05-28
US5920724A (en) 1999-07-06
TW339430B (en) 1998-09-01
WO1997036228A1 (en) 1997-10-02
EP0954778A4 (de) 2002-04-24

Similar Documents

Publication Publication Date Title
DE69722447T2 (de) Software-pipeline-verarbeitung einer hyperblock-schleife
DE69831133D1 (de) Konfiguriation einer Datenverarbeitungspipeline
DE19781995T1 (de) Prozessor mit einer Wiederhol-Architektur
DK0865562T3 (da) Rørledningsforbindelsesdel
DE69835637D1 (de) Mehrweg-Datenverarbeitungspipeline
DE69528885D1 (de) Software-notizen
FI973239A (fi) Mikropiirin läpivienti
DE69532628D1 (de) Fixiersteuervorrichtung
NO20002852L (no) Rørforbindelse
NO960355D0 (no) Spyleanordning
NO955135L (no) Koplingsstykke
ID19818A (id) Pengolahan untuk mendapatkan nekel
FR2745624B1 (fr) Tuyau flexible
KR960704272A (ko) 스칼라 인터럽트-입력 수리 시스템(a scalar interrupt-acknowledgement system)
FR2722545B1 (fr) Agrafe a ondulations
DE59601102D1 (de) Mehrfachschlauch
DE69603506T2 (de) Reinigung einer komplettanlage
DE9403326U1 (de) Rohrleitung
IT236441Y1 (it) Valvola a farfalla
KR950023162U (ko) 간이부표
DE29521219U1 (de) Leitungskanal
KR970024461U (ko) 호스 클램프
FI945565A0 (fi) Käsiohjain
KR970022496U (ko) 호스 고정 훅
FI945894A0 (fi) Identifierare

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee