EP0100540A3 - Circuit arrangement for acquiring a regulation criterion for the adjustment of adaptive equalisers for digital data transmission - Google Patents
Circuit arrangement for acquiring a regulation criterion for the adjustment of adaptive equalisers for digital data transmission Download PDFInfo
- Publication number
- EP0100540A3 EP0100540A3 EP83107513A EP83107513A EP0100540A3 EP 0100540 A3 EP0100540 A3 EP 0100540A3 EP 83107513 A EP83107513 A EP 83107513A EP 83107513 A EP83107513 A EP 83107513A EP 0100540 A3 EP0100540 A3 EP 0100540A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- circuit arrangement
- acquiring
- adjustment
- data transmission
- digital data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT83107513T ATE38601T1 (en) | 1982-08-02 | 1983-07-29 | CIRCUIT ARRANGEMENT FOR OBTAINING THE CONTROL CRITERIA FOR SETTING ADAPTIVE EQUALIZERS IN DIGITAL DATA TRANSMISSION. |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE3228840 | 1982-08-02 | ||
DE19823228840 DE3228840A1 (en) | 1982-08-02 | 1982-08-02 | CIRCUIT ARRANGEMENT FOR OBTAINING THE REGULATORY CRITERIA FOR SETTING ADAPTIVE EQUALIZERS FOR DIGITAL DATA TRANSMISSION |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0100540A2 EP0100540A2 (en) | 1984-02-15 |
EP0100540A3 true EP0100540A3 (en) | 1986-02-19 |
EP0100540B1 EP0100540B1 (en) | 1988-11-09 |
Family
ID=6169940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP83107513A Expired EP0100540B1 (en) | 1982-08-02 | 1983-07-29 | Circuit arrangement for acquiring a regulation criterion for the adjustment of adaptive equalisers for digital data transmission |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0100540B1 (en) |
AT (1) | ATE38601T1 (en) |
DE (2) | DE3228840A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE9017847U1 (en) * | 1990-02-15 | 1992-09-24 | Ant Nachrichtentechnik Gmbh, 7150 Backnang, De | |
DE4415298A1 (en) * | 1994-04-30 | 1995-11-02 | Thomson Brandt Gmbh | Procedure for setting the parameters of an equalizer |
DE19743171A1 (en) * | 1997-09-30 | 1999-04-01 | Daimler Benz Ag | Method for equalizing a received signal |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3185963A (en) * | 1960-11-25 | 1965-05-25 | Stelma Inc | Synchronizing system having reversible counter means |
US3578914A (en) * | 1969-04-09 | 1971-05-18 | Lynch Communication Systems | Equalizer with automatic line build-out |
FR2059287A5 (en) * | 1969-08-29 | 1971-05-28 | Fujitsu Ltd | |
DE3210079A1 (en) * | 1981-03-20 | 1982-10-21 | Hitachi, Ltd., Tokyo | CHANGEABLE EQUALIZER |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3728649A (en) * | 1972-04-24 | 1973-04-17 | Bell Telephone Labor Inc | Automatic equalizer for digital cable transmission systems |
-
1982
- 1982-08-02 DE DE19823228840 patent/DE3228840A1/en not_active Withdrawn
-
1983
- 1983-07-29 EP EP83107513A patent/EP0100540B1/en not_active Expired
- 1983-07-29 AT AT83107513T patent/ATE38601T1/en not_active IP Right Cessation
- 1983-07-29 DE DE8383107513T patent/DE3378449D1/en not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3185963A (en) * | 1960-11-25 | 1965-05-25 | Stelma Inc | Synchronizing system having reversible counter means |
US3578914A (en) * | 1969-04-09 | 1971-05-18 | Lynch Communication Systems | Equalizer with automatic line build-out |
FR2059287A5 (en) * | 1969-08-29 | 1971-05-28 | Fujitsu Ltd | |
DE3210079A1 (en) * | 1981-03-20 | 1982-10-21 | Hitachi, Ltd., Tokyo | CHANGEABLE EQUALIZER |
Non-Patent Citations (1)
Title |
---|
PROCEEDINGS OF THE NATIONAL TELECOMMUNICATIONS CONFERENCE, Band 3.4, 29. November/3. Dezember 1981, Seiten E1.5.1. - E1.5.6, New Orleans, Louisiana, IEEE New York, US; H. TAKATORI et al.: "A new equalizing scheme for digital subscriber loop" * |
Also Published As
Publication number | Publication date |
---|---|
EP0100540B1 (en) | 1988-11-09 |
DE3228840A1 (en) | 1984-02-02 |
ATE38601T1 (en) | 1988-11-15 |
EP0100540A2 (en) | 1984-02-15 |
DE3378449D1 (en) | 1988-12-15 |
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Legal Events
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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