EP0179693A1 - Integrated-circuit structure containing high-voltage CMOS transistors and method of making the same - Google Patents

Integrated-circuit structure containing high-voltage CMOS transistors and method of making the same Download PDF

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EP0179693A1
EP0179693A1 EP85401860A EP85401860A EP0179693A1 EP 0179693 A1 EP0179693 A1 EP 0179693A1 EP 85401860 A EP85401860 A EP 85401860A EP 85401860 A EP85401860 A EP 85401860A EP 0179693 A1 EP0179693 A1 EP 0179693A1
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type
region
channel
regions
transistors
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EP0179693B1 (en
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Gilles Thomas
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Thales SA
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Thomson CSF SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated

Definitions

  • the present invention relates to integrated circuits and more particularly circuits produced using CMOS technology, that is to say incorporating on the same semiconductor substrate both N-channel MOS transistors and P-channel MOS transistors. is used in particular for the realization of logic functions and it makes it possible in particular to obtain circuits with low consumption and working at very low voltage (a few volts).
  • MOS transistor structures have already been proposed having improved voltage withstand making it possible to meet this requirement; these transistors have a drain region which is not immediately adjacent to the channel region (that is to say the region covered by the control gate), but which is separated from it by a region of the same type of conductivity that the much lower drain and doping region; this region is relatively large (several microns for example between the heavily doped drain region and the channel region) and it is used to support part of the applied voltage by allowing an extension towards the drain of the space charge which develops when the transistor is non-conductive.
  • An object of the invention is to propose a structure and a method for producing this structure, which allows manufacturing in a low number of steps and with a also low number of masks, this structure incorporating logic CMOS transistors ( low voltage) and N-channel and P-channel high-voltage MOS transistors.
  • Another object of the invention is to propose a structure incorporating logic CMOS transistors and high voltage CMOS transistors, this structure being such that it is also possible to incorporate bipolar transistors therein without modifying the manufacturing process. It is indeed very desirable, in an industrial manufacturing process, for the process steps to be as universal as possible so that a large number of products which are very different from one another can largely follow the same production line. Here, we want this to be possible even if these products incorporate elements as different as logical CMOS transistors (low voltage), high voltage CMOS transistors and bipolar transistors.
  • the manufacturing method according to the invention is therefore characterized in turn by the formation (implantation / diffusion) of P-type regions in a single step, starting from the surface of the N-type epitaxial layer, not only at the places intended to form wells encompassing N-channel MOS transistors in their entirety (source + drain + channel) but also in regions within which only the source (but not the drain) of N-channel MOS transistors will be broadcast later or that the drain (but not the source) of P-channel transistors
  • a P / P + substrate that is to say a P-type substrate, heavily doped on its rear face only (in particular when it is desired to produce in the circuit a bipolar PNP vertical power transistor whose collector is accessible from the back); or also an N + type substrate, heavily doped over its entire thickness, for example if one wishes to produce in the circuit a bipolar transistor of vertical NPN power whose collector is accessible from the rear face of the substrate.
  • N-type impurity antimony for example
  • a first localized implantation of an N-type impurity is carried out, with a high concentration, to locally form N-type regions 12 which will later constitute what are called buried layers.
  • This implantation is done through a resin mask open only at the places corresponding to the regions 12.
  • This N + type implantation is subsequently followed by an epitaxial growth of monocrystalline silicon over the entire upper face of the substrate 10.
  • an additional step is provided beforehand due to the fact that zones isolation by junction are provided between the various active circuit areas, for example between the various MOS transistors which do not have their sources connected to the same potential; more specifically, the isolation is made by P-type isolation walls crossing the entire epitaxial layer from its surface to the P-type substrate; these walls are formed by a double diffusion of P-type impurities, namely a diffusion going up from the bottom from the substrate and doping from the top from the surface of the epitaxial layer.
  • a second ion implantation is carried out on the upper surface of the substrate 10, with a P-type impurity this time (for example boron), this implantation is localized by a mask. of resin open at the places where an insulation wall is desired and the structure of FIG. 1 is then obtained with regions 12 of type N + and regions 14 of type P + flush with the surface of the substrate.
  • a P-type impurity for example boron
  • An epitaxial layer 16 of lightly doped monocrystalline silicon, of type N, is then grown over the entire upper surface of the substrate; during the growth of this layer, as well as in certain subsequent stages of heat treatment, the impurities implanted previously diffuse both towards the substrate 10 and towards the epitaxial layer 16, as indicated in FIG. 2.
  • the buried layer regions 12 have been shown straddling the border between the P-type starting substrate and the epitaxial layer 16 which covers it. As for in regions 14, they diffuse on the one hand downwards, reducing the influence of the parasitic lateral NPN formed by the buried layers, and on the other hand upwards where they form the lower part of the future isolation walls.
  • the integrated circuit not only to include field effect transistors (MOS) but also a vertical NPN bipolar transistor in which the collector current is collected by a portion of buried layer 12 located in- below this transistor.
  • MOS field effect transistors
  • an access well 18 is created to this buried layer; this well is a heavily doped N + type region, crossing the epitaxial layer 16, from its surface to the buried layer.
  • the best is then to make this access well by deep phosphorus diffusion (pre-deposit of POC1 3 ) immediately after the formation of the epitaxial layer 16.
  • FIG. 3 represents the structure of the integrated circuit at this stage of manufacture.
  • the next step is a fundamental step in the process. It consists in locally forming P-type regions with little doping (which will be designated by P- regions), which extend from the surface of the epitaxial layer over part of its depth (for example on 7 to 8 microns deep for an epitaxial layer of 15 microns).
  • These P-type regions - are simultaneously formed by localized ion implantation (a registered with appropriate masking resist and etched in a pattern corresponding to the regions to be formed).
  • the implanted impurity is preferably boron with a dose which may be of the order of 1.5 ⁇ 10 13 atoms / cm 2 .
  • This implantation is followed by a diffusion heat treatment so that the P - regions reach a sufficient depth (essentially dictated by the desired height for the boxes containing the N channel MOS transistors).
  • the surface concentration of P-type impurities in the P - regions becomes of the order of 10 16 atoms / cm 3 at the end of diffusion.
  • the next step consists in forming, by a conventional localized oxidation process, regions of thick silicon oxide surrounding the active zones, for example surrounding each MOS transistor.
  • These thick oxide regions will in particular serve as a support for the metal interconnections of the circuit.
  • a layer of silicon nitride 28 is deposited which is etched to eliminate it where the thick oxide is to be grown; implantation of N-type impurities (arsenic) is carried out at certain locations delimited by a resin mask, then implantation of P-type (boron) at other locations delimited by another resin mask.
  • N-type impurities arsenic
  • P-type boron
  • FIG. 5 represents the state of the structure at the end of this step, with zones of thick oxide 30 at various locations, and more precisely at locations where it is desired to avoid a metallic or metallic connection.
  • polyscrystalline silicon does not pass in the immediate vicinity of the semiconductor surface and does not induce an undesirable channel (or inversion layer) by field effect.
  • a thick oxide region 30 is particularly desirable between the drain region and the channel region of high voltage MOS transistors.
  • a thick oxide region 30 can be provided surrounding the access well 18 and the base region of these transistors.
  • the following step consists in uniformly forming on all the bare surfaces of monocrystalline silicon, between the thick oxide regions 30, a thin layer of silicon oxide intended to form the gate oxide of the MOS transistors.
  • This layer, 32 is formed by thermal oxidation of the semiconductor wafer.
  • a uniform layer 34 of polycrystalline silicon of a few thousand angstroms ( Figure 6), is uniformly deposited, by chemical decomposition in the gas phase and at low pressure (from silane).
  • This layer is doped either "in situ”, that is to say during its deposition, or after the deposition, by diffusion of phosphorus for example (pre-deposition of POC1 3 ), to obtain a sufficient conductivity of the polycrystalline silicon.
  • Polycrystalline silicon and thin oxide are then etched, using a CF 4 plasma for example and a resin mask, to define on the one hand the gates of the various low MOS transistors and high voltage, and possibly also a number of polycrystalline silicon interconnections.
  • FIG. 7 represents the structure integrated at this stage of manufacture, after removal of the resin mask.
  • the gate 29, resting on thin oxide, passes inside the surface of a P-type box 20 and allows the formation of a source zone and a drain zone in this box on either side of the grid;
  • the gate 31 passes outside a P-type region - and allows the formation of a source zone and a drain zone on either side of the gate outside a P - type region;
  • the gate 33 passes astride the boundary between a region 22 of P-type - and the epitaxial layer, and it allows the formation of a source area in the region 22 of a side of the grid, a drain zone outside this region 22 on the other side of the grid, and a channel zone in the region 22 under the grid;
  • the gate 35 passes astride the boundary between the epitaxial layer and a P-type region 24 - and allows the formation of a source zone in
  • the first implantation is an implantation of type P impurities at high concentration, intended to form source and drain regions of type P + of the P-channel MOS transistors as well as the base regions of the bipolar NPN transistors if there is takes place.
  • a layer of resin is deposited and etched which masks the areas which must not undergo P + type implantation, namely all of the N channel MOS transistors, high or low voltage, and the well d access 18 of the NPN transistor collector.
  • P-channel MOS transistors not masked by the resin it is the thick oxide regions and the polycrystalline silicon grids which serve as a mask delimiting precisely the implanted regions of type P +.
  • the implantation is carried out for example with boron.
  • the masking resin used during the P + type implantation is then eliminated and annealing is carried out.
  • Another layer of resin is deposited and etched for implantation (or diffusion) of the N + type; this resin layer masks the transistors which must not undergo this implantation, namely the P-channel MOS transistors (low voltage or high voltage) and the base region of the NPN transistors.
  • the thick oxide 30 and the polycrystalline silicon regions serve as a mask precisely delimiting the implanted regions of N + type; implantation can be performed with arsenic; Diffusion of arsenic in ampoule is also possible.
  • the manufacturing process ends with conventional steps, not shown, which are: a gas phase deposition of an insulating layer of silicon oxide, a creep of this layer, an etching to open contacts, a metallic deposit (aluminum) , etching of aluminum to define an interconnection pattern, deposition of an insulating passivation layer, etching of contact pads for connection to the pins of the housing, and encapsulation.
  • the P-type wells 20 - containing the low-voltage N-channel MOS transistors are separated from the substrate by a thickness of the N-type epitaxial layer.
  • an area Type P 14 was diffused before the epitaxial growth at the location of the caisson, so that this zone then rises to the caisson which then constitutes both a low voltage MOS N caisson and an isolation wall.
  • the starting substrate is of the N + type
  • a power element which would be what is called a vertical DMOS, that is to say a MOS with N channel broadcast whose drain consists of the rear side N of the substrate, the source consists of N + zones like the sources of the low-voltage N-channel MOS transistors, and the channel region is locally diffused with the diffusion of P-type wells - transistors N-channel low voltage MOS

Abstract

An integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS transistors and LV-PMOS transistors) and high-voltage n-channel and p-channel MOS transistors (HV-NMOS transistors and HV-PMOS transistors). There are formed at the same time first p- regions for the compartments of the LV-NMOS transistors, second p- regions in which only the sources and channels of the HV-NMOS transistors are incorporated, and third p- regions in which only the drains of the HV-PMOS transistors are incorporated.

Description

La présente invention concerne les circuits intégrés et plus particulièrement les circuits réalisés selon une technologie CMOS, c'est-à-dire incorporant sur un même substrat semiconducteur à la fois des transistors MOS à canal N et des transistors MOS à canal P. Cette technologie est utilisée notamment pour la réalisation de fonctions logiques et elle permet en particulier d'obtenir des circuits à faible consommation et travaillant à très basse tension (quelques volts).The present invention relates to integrated circuits and more particularly circuits produced using CMOS technology, that is to say incorporating on the same semiconductor substrate both N-channel MOS transistors and P-channel MOS transistors. is used in particular for the realization of logic functions and it makes it possible in particular to obtain circuits with low consumption and working at very low voltage (a few volts).

Cependant, on désire parfois obtenir une tenue en tension beaucoup plus élevée que celle que permet la technologie normale CMOS ; c'est le cas par exemple pour des étages de sortie commandant des dispositifs spéciaux tels que des dispositifs de visualisation alimentés sous une tension de l'ordre d'une centaine de volts.However, it is sometimes desired to obtain a much higher voltage withstand than that which is possible with normal CMOS technology; this is the case, for example, for output stages controlling special devices such as display devices supplied with a voltage of the order of a hundred volts.

On a déjà proposé des structures de transistors MOS ayant une tenue en tension améliorée permettant de répondre à cet impératif ; ces transistors possèdent une région de drain qui n'est pas immédiatement adjacente à la région de canal (c'est-à-dire la région recouverte par la grille de commande), mais qui en est séparée par une région de même type de conductivité que la région de drain et de dopage beaucoup plus faible ; cette région est relativement large (plusieurs microns par exemple entre la région de drain fortement dopée et la région de canal) et elle sert à supporter une partie de la tension appliquée en permettant une extension vers le drain de la charge d'espace qui se développe lorsque le transistor est non conducteur.MOS transistor structures have already been proposed having improved voltage withstand making it possible to meet this requirement; these transistors have a drain region which is not immediately adjacent to the channel region (that is to say the region covered by the control gate), but which is separated from it by a region of the same type of conductivity that the much lower drain and doping region; this region is relatively large (several microns for example between the heavily doped drain region and the channel region) and it is used to support part of the applied voltage by allowing an extension towards the drain of the space charge which develops when the transistor is non-conductive.

Dans les quelques tentatives qui ont pu être faites jusqu'à maintenant pour réaliser sur un même substrat semiconducteur à la fois des transistors CMOS logiques et des transistors MOS haute tension, on a toujours proposé des structures qui ont l'inconvénient de nécessiter un nombre relativement élevé d'étapes de fabrication et un nombre élevé de masques différents.In the few attempts that have been made so far to produce on the same semiconductor substrate both logic CMOS transistors and high voltage MOS transistors, structures have always been proposed which have the disadvantage to require a relatively high number of manufacturing steps and a high number of different masks.

Un but de l'invention est de proposer une structure et un procédé de réalisation de cette structure, qui permet une fabrication en un nombre d'étapes peu élevé et avec un nombre de masques également peu élevé, cette structure incorporant des transistors CMOS logiques (basse tension) et des transistors MOS haute tension à canal N et à canal P.An object of the invention is to propose a structure and a method for producing this structure, which allows manufacturing in a low number of steps and with a also low number of masks, this structure incorporating logic CMOS transistors ( low voltage) and N-channel and P-channel high-voltage MOS transistors.

Un autre but de l'invention est de proposer une structure incorporant des transistors CMOS logiques et des transistors CMOS haute tension, cette structure étant telle qu'on puisse y incorporer aussi des transistors bipolaires sans modifier le procédé de fabrication. Il est en effet très souhaitable, dans un processus industriel de fabrication, que les étapes de procédé soient aussi universelles que possible pour qu'un grand nombre de produits très différents les uns des autres puissent suivre dans une large mesure une même chaine de fabrication. Ici, on veut que cela soit possible même si ces produits incorporent des éléments aussi différents que des transistors CMOS logiques (basse tension), des transistors CMOS haute tension et des transistors bipolaires.Another object of the invention is to propose a structure incorporating logic CMOS transistors and high voltage CMOS transistors, this structure being such that it is also possible to incorporate bipolar transistors therein without modifying the manufacturing process. It is indeed very desirable, in an industrial manufacturing process, for the process steps to be as universal as possible so that a large number of products which are very different from one another can largely follow the same production line. Here, we want this to be possible even if these products incorporate elements as different as logical CMOS transistors (low voltage), high voltage CMOS transistors and bipolar transistors.

La structure de base que l'on propose ici pour la réalisation d'un circuit incorporant des transistors MOS logiques à canal N et à canal P et des transistors MOS haute tension à canal N et à canal P comprend :

  • - une pastille semiconductrice constituée d'un substrat recouvert d'une couche épitaxiale peu dopée de type N ;
  • - des premières régions de type P , peu dopées, s'étendant à partir de la surface de la pastille semiconductrice sur une partie de la profondeur de la couche épitaxiale, ces régions constituant des caissons dans lesquels sont formés la source, le drain et le canal de transistors MOS basse tension à canal N ;
  • - des régions de type P fortement dopées, moins profondes que les régions de type P- peu dopées, s'étendant à partir de la surface de la pastille semiconductrice et constituant la source et le drain des transistors MOS à canal P, basse tension ou haute tension ;
  • - des régions de type N fortement dopées, moins profondes que les régions de type P-, s'étendant à partir de la surface de la pastille semiconductrice pour constituer la source et le drain de transistors MOS à canal N, basse tension ou haute tension ;
  • - au moins une seconde région de type P-, de même profil de concentration que les premières régions et s'étendant jusqu'à la même profondeur, cette seconde région entourant une région de source de type N+ et constituant une région de canal d'un transistor MOS haute tension à canal N, transistor qui comporte par ailleurs une région de drain de type N située en dehors de la seconde région et écartée d'elle de telle manière qu'il existe une zone de couche épitaxiale de type N peu dopée, non directement contrôlée par la grille du transistor, entre la région de drain et la seonde région,
  • - au moins une troisième région de type P-, de même profil de concentration que les premières et secondes régions et s'étendant jusqu'à la même profondeur, cette troisième région entourant une région de drain de type P d'un transistor MOS haute tension à canal P dont la région de canal est constituée par une région de couche épitaxiale de type N peu dopée, adjacente à la troisième région, la région de drain de type P+ de ce transistor étant écartée de la région de canal de telle manière qu'il existe entre elles une zone de la troisième région non directement contrôlée par la grille du transistor, et la région de source de ce transistor étant située en dehors de la troisième région.
The basic structure which is proposed here for the production of a circuit incorporating logic N-channel and P-channel MOS transistors and high-voltage N-channel and P-channel MOS transistors comprises:
  • - a semiconductor wafer consisting of a substrate covered with a lightly doped N-type epitaxial layer;
  • - first P-type regions, lightly doped, extending from the surface of the semiconductor wafer over part of the depth of the epitaxial layer, these regions constituting wells in which the source, the drain and the N-channel low-voltage MOS transistor channel;
  • - heavily doped P-type regions, less deep than the P-type - lightly doped regions, extending from the surface of the semiconductor wafer and constituting the source and the drain of P-channel, low-voltage MOS transistors or high tension ;
  • - heavily doped N-type regions, less deep than the P-type regions - , extending from the surface of the semiconductor wafer to constitute the source and the drain of N-channel MOS transistors, low voltage or high voltage ;
  • - at least a second P-type region - , with the same concentration profile as the first regions and extending to the same depth, this second region surrounding an N + type source region and constituting a channel region d '' a high-voltage N-channel MOS transistor, a transistor which moreover comprises an N-type drain region situated outside the second region and spaced from it so that there is an N-type epitaxial layer region doped, not directly controlled by the gate of the transistor, between the drain region and the second region,
  • - at least a third P-type region - , with the same concentration profile as the first and second regions and extending to the same depth, this third region surrounding a P-type drain region of a high MOS transistor P channel voltage of which the channel region consists of a lightly doped N-type epitaxial layer region, adjacent to the third region, the P + type drain region of this transistor being spaced from the channel region in such a way that there exists between them an area of the third region not directly controlled by the gate of the transistor, and the source region of this transistor being located outside the third region.

Cette structure, dont la caractéristique la plus marquante est le fait que les transistors MOS haute tension, aussi bien à canal N qu'à canal P, sont réalisés à partir de diffusions localisées dans une couche épitaxiée peu dopée et identiques à la diffusion des caissons d'isolement des MOS N basse tension, permet une réalisation qui est très simple et qui rend possible des extensions notamment à des structures où des transistors CMOS et des transistors bipolaires sont combinés sans qu'il soit nécessaire de changer le processus global de traitement des tranches de circuits intégrés.This structure, the most striking characteristic of which is that the high-voltage MOS transistors, both N-channel and P-channel, are produced from localized diffusions in an epitaxial layer with little doping and identical to the diffusion of wells of isolation of low voltage MOS N, allows an embodiment which is very simple and which makes possible extensions in particular to structures where CMOS transistors and bipolar transistors are combined without the need to change the overall process of processing wafers of integrated circuits.

Le procédé de fabrication selon l'invention se caractérise donc quant à lui par la formation (implantation/diffusion) de régions de type P en une même étape, à partir de la surface de la couche épitaxiée de type N, non seulement aux endroits destinés à former des caissons englobant des transistors MOS à canal N dans leur totalité (source + drain + canal) mais aussi dans des régions à l'intérieur desquelles on ne diffusera ultérieurement que la source (mais pas le drain) de transistors MOS à canal N ou que le drain (mais pas la source) de transistors à canal P.The manufacturing method according to the invention is therefore characterized in turn by the formation (implantation / diffusion) of P-type regions in a single step, starting from the surface of the N-type epitaxial layer, not only at the places intended to form wells encompassing N-channel MOS transistors in their entirety (source + drain + channel) but also in regions within which only the source (but not the drain) of N-channel MOS transistors will be broadcast later or that the drain (but not the source) of P-channel transistors

D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture de la description détaillée qui suit et qui est faite en référence aux dessins annexés dans lesquels :

  • - les figures 1 à 7 représentent les étapes successives du procédé de fabrication selon l'invention ;
  • - la figure 8 représente en coupe transversale la structure d'un exemple de réalisation de circuit intégré selon l'invention, avant la mise en place d'interconnexions métalliques superficielles.
Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which:
  • - Figures 1 to 7 show the successive stages of the manufacturing process according to the invention;
  • - Figure 8 shows in cross section the structure of an exemplary embodiment of an integrated circuit according to the invention, before the establishment of surface metal interconnections.

Sur ces figures, les échelles horizontales et verticales ne sont pas respectées, pour faciliter la représentation.In these figures, the horizontal and vertical scales are not respected, to facilitate the representation.

Dans l'exemple de réalisation représenté, on part d'un substrat 10 de silicium de type P, étant entendu que dans certaines applications on pourrait partir de substrats différents ; par exemple un substrat P/P+ c'est-à-dire un substrat de type P, fortement dopé sur sa face arrière seulement (notamment lorsqu'on veut réaliser dans le circuit un transistor de puissance bipolaire PNP vertical dont le collecteur est accessible par la face arrière) ; ou encore un substrat de type N+, fortement dopé sur toute son épaisseur, par exemple si on veut réaliser dans le circuit un transistor bipolaire de puissance NPN vertical dont le collecteur est accessible par la face arrière du substrat.In the embodiment shown, one starts from a P-type silicon substrate 10, it being understood that in certain applications one could start from different substrates; for example a P / P + substrate, that is to say a P-type substrate, heavily doped on its rear face only (in particular when it is desired to produce in the circuit a bipolar PNP vertical power transistor whose collector is accessible from the back); or also an N + type substrate, heavily doped over its entire thickness, for example if one wishes to produce in the circuit a bipolar transistor of vertical NPN power whose collector is accessible from the rear face of the substrate.

Sur la face avant du substrat (face supérieure sur les figures), on effectue une première implantation localisée d'une impureté de type N (antimoine par exemple), avec une concentration élevée, pour former localement des régions 12 de type N qui constitueront ultérieurement ce qu'on appelle des couches enterrées.On the front face of the substrate (upper face in the figures), a first localized implantation of an N-type impurity (antimony for example) is carried out, with a high concentration, to locally form N-type regions 12 which will later constitute what are called buried layers.

Cette implantation se fait à travers un masque de résine ouvert seulement aux endroits correspondant aux régions 12.This implantation is done through a resin mask open only at the places corresponding to the regions 12.

Cette implantation de type N+ est suivie ultérieurement d'une croissance épitaxiale de silicium monocristallin sur toute la face supérieure du substrat 10. Toutefois, dans l'exemple de réalisation plus précisément décrit, on prévoit auparavant une étape supplémentaire due au fait que des zones d'isolement par jonction sont prévues entre les diverses zones actives de circuit, par exemple entre les différents transistors MOS qui n'ont pas leurs sources reliées au même potentiel ; plus précisément, l'isolement est fait par des murs d'isolement de type P traversant toute la couche épitaxiale depuis sa surface jusqu'au substrat de type P ; ces murs sont formés par une double diffusion d'impuretés de type P, à savoir une diffusion remontant par le bas depuis le substrat et un dopage par le haut depuis la surface de la couche épitaxiale. C'est pourquoi, avant l'étape de croissance épitaxiale, on procède à une deuxième implantation ionique sur la surface supérieure du substrat 10, avec une impureté de type P cette fois (par exemple du bore), cette implantation est localisée par un masque de résine ouvert aux endroits où un mur d'isolement est désiré et on obtient alors la structure de la figure 1 avec des régions 12 de type N+ et des régions 14 de type P+ affleurant à la surface du substrat.This N + type implantation is subsequently followed by an epitaxial growth of monocrystalline silicon over the entire upper face of the substrate 10. However, in the embodiment more precisely described, an additional step is provided beforehand due to the fact that zones isolation by junction are provided between the various active circuit areas, for example between the various MOS transistors which do not have their sources connected to the same potential; more specifically, the isolation is made by P-type isolation walls crossing the entire epitaxial layer from its surface to the P-type substrate; these walls are formed by a double diffusion of P-type impurities, namely a diffusion going up from the bottom from the substrate and doping from the top from the surface of the epitaxial layer. This is why, before the epitaxial growth step, a second ion implantation is carried out on the upper surface of the substrate 10, with a P-type impurity this time (for example boron), this implantation is localized by a mask. of resin open at the places where an insulation wall is desired and the structure of FIG. 1 is then obtained with regions 12 of type N + and regions 14 of type P + flush with the surface of the substrate.

On fait croître alors sur toute la surface supérieure du substrat une couche épitaxiale 16 de silicium monocristallin peu dopé, de type N ; pendant la croissance de cette couche, ainsi d'ailleurs que dans certaines étapes ultérieures de traitement thermique, les impuretés implantées précédemment diffusent à la fois vers le substrat 10 et vers la couche épitaxiale 16, comme cela est indiqué sur la figure 2.An epitaxial layer 16 of lightly doped monocrystalline silicon, of type N, is then grown over the entire upper surface of the substrate; during the growth of this layer, as well as in certain subsequent stages of heat treatment, the impurities implanted previously diffuse both towards the substrate 10 and towards the epitaxial layer 16, as indicated in FIG. 2.

Dans les figures suivantes, on a représenté les régions de couche enterrée 12 à cheval sur la frontière entre le substrat de départ de type P et la couche épitaxiale 16 qui le recouvre. Quant aux régions 14, elles diffusent d'une part vers le bas, réduisant l'influence du NPN latéral parasite formé par les couches enterrées, et d'autre part vers le haut où elles forment la partie inférieure des futurs murs d'isolement.In the following figures, the buried layer regions 12 have been shown straddling the border between the P-type starting substrate and the epitaxial layer 16 which covers it. As for in regions 14, they diffuse on the one hand downwards, reducing the influence of the parasitic lateral NPN formed by the buried layers, and on the other hand upwards where they form the lower part of the future isolation walls.

Dans l'exemple décrit, on a prévu que le circuit intégré comprend non seulement des transistors à effet de champ (MOS) mais aussi un transistor bipolaire NPN vertical dans lequel le courant de collecteur est recueilli par une portion de couche enterrée 12 située en-dessous de ce transistor. Dans ce cas, on crée un puits d'accès 18 à cette couche enterrée ; ce puits est une région de type N+ fortement dopée, traversant la couche épitaxiale 16, depuis sa surface jusqu'à la couche enterrée. Le mieux est alors de réaliser ce puits d'accès par diffusion profonde de phosphore (pré- dépot de POC13) immédiatement après la formation de la couche épitaxiale 16. La figure 3 représente la structure du circuit intégré à ce stade de la fabrication.In the example described, provision has been made for the integrated circuit not only to include field effect transistors (MOS) but also a vertical NPN bipolar transistor in which the collector current is collected by a portion of buried layer 12 located in- below this transistor. In this case, an access well 18 is created to this buried layer; this well is a heavily doped N + type region, crossing the epitaxial layer 16, from its surface to the buried layer. The best is then to make this access well by deep phosphorus diffusion (pre-deposit of POC1 3 ) immediately after the formation of the epitaxial layer 16. FIG. 3 represents the structure of the integrated circuit at this stage of manufacture.

L'étape suivante est une étape fondamentale du procédé. Elle consiste à former localement des régions de type P peu dopées (qu'on désignera par régions P-), qui s'étendent à partir de la surface de la couche épitaxiale sur une partie de la profondeur de celle-ci (par exemple sur 7 à 8 microns de profondeur pour une couche épitaxiale de 15 microns).The next step is a fundamental step in the process. It consists in locally forming P-type regions with little doping (which will be designated by P- regions), which extend from the surface of the epitaxial layer over part of its depth (for example on 7 to 8 microns deep for an epitaxial layer of 15 microns).

La localisation de ces régions est la suivante :

  • 1°- là où on désire réaliser des transistors MOS à canal N à faible tenue en tension (MOS N BT) notamment pour les fonctions logiques du circuit, on forme une région P- 20 qui constitue un caisson fermé dans lequel se situera la totalité d'un transistor MOS à canal N (ou même de plusieurs), c'est-à-dire à la fois la région de source, la région de drain et la région de canal, cette dernière étant constituée par la partie superficielle de la région 20 de type P-.
  • 2°- là où on désire réaliser des transistors MOS à canal N à tenue en tension élevée (MOS N HT), par exemple pour des étages de sortie, on forme une région P 22 à l'intérieur de laquelle on diffusera ultérieurement, pour chaque transistor, une seule région N+ fortement dopée et moins profonde que la région 22, pour constituer la source du transistor, le canal étant constitué par une portion de cette région 22 (d'où la même tension de seuil pour le NMOS HT et le NMOS BT).
  • .3°- là où on désire réaliser des transistors MOS haute tension à canal P, on forme une région P- 24 à l'intérieur de laquelle on diffusera ultérieurement, pour chaque transistor, une seule région de type P+ fortement dopée et moins profonde que la région 24, pour constituer le drain du transistor, le canal étant constitué par une portion de la couche épitaxiale 16 de type N.
  • 4*- si l'isolement entre zones actives se fait par jonction (murs d'isolement de type P comme c'est le cas dans l'exemple décrit), on formera une région P 26 à l'endroit de ces murs d'isolement, c'est-à-dire à l'aplomb de chacune des régions diffusées 14, de telle manière que chaque région 14 rejoigne une région 26 correspondante pour compléter le mur d'isolement qui traverse alors la totalité de l'épaisseur de la couche épitaxiale 16.
The location of these regions is as follows:
  • 1 ° - where it is desired to make N-channel MOS transistors with low voltage withstand (MOS N LV), in particular for the logic functions of the circuit, a region P - 20 is formed which constitutes a closed box in which all of it will be located of an N-channel MOS transistor (or even of several), that is to say both the source region, the drain region and the channel region, the latter being constituted by the surface part of the region 20 of type P -.
  • 2 ° - where it is desired to produce N-channel MOS transistors with high voltage withstand (MOS N HT), for example for output stages, a region P 22 is formed inside which will be broadcast later, for each transistor, a single region N + heavily doped and less deep than region 22, to constitute the source of the transistor, the channel being constituted by a portion of this region 22 (hence the same threshold voltage for NMOS HT and NMOS BT).
  • .3 ° - where it is desired to produce high-voltage MOS transistors with P channel, a P - 24 region is formed inside which will be diffused subsequently, for each transistor, a single P + type region highly doped and less deeper than region 24, to constitute the drain of the transistor, the channel being constituted by a portion of the epitaxial layer 16 of type N.
  • 4 * - if the isolation between active zones is done by junction (type P isolation walls as is the case in the example described), a P 26 region will be formed at the location of these walls isolation, that is to say directly above each of the diffused regions 14, such that each region 14 joins a corresponding region 26 to complete the isolation wall which then crosses the entire thickness of the epitaxial layer 16.

Ces différentes régions de type P- sont formées simultanément par implantation ionique localisée (avec une résine de masquage appropriée déposée et gravée selon un motif correspondant aux régions à former). L'impureté implantée est de préférence du bore avec une dose qui peut-être de l'ordre de 1,5 x 1013 atomes/cm2. Cette implantation est suivie d'un traitement thermique de diffusion pour que les régions P- atteignent une profondeur suffisante (dictée essentiellement par la hauteur désirée pour les caissons contenant les transistors MOS à canal N). A titre d'exemple, la concentration superficielle en impuretés de type P dans les régions P- devient de l'ordre de 1016 atomes/cm3 en fin de diffusion.These P-type regions - are simultaneously formed by localized ion implantation (a registered with appropriate masking resist and etched in a pattern corresponding to the regions to be formed). The implanted impurity is preferably boron with a dose which may be of the order of 1.5 × 10 13 atoms / cm 2 . This implantation is followed by a diffusion heat treatment so that the P - regions reach a sufficient depth (essentially dictated by the desired height for the boxes containing the N channel MOS transistors). By way of example, the surface concentration of P-type impurities in the P - regions becomes of the order of 10 16 atoms / cm 3 at the end of diffusion.

L'étape suivante consiste à former, par un procédé d'oxydation localisée classique, des régions d'oxyde de silicium épais entourant les zones actives, par exemple entourant chaque transistor MOS.The next step consists in forming, by a conventional localized oxidation process, regions of thick silicon oxide surrounding the active zones, for example surrounding each MOS transistor.

Ces régions d'oxyde épais serviront notamment de support aux interconnexions métalliques du circuit.These thick oxide regions will in particular serve as a support for the metal interconnections of the circuit.

Pour cela, on dépose une couche de nitrure de silicium 28 que l'on grave pour l'éliminer là où on veut faire croître l'oxyde épais ; on effectue une implantation d'impuretés de type N (arsenic) à certains endroits délimités par un masque de résine, puis une implantation de type P (bore) à d'autres endroits délimités par un autre masque de résine. Ces implantations dites "de champ", situées ultérieurement sous l'oxyde épais, sont destinées à éviter la mise en conduction des transistors MOS parasites formés sous l'oxyde épais ; ces implantations sont classiques et n'ont pas été représentées pour ne pas surcharger les figures. La figure 4 montre la structure intégrée à ce stade de la fabrication.For this, a layer of silicon nitride 28 is deposited which is etched to eliminate it where the thick oxide is to be grown; implantation of N-type impurities (arsenic) is carried out at certain locations delimited by a resin mask, then implantation of P-type (boron) at other locations delimited by another resin mask. These so-called "field" implantations, located subsequently under the thick oxide, are intended to avoid conduction of the parasitic MOS transistors formed under the thick oxide; these layouts are classic and have not been shown so as not to overload the figures. Figure 4 shows the integrated structure at this stage of manufacturing.

On effectue alors un traitement thermique oxydant qui produit la croissance de l'oxyde épais là où il n'y a pas de nitrure après quoi on retire le nitrure. On peut noter que pendant ce traitement thermique se produit une diffusion des impuretés implantées dans les régions P- (20, 22, 24, 26)An oxidizing heat treatment is then carried out which produces the growth of the thick oxide where there is no nitride after which the nitride is removed. It can be noted that during this heat treatment a diffusion of the impurities implanted in the regions P - (20, 22, 24, 26) occurs.

La figure 5 représente l'état de la structure à la fin de cette étape, avec des zones d'oxyde épais 30 à divers endroits, et plus précisément à des endroits où l'on désire éviter qu'une intercon- nection métallique ou en silicium polyscristallin, ne passe à proximité immédiate de la surface semiconductrice et n'induise par effet de champ un canal (ou couche d'inversion) indésirable.FIG. 5 represents the state of the structure at the end of this step, with zones of thick oxide 30 at various locations, and more precisely at locations where it is desired to avoid a metallic or metallic connection. polyscrystalline silicon, does not pass in the immediate vicinity of the semiconductor surface and does not induce an undesirable channel (or inversion layer) by field effect.

Par exemple, une région d'oxyde épais 30 est particulièrement désirable entre la région de drain et la région de canal des transistors MOS haute tension.For example, a thick oxide region 30 is particularly desirable between the drain region and the channel region of high voltage MOS transistors.

En ce qui concerne les transistors bipolaires éventuellement présents, on peut prévoir une région d'oxyde épais 30 entourant le puits d'accès 18 et la région de base de ces transistors.As regards the bipolar transistors which may be present, a thick oxide region 30 can be provided surrounding the access well 18 and the base region of these transistors.

L'étape suivante consiste à former uniformément sur toutes les surfaces dénudées de silicium monocristallin, entre les régions d'oxyde épais 30, une couche mince d'oxyde de silicium destinée à former l'oxyde de grille des transistors MOS. Cette couche, 32, est formée par oxydation thermique de la tranche semiconductrice.The following step consists in uniformly forming on all the bare surfaces of monocrystalline silicon, between the thick oxide regions 30, a thin layer of silicon oxide intended to form the gate oxide of the MOS transistors. This layer, 32, is formed by thermal oxidation of the semiconductor wafer.

Après cela, on dépose uniformément, par décomposition chimique en phase gazeuse et à basse pression (à partir de silane), une couche uniforme 34 de silicium polycristallin, de quelques milliers d'angstrôms (figure 6).After that, a uniform layer 34 of polycrystalline silicon, of a few thousand angstroms (Figure 6), is uniformly deposited, by chemical decomposition in the gas phase and at low pressure (from silane).

Cette couche est dopée soit "in situ", c'est -à-dire pendant son dépôt, soit après le dépôt, par diffusion de phosphore par exemple (prédépôt de POC13), pour obtenir une conductivité suffisante du silicium polycristallin.This layer is doped either "in situ", that is to say during its deposition, or after the deposition, by diffusion of phosphorus for example (pre-deposition of POC1 3 ), to obtain a sufficient conductivity of the polycrystalline silicon.

On procède alors à la gravure du silicium polycristallin et de l'oxyde mince, à l'aide d'un plasma de CF 4 par exemple et d'un masque de résine, pour définir d'une part les grilles des différents transistors MOS basse et haute tension, et d'autre part éventuellement un certain nombre d'interconnexions en silicium polycristallin.Polycrystalline silicon and thin oxide are then etched, using a CF 4 plasma for example and a resin mask, to define on the one hand the gates of the various low MOS transistors and high voltage, and possibly also a number of polycrystalline silicon interconnections.

La figure 7 représente la structure intégrée à ce stade de fabrication, après enlèvement du masque de résine.FIG. 7 represents the structure integrated at this stage of manufacture, after removal of the resin mask.

Pour les transistors MOS basse tension à canal N, la grille, 29, reposant sur de l'oxyde mince, passe à l'intérieur de la surface d'un caisson 20 de type P et permet la formation d'une zone de source et d'une zone de drain dans ce caisson de part et d'autre de la grille ; pour les transistors MOS basse tension à canal P, la grille 31 passe en dehors d'une région de type P- et permet la formation d'une zone de source et d'une zone de drain de part et d'autre de la grille en dehors d'une région de type P- ; pour les transistors MOS haute tension à canal N, la grille 33 passe à cheval sur la frontière entre une région 22 de type P- et la couche épitaxiale, et elle permet la formation d'une zone de source dans cette région 22 d'un côté de la grille, d'une zone de drain en dehors de cette région 22 de l'autre côté de la grille, et d'une zone de canal dans la région 22 sous la grille ; enfin, pour les transistors MOS haute tension à canal P, la grille 35 passe à cheval sur la frontière entre la couche épitaxiale et une région 24 de type P-, et elle permet la formation d'une zone de source dans la couche épitaxiale en dehors de cette région 24 d'un côté de la grille, d'une zone de drain dans la région 24 de l'autre côté de la grille et d'une zone de canal dans la couche épitaxiale en dehors de la région 24, sous la grille.For low-voltage N-channel MOS transistors, the gate, 29, resting on thin oxide, passes inside the surface of a P-type box 20 and allows the formation of a source zone and a drain zone in this box on either side of the grid; for low-voltage P-channel MOS transistors, the gate 31 passes outside a P-type region - and allows the formation of a source zone and a drain zone on either side of the gate outside a P - type region; for high-voltage MOS transistors N-channel, the gate 33 passes astride the boundary between a region 22 of P-type - and the epitaxial layer, and it allows the formation of a source area in the region 22 of a side of the grid, a drain zone outside this region 22 on the other side of the grid, and a channel zone in the region 22 under the grid; Finally, for high-voltage MOS P-channel transistors, the gate 35 passes astride the boundary between the epitaxial layer and a P-type region 24 - and allows the formation of a source zone in the epitaxial layer outside this region 24 on one side of the grid, from a drain zone in region 24 on the other side of the grid and a channel area in the epitaxial layer outside of region 24, under the grid.

Le silicium polycristallin qui subsiste sert alors de masque d'autoalignement pour les étapes d'implantation ionique qui suivent.The polycrystalline silicon which remains then serves as a self-alignment mask for the steps of ion implantation which follow.

La première implantation est une implantation d'impuretés de type P à concentration élevée, destinée à former des régions de source et de drain de type P+ des transistors MOS à canal P ainsi que les régions de base des transistors bipolaires NPN s'il y a lieu. Pour cela, on dépose et on grave une couche de résine qui masque les zones qui ne doivent pas subir d'implantation de type P+, à savoir l'ensemble des transistors MOS à canal N, haute ou basse tension, et le puits d'accès 18 du collecteur des transistors NPN. Pour les transistors MOS à canal P non masqués par la résine, ce sont les régions d'oxyde épais et les grilles de silicium polycristallin qui servent de masque délimitant précisément les régions implantées de type P+. L'implantation est effectuée par exemple avec du bore.The first implantation is an implantation of type P impurities at high concentration, intended to form source and drain regions of type P + of the P-channel MOS transistors as well as the base regions of the bipolar NPN transistors if there is takes place. For this, a layer of resin is deposited and etched which masks the areas which must not undergo P + type implantation, namely all of the N channel MOS transistors, high or low voltage, and the well d access 18 of the NPN transistor collector. For P-channel MOS transistors not masked by the resin, it is the thick oxide regions and the polycrystalline silicon grids which serve as a mask delimiting precisely the implanted regions of type P +. The implantation is carried out for example with boron.

Ces régions de type P+ sont respectivement (figure 8) :

  • - des régions 36, constituant le drain de transistors MOS basse tension à canal P, implantées directement dans la couche épitaxiale 16 de type N entre une grille 31 et une région d'oxyde épais 30.
  • - des régions 38 constituant la source de ces mêmes transistors, également implantées dans la couche épitaxiale de type N entre une grille 31 et de l'oxyde épais 30 ;
  • - des régions 40 constituant le drain de transistors MOS haute tension à canal P ; ces régions 40 sont implantées à l'intérieur des régions 24 de type P , et sont moins profondes qu'elles ; on notera d'autre part qu'une distance relativement importante, mais quand même inférieure à la profondeur de la région 24, sépare le bord de la région 40 (du côté du canal) de la région de canal 42 proprement dite ; ce qu'on appelle ici région de canal 42 est la région de type N qui est recouverte par la grille de transistor ou plus précisément par la portion de grille qui n'est séparée de la surface semiconductrice que par une couche d'oxyde mince 32 et qui peut donc contrôler directement la formation d'un canal.
  • - des régions 44 constituant la source des transistors MOS haute tension à canal P ; ces régions sont implantées dans la couche épitaxiale entre la grille 35 et une zone d'oxyde épais,
  • - éventuellement des régions 46 constituant la base des transistors bipolaires NPN.
These P + type regions are respectively (Figure 8):
  • regions 36 constituting the drain of low voltage P channel MOS transistors, located directly in the N type epitaxial layer 16 between a gate 31 and a thick oxide region 30.
  • - Regions 38 constituting the source of these same transistors, also located in the N-type epitaxial layer between a grid 31 and thick oxide 30;
  • - Regions 40 constituting the drain of P-channel high voltage MOS transistors; these regions 40 are located inside the P-type regions 24, and are shallower than them; it will be noted on the other hand that a relatively large distance, but still less than the depth of the region 24, separates the edge of the region 40 (on the channel side) from the channel region 42 proper; what is called here channel region 42 is the N type region which is covered by the transistor gate or more precisely by the gate portion which is not separated from the semiconductor surface only by a thin oxide layer 32 and which can therefore directly control the formation of a channel.
  • - Regions 44 constituting the source of high voltage P channel MOS transistors; these regions are located in the epitaxial layer between the grid 35 and a thick oxide zone,
  • - possibly regions 46 constituting the base of the NPN bipolar transistors.

On élimine alors la résine de masquage utilisée pendant l'implantation de type P+ et l'on effectue un recuit. On dépose et on grave une autre couche de résine en vue d'une implantation (ou diffusion) de type N+ ; cette couche de résine masque les transistors qui ne doivent pas subir cette implantation, à savoir les transistors MOS à canal P (basse tension ou haute tension) et la région de base des transistors NPN. Pour les transistors non masqués, l'oxyde épais 30 et les régions de silicium polycristallin servent de masque délimitant précisément les régions implantées de type N+ ; l'implantation peut être effectuée avec de l'arsenic ; une diffusion d'arsenic en ampoule est aussi possible.The masking resin used during the P + type implantation is then eliminated and annealing is carried out. Another layer of resin is deposited and etched for implantation (or diffusion) of the N + type; this resin layer masks the transistors which must not undergo this implantation, namely the P-channel MOS transistors (low voltage or high voltage) and the base region of the NPN transistors. For unmasked transistors, the thick oxide 30 and the polycrystalline silicon regions serve as a mask precisely delimiting the implanted regions of N + type; implantation can be performed with arsenic; Diffusion of arsenic in ampoule is also possible.

Ces régions de type N+ sont moins profondes que les régions de type P+ et sont respectivement (figure 8)

  • - des régions 48 de drain des transistors MOS basse tension à canal N, implantées dans la région 20 de type P- entre une grille 29 et une zone d'oxyde épais ;
  • - des régions 50 de source de ces transistors, également implantées dans la région 20 entre une grille 29 et une zone d'oxyde épais ;
  • - des régions 52 de drain des transistors MOS haute tension à canal N, implantées directement dans la couche épitaxiale originelle de type N ; ces régions sont espacées, d'une distance relativement importante mais inférieure à l'épaisseur de la coucxhe épitaxiale, de la région de canal proprement dite 54 de ces transistors, c'est-à-dire de la région de type P- directement recouverte (à travers de l'oxyde mince 32) par une grille de silicium polycristallin 33. Sur cette distance, la couche épitaxiale est surmontée d'une zone d'oxyde épais 30. Dans ces conditions, les régions 52 sont entièrement délimitées par de l'oxyde épais 30.
  • - des régions 56 diffusées dans les régions 22 et constituant les régions de source de transistors MOS haute tension à canal N, l'espace entre le bord d'une région 56 et le bord de la région 22 dans laquelle elle se trouve constituant la région de canal 54 de ces transistors ; les régions 56 sont délimitées par les grilles 33 et des zones d'oxyde épais 30.
  • - éventuellement des régions 58 constituant l'émetteur de transistors bipolaires NPN verticaux, ces régions étant diffusées à l'intérieur des régions de base 46. Le puits d'accès 18 à la couche enterrée peut également subir cette opération d'implantation peu profonde de type N+.
These N + type regions are shallower than the P + type regions and are respectively (Figure 8)
  • - drain regions 48 of low-voltage N-channel MOS transistors, located in the P-type region 20 - between a gate 29 and a thick oxide zone;
  • - Source regions 50 of these transistors, also located in region 20 between a gate 29 and a thick oxide zone;
  • - drain regions 52 of the N-channel high voltage MOS transistors, located directly in the original N-type epitaxial layer; these regions are spaced, by a relatively large distance but less than the thickness of the epitaxial layer, from the channel region proper 54 of these transistors, that is to say from the P-type region - directly covered (through thin oxide 32) by a polycrystalline silicon grid 33. On this distance, the epitaxial layer is surmounted by a zone of thick oxide 30. Under these conditions, the regions 52 are entirely delimited by thick oxide 30.
  • - Regions 56 diffused in regions 22 and constituting the source regions of N-channel high voltage MOS transistors, the space between the edge of a region 56 and the edge of region 22 in which it is found constituting the region channel 54 of these transistors; the regions 56 are delimited by the grids 33 and thick oxide zones 30.
  • - Possibly regions 58 constituting the emitter of vertical NPN bipolar transistors, these regions being diffused inside the base regions 46. The access well 18 to the buried layer can also undergo this shallow implantation operation of type N + .

Le procédé de fabrication se termine par des étapes classiques non représentées qui sont : un dépôt en phase gazeuse d'une couche isolante d'oxyde de silicium, un fluage de cette couche, une gravure pour ouvrir des contacts, un dépôt métallique (aluminium), une gravure de l'aluminium pour définir un motif d'interconnexions, un dépôt d'une couche isolante de passivation, une gravure de plots de contact pour la connexion aux broches du boîtier, et une encapsu- lation.The manufacturing process ends with conventional steps, not shown, which are: a gas phase deposition of an insulating layer of silicon oxide, a creep of this layer, an etching to open contacts, a metallic deposit (aluminum) , etching of aluminum to define an interconnection pattern, deposition of an insulating passivation layer, etching of contact pads for connection to the pins of the housing, and encapsulation.

Dans l'exemple de réalisation qui a été décrit, les caissons 20 de type P- contenant les transistors MOS basse tension à canal N sont séparés du substrat par une épaisseur de couche épitaxiale de type N. Cependant, on pourrait prévoir qu'une zone 14 de type P a été diffusée avant la croissance épitaxiale à l'endroit du caisson, de sorte que cette zone remonte ensuite jusqu'au caisson qui constitue alors à la fois un caisson de MOS N basse tension et un mur d'isolement. En reliant ainsi le caisson au substrat, on évite l'apparition d'un phénomène de "latch up", c'est-à-dire la formation d'un thyristor parasite NPNP.In the embodiment which has been described, the P-type wells 20 - containing the low-voltage N-channel MOS transistors are separated from the substrate by a thickness of the N-type epitaxial layer. However, one could provide that an area Type P 14 was diffused before the epitaxial growth at the location of the caisson, so that this zone then rises to the caisson which then constitutes both a low voltage MOS N caisson and an isolation wall. By thus connecting the box to the substrate, the appearance of a "latch up" phenomenon, that is to say the formation of a parasitic NPNP thyristor, is avoided.

Le procédé qui a été décrit est parfaitement compatible avec la formation de transistors bipolaires PNP latéraux (émetteur et collecteur formés en même temps que le drain des transistors MOS à canal P, base formée par la couche épitaxiale).The process which has been described is perfectly compatible with the formation of lateral PNP bipolar transistors (transmitter and collector formed at the same time as the drain of the P channel MOS transistors, base formed by the epitaxial layer).

Enfin, on peut envisager de réaliser, si le substrat de départ est de type N+, un élément de puissance qui serait ce qu'on appelle un DMOS vertical, c'est-à-dire un MOS à canal N diffusé dont le drain est constitué par la face arrière N du substrat, la source est constituée par des zones N+ comme les sources des transistors MOS basse tension à canal N, et la région de canal est diffusée localement avec la diffusion de caisson de type P- des transistors MOS basse tension à canal N.Finally, it is possible to envisage making, if the starting substrate is of the N + type, a power element which would be what is called a vertical DMOS, that is to say a MOS with N channel broadcast whose drain consists of the rear side N of the substrate, the source consists of N + zones like the sources of the low-voltage N-channel MOS transistors, and the channel region is locally diffused with the diffusion of P-type wells - transistors N-channel low voltage MOS

Claims (3)

1. Structure de circuit intégré incorporant des transistors MOS basse tension à canal N et à canal P et des transistors MOS haute tension à canal N et à canal P, comprenant : - une pastille semiconductrice constituée d'un substrat (10) recouvert d'une couche épitaxiale (16) peu dopée de type N ; - des première régions (20) de type P-, peu dopées, s'étendant à partir de la surface de la pastille semiconductrice sur une partie de la profondeur de la couche épitaxiale, ces régions (20) constituant des caissons dans lesquels sont formés la source, le drain et le canal de transistors MOS basse tension à canal N ; - des réglons de type P+ fortement dopées (36, 38, 40, 44), moins profondes que les régions de type P-, s'étendant à partir de la surface de la pastille semiconductrice et constituant la source et le drain des transistors MOS à canal P ; - des régions de type N+ fortement dopées (48, 50, 52, 56), moins profondes que les régions de type P-, s'étendant à partir de la surface de la pastille semiconductrice et constituant la source et le drain des transistors MOS à canal N,
caractérisée en ce qu'il est prévu en outre - au moins une seconde région (22) de type P-, de même profil de concentration que les premières régions et s'étendant jusqu'à la même profondeur, cette seconde région entourant une région de source (56) de type N+ et constituant une région de canal (54) d'un transistor MOS haute tension à canal N, transistor qui comporte par ailleurs une région de drain (52) de type N+ située en dehors de la seconde région (22) et écartée d'elle de telle manière qu'il existe une zone de couche épitaxiale de type N peu dopée, non directement contrôlée par la grille du transistor, entre la région de drain et la seconde région (22), - au moins une troisième région (24) de type P-, de même profil de concentration des première et secondes régions et s'étendant jusqu'à la mêmf profondeur, cette troisième région entourant une région de drain (40) de type P d'un transistor MOS haute tension à canal P dont la région de canal est constituée par une région (42) de couche épitaxiale de type N peu dopée, adjacente à la troisième région (24), la région de drain (40) de type P+ de ce transistor étant écartée de la région de canal (42) de telle manière qu'il existe entre elles une zone de la troisième région (24) non directement contrôlée par la grille (35) du transistor, et la région de source (40) de ce transistor étant située en dehors de la troisième région. 1. Integrated circuit structure incorporating low-voltage N-channel and P-channel MOS transistors and high-voltage N-channel and P-channel MOS transistors, comprising: - a semiconductor wafer consisting of a substrate (10) covered with an epitaxial layer (16) lightly doped with type N; - first regions (20) P - -type, no doped, extending from the surface of the semiconductor wafer over a part of the depth of the epitaxial layer, these regions (20) forming chambers which are formed in the source, the drain and the channel of N-channel low voltage MOS transistors; - highly doped P + type regions (36, 38, 40, 44), less deep than the P type regions - , extending from the surface of the semiconductor patch and constituting the source and the drain of the transistors P channel MOS; - heavily doped N + type regions (48, 50, 52, 56), less deep than the P type regions - , extending from the surface of the semiconductor wafer and constituting the source and the drain of the transistors N-channel MOS,
characterized in that it is further provided - at least one second region (22) P - -type, the same concentration profile as the first regions and extending to the same depth, this second region surrounding a source region (56) of N + type and constituting a channel region (54) of an N-channel high voltage MOS transistor, transistor which moreover comprises an N + type drain region (52) located outside the second region (22) and separated from it in such a way that there is a slightly doped N-type epitaxial layer zone, not directly controlled by the gate of the transistor, between the drain region and the second region (22), - at least a third region (24) of type P - , with the same concentration profile of the first and second regions and extending to the same depth, this third region surrounding a P-type drain region (40) of a P-channel high voltage MOS transistor, the channel region of which is a region (42) of lightly doped N-type epitaxial layer, adjacent to the third region (24 ), the P + type drain region (40) of this transistor being spaced from the channel region (42) in such a way that there exists between them a zone of the third region (24) not directly controlled by the gate (35) of the transistor, and the source region (40) of this transistor being located outside the third region. 2. Structure selon la revendication 1, caractérisée en ce qu'elle comporte des murs d'isolement de type P traversant la couche épitaxiale du haut en bas, la partie supérieure de ces murs étant constituée par des régions (26) de type P" formées par la même opération que les premières, secondes et troisièmes régions.2. Structure according to claim 1, characterized in that it comprises type P isolation walls crossing the epitaxial layer from top to bottom, the upper part of these walls being constituted by P type regions (26). formed by the same operation as the first, second and third regions. 3. Procédé de fabrication de circuits intégrés incorporant des transistors MOS à canal N et à canal P dont certains ont une tenue en tension améliorée, caractérisé en ce que a) on effectue une implantation ionique localisée d'impuretés de type P à faible concentration dans une couche épitaxiale peu dopée de type N, simultanément dans des régions qui sont - des première régions (20) constituant des caissons destinés à enfermer source (50), drain (48) et canal de certains transistors MOS à canal N dits transistors MOS N basse tension ; - des secondes régions (22) destinées à enfermer uniquement la source (56) et le canal (54) de transistors MOS à canal N dits transistors MOS N haute tension ; - des troisièmes régions (24) destinées à enfermer uniquement le drain (40) de transistors MOS à canal P dits transistors MOS P haute tension ; b) on forme et on grave une couche d'oxyde mince (32) surmontée d'une couche de silicium polycristallin (34) pour former : - des grilles passant à l'intérieur des premières régions en permettant la formation dans ces régions d'une zone de source (50) et d'une zone de drain (48) de part et d'autre de la grille ; - des grilles venant à cheval sur la frontière entre une deuxième région (22) de type P et la couche épitaxiale (16) de type N, en permettant la formation d'une zone de source (56) dans la deuxième région d'un côté de la grille, d'une zone de drain (52) dans la couche épitaxiale de l'autre côté de la grille, et d'une zone de canal (54) sous la grille dans la deuxième région ; - des grilles venant à cheval sur la frontière entre une troisième région (24) de type P- et la couche épitaxiale (16) de type N, en permettant la formation d'une zone de source (44) dans la couche épitaxiale d'un côté de la grille, d'une zone de drain (40) dans la troisième région de l'autre côté de la grille, et d'une zone de canal (42) dans la couche épitaxiale sous la grille; c) on implante localement d'une part une impureté de type P et d'autre part une impureté de type N pour former des régions (36, 38, 40, 44) de type P+ constituant la source et le drain des transistors à canal P et des régions (48, 50 52, 56) de type N+ constituant la source et le drain des transistors à canal N, les régions de drain des transistors MOS haute tension étant écartées latéralement des régions contrôlées par la grille de ces transistors. 3. Method for manufacturing integrated circuits incorporating N-channel and P-channel MOS transistors, some of which have improved voltage withstand, characterized in that a) a localized ion implantation of P-type impurities at low concentration is carried out in a lightly doped N-type epitaxial layer, simultaneously in regions which are - First regions (20) constituting boxes intended to enclose source (50), drain (48) and channel of certain N channel MOS transistors called low voltage MOS N transistors; - second regions (22) intended to enclose only the source (56) and the channel (54) of N-channel MOS transistors called high-voltage MOS N transistors; - third regions (24) intended to enclose only the drain (40) of P channel MOS transistors called high voltage MOS P transistors; b) a thin oxide layer (32) surmounted by a layer of polycrystalline silicon (34) is formed and etched to form: - grids passing inside the first regions allowing the formation in these regions of a source zone (50) and a drain zone (48) on either side of the grid; - grids straddling the border between a second P-type region (22) and the N-type epitaxial layer (16), allowing the formation of a source zone (56) in the second region of a side of the grid, a drain zone (52) in the epitaxial layer on the other side of the grid, and a channel zone (54) under the grid in the second region; - grids straddling the border between a third region (24) of type P - and the epitaxial layer (16) of type N, allowing the formation of a source zone (44) in the epitaxial layer of one side of the grid, a drain zone (40) in the third region on the other side of the grid, and a channel zone (42) in the epitaxial layer under the grid; c) a P type impurity is implanted locally on the one hand and an N type impurity on the other hand to form P + type regions (36, 38, 40, 44) constituting the source and the drain of the transistors at P channel and N + type regions (48, 50 52, 56) constituting the source and the drain of the N channel transistors, the drain regions of the high voltage MOS transistors being separated laterally from the regions controlled by the gate of these transistors .
EP85401860A 1984-09-28 1985-09-24 Integrated-circuit structure containing high-voltage cmos transistors and method of making the same Expired EP0179693B1 (en)

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0295391A1 (en) * 1987-04-24 1988-12-21 Power Integrations, Inc. High voltage MOS transistors
EP0296997A1 (en) * 1987-06-22 1988-12-28 STMicroelectronics S.A. Power mos transistors structure
FR2620570A1 (en) * 1987-09-15 1989-03-17 Samsung Semiconductor Tele METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE "BICMOS"
EP0314226A2 (en) * 1987-10-30 1989-05-03 STMicroelectronics S.r.l. Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it
EP0319047A2 (en) * 1987-12-04 1989-06-07 Nissan Motor Co., Ltd. Power integrated circuit
WO1990007794A1 (en) * 1988-12-23 1990-07-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. High-voltage transistor arrangement produced by cmos technology
EP0388329A1 (en) * 1989-03-15 1990-09-19 STMicroelectronics S.A. Driver circuit of a power MOS transistor with inductive load
EP0387999A2 (en) * 1989-03-17 1990-09-19 Delco Electronics Corporation Process for forming high-voltage and low-voltage CMOS transistors on a single integrated circuit chip
EP0388000A2 (en) * 1989-03-17 1990-09-19 Delco Electronics Corporation Process for forming vertical bipolar transistors and high-voltage CMOS in a single integrated circuit chip
EP0401135A1 (en) * 1989-06-02 1990-12-05 Sgs Thomson Microelectronics Sa Method of fabricating simultaneous of N-channel MOS transistors and vertical bipolar PNP transistors
EP0403449A2 (en) * 1989-06-14 1990-12-19 STMicroelectronics S.r.l. Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
FR2675311A1 (en) * 1991-04-09 1992-10-16 Samsung Electronics Co Ltd Semiconductor device of the bicmos type for integrated circuits and its method of fabrication
USRE37424E1 (en) * 1989-06-14 2001-10-30 Stmicroelectronics S.R.L. Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
US6869847B2 (en) 2001-08-30 2005-03-22 Sony Corporation Semiconductor device manufacturing method thereof

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
JPH0695563B2 (en) * 1985-02-01 1994-11-24 株式会社日立製作所 Semiconductor device
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
JPS61111576A (en) * 1984-10-13 1986-05-29 Fujitsu Ltd Semiconductor device
JPH0652792B2 (en) * 1985-02-26 1994-07-06 日産自動車株式会社 Semiconductor device
JPH0793383B2 (en) * 1985-11-15 1995-10-09 株式会社日立製作所 Semiconductor device
US5264719A (en) * 1986-01-07 1993-11-23 Harris Corporation High voltage lateral semiconductor device
IT1188465B (en) * 1986-03-27 1988-01-14 Sgs Microelettronica Spa PROCEDURE FOR THE MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING CMOS DEVICES AND HIGH VOLTAGE ELECTRONIC DEVICES
JPH0812918B2 (en) * 1986-03-28 1996-02-07 株式会社東芝 Method for manufacturing semiconductor device
JP2635961B2 (en) * 1986-09-26 1997-07-30 株式会社日立製作所 Method for manufacturing semiconductor device
IT1218128B (en) * 1987-03-05 1990-04-12 Sgs Microelettronica Spa INTEGRATED STRUCTURE FOR SIGNAL TRANSFER NETWORK, ESPECIALLY FOR PILOT CIRCUIT FOR POWER MOS TRANSISTORS
US4866495A (en) * 1987-05-27 1989-09-12 International Rectifier Corporation High power MOSFET and integrated control circuit therefor for high-side switch application
US5023678A (en) * 1987-05-27 1991-06-11 International Rectifier Corporation High power MOSFET and integrated control circuit therefor for high-side switch application
US4994887A (en) * 1987-11-13 1991-02-19 Texas Instruments Incorporated High voltage merged bipolar/CMOS technology
US5014097A (en) * 1987-12-24 1991-05-07 Waferscale Integration, Inc. On-chip high voltage generator and regulator in an integrated circuit
US4980746A (en) * 1988-04-29 1990-12-25 Dallas Semiconductor Corporation Integrated circuit with improved battery protection
KR910009739B1 (en) * 1988-07-13 1991-11-29 삼성전자 주식회사 Manufacturing method of semiconductor device
US4914051A (en) * 1988-12-09 1990-04-03 Sprague Electric Company Method for making a vertical power DMOS transistor with small signal bipolar transistors
DE3936668A1 (en) * 1988-12-23 1990-06-28 Fraunhofer Ges Forschung High voltage CMOS transistor arrangement - has source zone of substrate-opposed type directly surrounded by substrate
US5041896A (en) * 1989-07-06 1991-08-20 General Electric Company Symmetrical blocking high voltage semiconductor device and method of fabrication
US5045492A (en) * 1989-09-25 1991-09-03 Allegro Microsystems, Inc. Method of making integrated circuit with high current transistor and CMOS transistors
JPH06103745B2 (en) * 1989-10-06 1994-12-14 株式会社東芝 Integrated circuit element
JPH0824146B2 (en) * 1989-10-19 1996-03-06 株式会社東芝 MOS integrated circuit
US5229308A (en) * 1990-04-30 1993-07-20 Xerox Corporation Bipolar transistors with high voltage MOS transistors in a single substrate
US5442191A (en) * 1990-09-05 1995-08-15 Yale University Isotopically enriched semiconductor devices
US5144409A (en) * 1990-09-05 1992-09-01 Yale University Isotopically enriched semiconductor devices
IT1250406B (en) * 1991-02-07 1995-04-07 Sgs Thomson Microelectronics HIGH VOLTAGE CMOS LOGIC CIRCUIT WITH LOGIC PORTS CONFIGURED NAND AND REDUCED NUMBER OF N-MOS TRANSISTORS REQUIRING A GRADUATED DIFFUSION LIMITED TO DRAIN ONLY
JPH04320368A (en) * 1991-04-19 1992-11-11 Sanyo Electric Co Ltd Semiconductor device
JPH05267604A (en) * 1991-05-08 1993-10-15 Seiko Instr Inc Manufacture of semiconductor device
JP2861624B2 (en) * 1992-05-13 1999-02-24 日本電気株式会社 Method for manufacturing semiconductor device
US5282107A (en) * 1992-09-01 1994-01-25 Power Integrations, Inc. Power MOSFET safe operating area current limiting device
US5648281A (en) * 1992-09-21 1997-07-15 Siliconix Incorporated Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate
US5374569A (en) * 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
US5559044A (en) * 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
DE69307121T2 (en) * 1993-02-24 1997-04-17 Sgs Thomson Microelectronics Completely depleted lateral transistor
EP0613181A1 (en) * 1993-02-26 1994-08-31 STMicroelectronics S.r.l. Bipolar transistor compatible with CMOS processes
JPH10189762A (en) 1996-12-20 1998-07-21 Nec Corp Semiconductor device and its manufacturing method
JP3527094B2 (en) * 1998-04-03 2004-05-17 Ｎｅｃエレクトロニクス株式会社 Active XY address type solid-state imaging device
US6534829B2 (en) * 1998-06-25 2003-03-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6214675B1 (en) * 1999-02-08 2001-04-10 Lucent Technologies Inc. Method for fabricating a merged integrated circuit device
US6743679B2 (en) 1999-03-03 2004-06-01 Koninklijke Philips Electronics N.V. Integrated circuit devices with high and low voltage components and processes for manufacturing these devices
SE523899C2 (en) * 1999-04-15 2004-06-01 Ericsson Telefon Ab L M semiconductor device
KR100350648B1 (en) * 2000-01-17 2002-08-28 페어차일드코리아반도체 주식회사 Mos transistor and method for manufacturing the same
US6818494B1 (en) 2001-03-26 2004-11-16 Hewlett-Packard Development Company, L.P. LDMOS and CMOS integrated circuit and method of making
JP4811895B2 (en) * 2001-05-02 2011-11-09 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4166010B2 (en) * 2001-12-04 2008-10-15 富士電機デバイステクノロジー株式会社 Horizontal high voltage MOSFET and semiconductor device having the same
JP2003197792A (en) * 2001-12-28 2003-07-11 Sanyo Electric Co Ltd Semiconductor device
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US7781843B1 (en) 2007-01-11 2010-08-24 Hewlett-Packard Development Company, L.P. Integrating high-voltage CMOS devices with low-voltage CMOS
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2449334A1 (en) * 1979-02-15 1980-09-12 Texas Instruments Inc METHOD FOR MONOLITHIC INTEGRATION OF HIGH-PERFORMANCE LOGIC, CONTROL AND INTERFACE CIRCUITS
EP0020164A1 (en) * 1979-05-30 1980-12-10 Xerox Corporation Monolithic HVMOSFET array
FR2464561A1 (en) * 1979-08-31 1981-03-06 Thomson Csf Complementary MOSFET structure handling large voltage - has each transistor enclosed by n-type epitaxial pocket reducing parasitic bipolar transistor gain
US4300150A (en) * 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
EP0070101A1 (en) * 1981-07-06 1983-01-19 Xerox Corporation Mos transistors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216455A (en) * 1982-06-09 1983-12-16 Toshiba Corp Manufacture of semiconductor device
JPS5947757A (en) * 1982-09-10 1984-03-17 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2449334A1 (en) * 1979-02-15 1980-09-12 Texas Instruments Inc METHOD FOR MONOLITHIC INTEGRATION OF HIGH-PERFORMANCE LOGIC, CONTROL AND INTERFACE CIRCUITS
EP0020164A1 (en) * 1979-05-30 1980-12-10 Xerox Corporation Monolithic HVMOSFET array
FR2464561A1 (en) * 1979-08-31 1981-03-06 Thomson Csf Complementary MOSFET structure handling large voltage - has each transistor enclosed by n-type epitaxial pocket reducing parasitic bipolar transistor gain
US4300150A (en) * 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
EP0070101A1 (en) * 1981-07-06 1983-01-19 Xerox Corporation Mos transistors

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
INTERNATIONAL ELECTRON DEVICES MEETING 1982, 13-15 décembre 1982, pages 77-80, San Francisco, US; V. RUMENNIK et al.: "Integrated high and low voltage CMOS technology" *

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0295391A1 (en) * 1987-04-24 1988-12-21 Power Integrations, Inc. High voltage MOS transistors
EP0296997A1 (en) * 1987-06-22 1988-12-28 STMicroelectronics S.A. Power mos transistors structure
FR2620570A1 (en) * 1987-09-15 1989-03-17 Samsung Semiconductor Tele METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE "BICMOS"
NL8802282A (en) * 1987-09-15 1989-04-03 Samsung Electronics Co Ltd METHOD FOR MANUFACTURING A BICMOS SEMICONDUCTOR DEVICE
EP0314226A2 (en) * 1987-10-30 1989-05-03 STMicroelectronics S.r.l. Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it
EP0314226A3 (en) * 1987-10-30 1989-11-15 STMicroelectronics S.r.l. Integrated structure with active and passive components enclosed in insulating pockets and operating at higher than the breakdown voltage between each component and the pocket containing it
EP0319047A2 (en) * 1987-12-04 1989-06-07 Nissan Motor Co., Ltd. Power integrated circuit
EP0319047A3 (en) * 1987-12-04 1992-07-08 Nissan Motor Co., Ltd. Power integrated circuit
WO1990007794A1 (en) * 1988-12-23 1990-07-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. High-voltage transistor arrangement produced by cmos technology
FR2644651A1 (en) * 1989-03-15 1990-09-21 Sgs Thomson Microelectronics INDUCTIVE LOAD POWER MOS TRANSISTOR CONTROL CIRCUIT
EP0388329A1 (en) * 1989-03-15 1990-09-19 STMicroelectronics S.A. Driver circuit of a power MOS transistor with inductive load
EP0388000A2 (en) * 1989-03-17 1990-09-19 Delco Electronics Corporation Process for forming vertical bipolar transistors and high-voltage CMOS in a single integrated circuit chip
EP0388000A3 (en) * 1989-03-17 1991-03-27 Delco Electronics Corporation Process for forming vertical bipolar transistors and high-voltage cmos in a single integrated circuit chip
EP0387999A2 (en) * 1989-03-17 1990-09-19 Delco Electronics Corporation Process for forming high-voltage and low-voltage CMOS transistors on a single integrated circuit chip
EP0387999A3 (en) * 1989-03-17 1992-07-29 Delco Electronics Corporation Process for forming high-voltage and low-voltage cmos transistors on a single integrated circuit chip
EP0401135A1 (en) * 1989-06-02 1990-12-05 Sgs Thomson Microelectronics Sa Method of fabricating simultaneous of N-channel MOS transistors and vertical bipolar PNP transistors
FR2647959A1 (en) * 1989-06-02 1990-12-07 Sgs Thomson Microelectronics METHOD FOR THE SIMULTANEOUS MANUFACTURE OF N-CHANNEL MOS TRANSISTORS AND PNP VERTICAL BIPOLAR TRANSISTORS
EP0403449A2 (en) * 1989-06-14 1990-12-19 STMicroelectronics S.r.l. Mixed technology intergrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
EP0403449A3 (en) * 1989-06-14 1992-07-08 STMicroelectronics S.r.l. Mixed technology intergrated device comprising complementary ldmos power transistors, cmos and vertical pnp integrated structures having an enhanced ability to withstand a relatively high supply voltage
USRE37424E1 (en) * 1989-06-14 2001-10-30 Stmicroelectronics S.R.L. Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage
FR2675311A1 (en) * 1991-04-09 1992-10-16 Samsung Electronics Co Ltd Semiconductor device of the bicmos type for integrated circuits and its method of fabrication
US6869847B2 (en) 2001-08-30 2005-03-22 Sony Corporation Semiconductor device manufacturing method thereof
US7122861B2 (en) 2001-08-30 2006-10-17 Sony Corporation Semiconductor device and manufacturing method thereof

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ATE45443T1 (en) 1989-08-15
EP0179693B1 (en) 1989-08-09
FR2571178B1 (en) 1986-11-21
US4628341A (en) 1986-12-09
DE3572260D1 (en) 1989-09-14
FR2571178A1 (en) 1986-04-04
JPS6188553A (en) 1986-05-06

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