EP0419260A2 - Electrically erasable and programmable non-volatile semiconductor memory device - Google Patents
Electrically erasable and programmable non-volatile semiconductor memory device Download PDFInfo
- Publication number
- EP0419260A2 EP0419260A2 EP90310303A EP90310303A EP0419260A2 EP 0419260 A2 EP0419260 A2 EP 0419260A2 EP 90310303 A EP90310303 A EP 90310303A EP 90310303 A EP90310303 A EP 90310303A EP 0419260 A2 EP0419260 A2 EP 0419260A2
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- European Patent Office
- Prior art keywords
- circuit
- output
- nmos
- volatile semiconductor
- electrically erasable
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Definitions
- the present invention relates to a semiconductor memory device and more particularly to an electrically erasable and programmable non-volatile memory device, namely, an electrically erasable and programmable read only memory, called an EEPROM hereinafter.
- an EEPROM receives a chip enable signal CE , an output enable signal OE or a write enable signal WE as a control signal and determines various modes for waiting, erasing, writing or reading based on the logical state of those signals.
- these control signals CE , OE and WE are apt to be affected by variations in power source voltage or noise, and their logical states are made wrong by the variations in power source voltage or noise.
- a writing mode is incidentally set and error data is written, thereby resulting in an error writing operation.
- Such error writing can be avoided by providing a so-called software data protection circuit within the memory device.
- the EEPROM comprises a row-decoder 1, a cell matrix 2, a read column decoder 3, a read column gate 4, a sense amplifier 5, an I/0 buffer 6, an E / W (erase/write) column decoder 7, an EfW column gate 8 and a page register 9. It further comprises a control signal logic circuit 10, an E/W timing signal generating circuit 11, an increased voltage generating circuit 12, and a software data protection circuit 13.
- the chip enable signal CE , the output enable signal OE and the write enable signal WE are put in the state shown in the following table 1, thereby enabling the EEPROM to be set in the write mode.
- the write address is obtained at the fall of the write enable signal WE and the write data is got at the rise of the write enable signal WE .
- the software data protection circuit 13 is for preventing an error write caused as described above.
- Software data protection circuit 13 has an EEPROM cell 13A, which sets a software data protection circuit 13 to prevent the data from being written in respective memory cells in cell matrix 2 by setting storing and maintaining a discretional logic value in EEPROM cell 13A.
- An address signal of 16 bits comprising, for example, the row-address and column- address input to matrix 2 and the data output from I / 0 buffer 6,are input to the software data protection circuit 13.
- the software data protection is set by sequentially providing the address and the data to the software data protection circuit 13.
- the software data protection state when the software data protection state is set, data is not written in cell matrix 2 if an address and data for setting the software data protection is not input to EEPROM cell 13A.
- the software data protection state is set, the write operation is performed for EEPROM cell 13A whenever the data is written into cell matrix 2.
- write mode When write mode is set, write operation is not performed to all the EEPROM cells performing cell matrix 2. Namely, when the setting and releasing operation of software data protection are frequently performed, the writing operation for EEPROM in software data protection circuit 13 is performed more than that for the writing operation for the discretional EEPROM cell 13A.
- a write operation is not carried out for all the EEPROM cells forming a cell matrix 2. Namely, the number of a write operation by which data is written in EEPROM 13A in software data protection circuit 13 is sometimes larger than that of a write operation by which data is written in a discretional EEPROM cell forming cell matrix 2.
- An object of the present invention is to provide EEPROM of capable of decreasing the deterioration of the EEPROM cell forming the software data protection circuit so that EEPROM cell can maintain function or in longer period of time.
- the EEPROM is equipped with a software data processing circuit having an EEPROM cell.
- the software data protection circuit can memorize and maintain the software data protection setting state by setting the EEPROM cell to one logic state, for example, logic "0" (conductive state) where it receives the address and data for setting the software data protection and memorize and maintain the software data protection releasing state by setting the EEPROM cell to be in the other logic state, for example, logic "1" (nonconductive state) where it receives an address and data for removing the software data protection.
- the first invention provides the logic state setting control means for controlling the logic state setting operation of the EEPROM cell so that, where the EEPROM cell is set to be in one logic state, for example, logic "0", one logic state, namely, the state of logic "0" is not repeatedly set in the EEPROM, even if the address and data for setting the software data protection is received.
- An increase voltage for setting one logic state "0" is not supplied to a drain or source of EEPROM cell therefore the increase voltage for software data protection is prevented from being applied to the EEPROM cell and the EEPROM cell for forming the software data protection circuit is prevented from being deteriorated largely.
- the second invention further provides a logic state setting control circuit for controlling the logic state setting operation of the EEPROM cell so that, where the EEPROM cell is already set in the other logic state, namely, logic "1", the other logic state, namely the state of logic "1 " is not repeatedly set, even if the address and data for removing the software data protection is input.
- the second invention in addition to the setting of the software data protection, the unnecessary increase voltage is prevented from being applied to EEPROM upon the release of the data protection and thus the second invention can prevent the deterioration of the EEPROM cell for a longer period time than the first invention.
- FIG 3 shows a block diagram designating one embodiment of the present invention.
- EEPROM of the present invention provides the software data protection circuit 14 with detail circuit shown in Figure 4, in place of software data protection circuit 13 shown in Figure 1 as a prior art and the other part of EEPROM shown in Figure 1 is formed in the same manner as the prior art EEPROM shown in Figure 1. Therefore, the same block as that shown in Figure 1 is designated by the same reference number as Figure 1 and the explanation of the block is abbreviated.
- FIG 4 shows an example of increased voltage generating circuit 12 in the above recited software data protection circuit 14.
- increased voltage generating circuit 12 comprises voltage increase circuit clock signal generating circuit 15 and voltage increasing circuit 16.
- Voltage increase circuit clock signal generating circuit 15 comprises a ring oscillator 22 comprising NAND circuit 17, and inverters 18, 19, 20 and 21 , and buffer inverters 23 and 24.
- NAND circuit 17 and inverters 18, 19, 20 and 21 are connected in series and the output terminal of the inverter 21 is connected to one input terminal of NAND circuit 17, thereby forming a ring oscillator 22.
- the increased voltage generating control signal VPACT is input to the other input terminal of NAND circuit 17 and when increased voltage generating control signal VPACT is at a high level "H", ring oscillator 22 performs an oscillation operation.
- Inverters 21, 23 and 24 are connected in series and voltage increase circuit clock signal CLK and CLK are respectively output from the output terminals of the inverters 23 and 24.
- nMOS 25 has drain and gate connected to power source line 29 to which power source voltage VCC (5V) is applied and its source connected to the drain and gate of nMOS 26-1.
- nMOS 26-1 has its source connected a drain and gate of nMOS 26-2. The same connection is made from nMOS 26-1 to nMOS 26-n.
- the source of nMOS 26-n is connected to increased voltage outputting terminal 28.
- a connecting point between a drain of nMOS 26-1 and gate thereof, a connecting point between a drain of nMOS 26-3 (not shown) and a gate thereof, ... and a connecting point between a drain of nMOS 26-n-1 and a gate thereof are connected to an output terminal of inverter 23 of voltage increased circuit clock signal generating circuit 15 through capacitors 27-1, 27-3...27-n-1, respectively.
- a connecting point between a drain and a gate of nMOS 26-2, a connecting point between a drain and a gate of nMOS 26-n are connected to the output terminal of the inverter 24 of increased voltage circuit clock signal generating circuit 15 through capacitors 27-2...27-n.
- capacitors 27-1, 27-2...27-n are charged up when voltage increased circuit clock signal CLK and CLK are applied thereto and the voltages on the side of nMOS 26-1, 26-2...26-n are sequentially increased.
- the increased voltage VPP of 20V for example, can be obtained at increased voltage output terminal 28.
- Software data protection circuit 14 comprises logic circuit 30, write erase control circuit 31, write erase circuit 32, memory unit 33, latch circuit 34 and increased voltage generating control circuit 35.
- Logic circuit 30 outputs write control signal SPWR and erase control signal SPER from two output terminals 30W and 30E to write and erase control circuit 31.
- the write control signal SPWR and erase control signal SPER enables a setting and releasing of the software data protection and an ordinary operation (data erase, data write and data read) for cell matrix 2 in a state of releasing the software data protection.
- the address and data for setting the software data protection can be provided such that in address is received upon a fall of WE , and data is received upon a right of WE as shown in Figure 5.
- the address and data for releasing software data protection can be provided such that the address is received upon a fall of WE and the data is received upon the rise of WE .
- Write erase control circuit 31 comprises NAND circuit 36 for outputting write control signal SPWR and NAND circuit 37 for outputting erase control signal SPER .
- Such one input terminal of NAND circuit 36 receives a reverse signal SPS of the output signal SPS of latch circuit 34 designating whether the software data protection state is set or is released. (When software data protection state is set, the signal SPS is at "H” and when it is released, the signal SPS is at "L".)
- the other input terminal of NAND circuit 36 receives the signal SPWR of logic circuit 30.
- NAND circuit 37 receives the output signal SPS of latch circuit 34 at one input terminal and receives the output signal SPER from logic circuit 30 at the other input terminal.
- a write and erase circuit 32 has one and the other input terminals connected to the output terminal of NAND circuit 36 and 37 and has one and the other output terminals 32W and 32E connected to drain 40d of EEPROM cell 40 and control gate 40g thereof.
- Storing unit 33 comprises nMOS 38, 39 and EEPROM cell 40 as shown in Figure 4.
- nMOS 38 is a selection transistor for controlling a read of data stored in EEPROM cell 40 and has the drain connected to power source line 41 and has the gate connected to read control circuit input terminal 42 for receiving read control signal SG and has the source connected to the drain and nMOS 39.
- nMOS 39 forms a load of EEPROM cell 40 and has the gate and source connected to each other and has the connection point connected to the drain of EEPROM cell 40.
- nMOS 39 comprises nMOS of depletion type. The source of EEPROM cell 40 is grounded in the drawing but is made floating upon writing of the data.
- nMOS 38 operating as a selection transistor is provided on the side of the power source voltage Vcc and by reversing the connection relation between nMOS 38 and load transistor nMOS 39, load transistor nMOS 39 may be provided on the side of the power source voltage Vcc.
- Latch circuit 34 latches the current memory data (logic state) of EEPROM cell and outputs signals SPS and SPS to NAND circuits 36 and 37, respectively and comprises NAND circuit 43, 44, 45 and 46 and inverters 47 and 48, and NOR circuit 49.
- NAND circuit 43 has one input terminal connected to the drain of EEPROM cell 40 and the output terminal connected to one input terminal of NAND circuit 45 and one input terminal of NAND circuit 44.
- NOR circuit 49 has one and the other input terminals connected to the output terminals 30W and 30E of logic circuit 30, respectively, and has the output terminal connected to the other input terminal of NAND circuit 43 and the other input terminal of NAND circuit 44.
- NAND circuit 45 has the other input terminal connected to an output terminal of NAND circuit 46 and input terminal of inverter 48 and has the output terminal connected to one input terminal of NAND circuit 46 and the input terminal of inverter 47.
- NAND circuit 46 has the other input terminal connected to an output terminal of NAND circuit 44.
- Inverter 47 has the output terminal ( SPS output) connected to one input terminal of NAND. circuit 37 of write erase control circuit 31.
- Inverter 48 (SPS output) connected to one input terminal of NAND circuit 36 of write erase control circuit 31.
- the increased voltage generating control circuit 35 outputs increased voltage generating control signal VPACT to control the oscillation operation of the ring oscillator 22 of the voltage increase clock signal generating circuit 15 and comprises a NOR circuit 50, NAND circuits 51, 52 and an inverter 53.
- One and the other input terminals of the NOR circuit 50 are connected to one output terminal 30W and the other output terminal 30E of the logic circuit 30, respectively.
- One or the other input terminal of the NAND circuit 51 are connected to the output terminals of inverter 47 and the NOR circuit 50.
- One input terminal of the NAND circuit 52 is connected to the output terminal of the NAND circuit 51.
- the other input terminal of the NAND circuit 52 receives write signal WR (which becomes "H" during a normal write mode) which is produced by a control circuit (not shown) in the EEPROM and is used for the EEPROM.
- the output terminal of the NAND circuit 52 is connected to the input terminal of the inverter 53 and the output terminal of the inverter 53 is connected to the other input terminal of the NAND circuit 17 of the voltage increase circuit clock signal generating circuit 15.
- the present embodiment can realize a software data protection function by writing and storing logic "0" in the EEPROM cell 40.
- the present embodiment reads and stores in latch circuit 34 the logic state (store data) of EEPROM cell 40 which stores a setting state or releasing state of the software data protection, every time a switching operation for setting or releasing the software data protection is conducted. Then, the present embodiment prevents the same logic state as that stored in the EEPROM cell 40 from being set therein by using the write and erase control circuit 31, based on the signals SPS and SPS for setting and releasing the software data protection and output from the latch circuit 34. Thus, unnecessary write and erase operations conventionally conducted for the EEPROM cell 40 can be avoided.
- the above embodiment can prevent the same data from being written into the EEPROM cell 40 again. It can also prevent the erase operation from being performed again or repeatedly. It is operable even if only repeated writing of the same data into EEPROM cell 40 is prevented. This case can achieve almost the same effect as the above embodiment although its advantage is not as great.
- Figure 7 shows a detailed circuit structure of the logic circuit 30.
- the logic circuit 30 comprises five flip-flops 310, 320, 330, 340 and 350 connected in series.
- the output terminal of the inverter 354 of flip-flop 350 in the last stage is connected to one input terminal of four input NAND circuits 801, 901 and 101.
- flip-flops circuits 310, 320, 330, 340 and 350 have the same circuit configuration and thus the explanation will be made as to flip-flip 310.
- Flip-flop 310 is a reset flip-flop (called R-S-FF hereinafter) comprising a NAND circuit 311, NAND circuit 312, 313 whose output terminal is connected to the other input terminal of NAND circuit 312, an inverter circuit 314 whose input terminal is connected to the output terminal of NAND circuit 312, and an inverter 315 whose input terminal is connected to the output terminal of NAND circuit 312.
- the output of inverter 314 is connected to one input terminal of NAND circuit 323 of flip-flop circuit 320 in the next stage, thereby forming a serial connection of flip-flop circuit 310 and flip-flop circuit 320.
- Flip-flop circuits 320, 330, 340 and 350 are connected in series as described above.
- One input terminal of NAND circuits 311, 321, 331, 341 and 351 of respective flip-flop circuits 310, 320, 330, 340 and 350 receive signal SRST to be output from inverter 1407 to reset flip-flop circuits 310, 320, 330, 340 and 350.
- One input terminal of flip-flop circuit 310 is connected to power source voltage Vcc (5V) and is normally kept at "H”.
- the other input terminal is connected to the output terminal of inverter 401.
- the output terminal of inverter 361 is also connected to the other input terminal of NAND circuit 353 of flip-flop 350.
- Address selection circuit 400 receives 15 address signals A 0 -A 14 and a control signal PRAD output from a control unit not shown.
- Address selection signal 400 comprises NAND circuit 409 for receiving address signals Ao and A 2 and address signals Ai and A3 through respective inverters 402 and 403, NAND circuit 410 for receiving address signals A4 and As and address signals As and A 7 through respective inverters 404 and 405, NAND circuit 411 for receiving address signals As and A 10 and for receiving address signals As and A" through respective inverters 406 and 407 and NAND circuit 412 for receiving address signals A 12 and A 14 and for receiving address signals PRDD and A 12 through the inverter 408.
- NAND circuit 417 for receiving the outputs of NAND circuits 409, 410, 411 and 412 through respective inverters 413, 414, 415 and 416 and inverter 401 for providing the output to the other input terminal of NAND circuit 417.
- Address selection circuit 400 turns the output of inverter 401 to "H” only when the 16-bit address comprising address signals Ao to A 14 and signal PRAD becomes “5555", thereby providing "H” to NAND circuit 313 of flip-flop circuit 310.
- Data selection circuit 500 receives 8-bit data signals Do-D 7 and output signal PRDD of a control unit not shown and comprises NAND circuit 506 for receiving data signals Do and D 2 and for receiving data signal D, through inverter 502, NAND circuit 507 for receiving data signal D 4 and for receiving data signals D 3 and D 5 through resepctive inverters 503 and 504, and NAND circuit 508 for receiving data signal D 6 and signal PRDD, and data signal D 7 through inverter 505.
- NAND circuit 512 for receiving the outputs of NAND circuits 506, 507 and 508 through respective inverters 509, 510 and 511, and inverter 501 for receiving the output of NAND circuit 512 and providing the output to the other input terminal of NAND circuit 323 of flip-flop circuit 320.
- the data selection circuit 500 turns the output of inverter 501 to "H” only when data signals Do-D 7 become “AA” and the signal PRDD becomes “H”, thereby providing "H” signal to NAND circuit 323 of flip-flop circuit 320.
- Address selection circuit 600 receives 15 address signals A 0 -A 1 and a control signal PRAD of a control unit not shown in the same manner as in address selection circuit 400.
- Address selection signal 600 comprises NAND circuit 610 for receiving address signal A 2 and address signals A o , A, and A3 through respective inverters 602, 603 and 604, NAND circuit 611 for receiving address signals A4 and A 6 and address signals As and A 7 through respective inverters 605 and 606, NAND circuit 612 for receiving address signals As and A,o and for receiving address signals As and A 11 through respective inverters 607 and 608, and NAND circuit 613 for receiving address signals A12 and A 1 and for receiving the signal PRAD and the address signal A12 through the inverter 609.
- NAND circuit 618 for receiving the outputs of NAND circuits 610, 611, 612 and 613 through respective inverters 614, 615, 616 and 617 and inverter 601 for receiving the output of NAND circuit 618 and for providing the output to NAND circuit 333 in flip-flop circuit 330.
- Address selection circuit 600 turns the output of inverter 601 to "H” only when the 16- bit address comprising address signals Ao to A 15 and signal PRAD becomes "2AAA(H), thereby providing "H” to NAND circuit 333 of the flip-flop circuit 330.
- Data selection circuit 700 receives 8-bit data signals Do-D 7 and control output signal PRDD of a control unit not shown and comprises NAND circuit 707 for receiving data signal D 1 and for receiving data signals Do and D 2 through inverters 702 and 703, NAND circuit 708 for receiving data signals D 3 and D 5 and for receiving data signals D 4 through resepctive inverter 710, and NAND circuit 709 for receiving data signal D 7 and control signal PRDD and for receiving data signal 6 through inverter 708.
- NAND circuit 713 for receiving the outputs of NAND circuits 710, 711 and 712 through respective inverters 710, 711 and 712, inverter 701 for receiving the output of NAND circuit 713 and providing the output to the other input terminal of NAND circuit 343 of flip-flop circuit 340.
- the data selection circuit 700 turns the output of inverter 701 to "H” only when data signal Do-D 7 becomes “55” and the control signal PRDD becomes “H”, thereby providing "H” signal to the other input terminal of NAND circuit 343 of flip-flop circuit 340.
- the logic circuit further comprises data selection circuits 800, 900 and 1000, which receive 8-bit data signals Do-D 7 and control signal PRDD in the same as data selection circuit 500 and 700.
- Data selection circuit 800 comprises NAND circuit 807 for receiving data signals Do and D 2 and for receiving data signal D 1 through inverter 802, NAND circuit 808 for receiving data signal D 4 and for receiving data signals D 3 and Ds through inverters 803 and 804 and NAND circuit 809 for receiving control signal PRDD and for receiving data signals Ds and D 7 through resepctive inverters 805 and 806.
- NAND circuits 807, 808 and 809 provide outputs to NAND circuit 801 through respective inverters 810, 811 and 812.
- the output signal SPW from NAND circuit 801 is supplied to one input terminal of NAND circuit 1101 of flip-flop circuit 1100 and three-input NAND circuit 1401
- the data selection circuit 800 produces the output "H" from NAND circuit 801, only when the 8-bit data signal comprising data signals Do to D 7 becomes "AO" and control signal PRDD becomes "H".
- Data selection circuit 900 comprises NAND circuit 909 for receiving data signal Do and for receiving data signals D, and D 2 through respective inverters 902 and 903, NAND circuit 910 for receiving data signals D 3 , D4. and Ds through respective inverters 904, 905 and 906 and NAND circuit 911 for receiving control signal PRDD and for receiving data signals D 6 and D 7 through respective inverters 907 and 908. It further comprises NAND circuit 901 for receiving the output of NAND circuits 909, 910 and 911 through respective inverters 912, 913 and 914. The output signal SPR of NAND circuit 901 is input to NAND circuit 1401. The data selection circuit 900 produces the output "H" from NAND circuit 1001 only when the 8-bit data comprising data signals Do to D 7 becomes "20" and control signal PRDD becomes “H", thereby providing "H" signal to NAND circuit 1401.
- Data selection circuit 1000 comprises NAND circuit 1009 for receiving data signal D 2 and for receiving data signals Do and D, through inverters 1002 and 1003, NAND circuit 1010 for receiving data signals D 3 , D 4 and D 5 through inverters 1004, 1005 and 1006 and NAND circuit 1011 for receiving signal PRDD and for receiving data signal Ds and D 7 through inverters 1007 and 1008, and NAND circuit 1001 for receiving the outputs of NAND circuits 1009, 1010 and 1011 through respective inverters 1012, 1013 and 1014.
- the output signal SPE of NAND circuit 1001 is applied to one input terminal of NAND circuit 1201 in flip-flop circuit 1200 and NAND circuit 1401.
- Data selection circuit 1000 produces the output "H” from NAND circuit 1001 only when data signals Do-D 7 become “20” and controls signal PRDD becomes “H”, thereby providing "H” to NAND circuit 1401 and to one input terminal of NAND circuit 1201 of flip-flop circuit 1200.
- NOR circuit 1402 has one input terminal connected to the output terminal of NAND circuit 1401 and the other input terminal receive signal INT of a falling pulse upon a rise of the power source Vcc after the signal INT is inverted by inverter 1408.
- Inverter 1403 inverts the output of inverter 1408, signal INT , and provides the output to the other input terminal of NAND circuit 1102 of flip-flop circuit 1100 and to the other input terminal of NAND circuit 1202 of flip-flop circuit 1200.
- the output terminal of NOR circuit 1402 is directly connected to one input terminal of NAND circuit 1406 and is connected to the other input terminal of NAND circuit 1406 through inverters 1404 and 1405.
- the output of NAND circuit 1406 forms the signal SRST through inverter 1407 so that the signal SRST is input to one input terminal of NAND circuit 311 in flip-flop circuit 310.
- Flip-flop circuit 1100 comprises an R-S-FF formed of NAND circuits 1101 and 1102, inverter 1103 for inverting the output of NAND circuit 1101 and inverter 1104 for inverting the output of NAND circuit 1102 and providing the output of inverter 1104 to write erase control circuit 31 shown in Figure 4 as the write control signal SPWR.
- Flip-flop circuit 1200 comprises NAND circuits 1201 and 1202 for forming an R-S-FF and inverter 1203 for inverting the output of NAND circuit 1201 and inverter 1204 for inverting the output of NAND circuit 1202.
- the output of inverter 1204 is supplied to write erase control circuit 31, shown in Figure 4 as erase control signal SPER.
- address signals Ao-Ais and data signals Do-D 7 are respectively supplied through an address bus and a data bus from an external control circuit (comprising a micro processor, for example), not shown.
- logic circuit 30 The operation of logic circuit 30 will be explained sequentially as follows.
- the address signals "5555" in the above (1) changes the output of inverter 401 of address selection circuit 400 from “L” to “H” so that "H” is input to the other input terminal of NAND circuit 313 of flip-flop circuit 310.
- output signal OUT1 of flip-flop circuit 310 becomes “H” and is input to one input terminal of NAND circuit 312 of flip-flop circuit 320 in the next stage.
- write erase control circuit 31 controls write erase circuit 32 as described before, so that the logic "0" designating the setting of the software data protection is written in EEPROM cell 40 in storing unit 33, shown in Figure 4.
- address signal "5555" and data signal “AA” described in (1) above sequentially set the output OUT1, OUT2 of flip-flop circuits 310 and 320 to "H".
- Address signal "AAAA” and data signal “55”, as described in (2) above set outputs OUT3 and OUT4 of flip-flop circuits 330 and 340 to "H”.
- address signal "5555" described in (3) above sets the output signal SPINT of flip-flop circuit 350 at “H” and then when data signal "80" is output, output signal SPR of NAND circuit 901 of flip-flop circuit 900 changes from “H” to "L”. Therefore, the output of NAND gate 1401 becomes “H” and the output SRST of inverter 1407 changes from “H” to “L”. As the output S RST changes from “H” to “L”, all the outputs of flip-flop circuits 310, 320, 330, 340 and 350 are reset to “L”.
- Figure 8 shows the detailed circuit structure of the write erase control circuit 31, the write erase circuit 32, the storing unit 33 and the latch circuit 34 shown in the embodiment shown in Figure 4.
- the write erase circuit 32 comprises a write circuit 32a and an erase circuit 32b.
- Write circuit 32a comprises PMOS 3201, nMOS 3202 and nMOS 3203 connected in series between power source voltage Vcc and the ground, MOS capacitor 3204 connected between the source of PMOS 3201 and the drain of nMOS 3202, nMOS 3205 of the depletion type connected to the other terminal of MOS capacitor 3204 and whose gate and drain are connected, PMOS 3206 having its source and gate respectively connected to the drain and source of nMOS 3205 and having its drain connected to the power source Vpp, PMOS 3207 having its gate connected to the source of depletion type nMOS 3205 and its source connected to the power source voltage Vpp, PMOS 3208 having its drain commonly connected to the drain of PMOS 3207 and its source connected to ground, inverter 3209 having the output of NAND gate 36 of the write erase control circuit 31 connected to the input terminal and having the output PN connected to the gate of PMOS
- MOS capacitor 3212 has one of its terminals connected to the output terminal of NOR circuit 3211 and the other connected to ground.
- the gates of PMOS 3201 and nMOS 3202 receive a clock signal SCLK of a predetermined duty ratio. This signal is generated from a clock generator, not shown, which operates when an "H" of write control signal SPWR is transmitted, and the source of transfer gate 3210 is connected to the source of nMOS 3205 of the depletion type and the gate of nMOS 3207 and of nMOS 3206.
- the gate of transfer gate 3210 is connected to the power source voltage Vcc.
- Erase circuit 32b has a similar configuration to that of write circuit 32a.
- Erase circuit 32b comprises PMOS 4201. nMOS 4202, and nMOS 4203 which are connected in series between power source voltage Vcc and the ground, MOS capacitor 4204 connected between the source of PMOS 4201 and the drain of nMOS 4202, nMOS 4205 of the depletion type connected to the other terminal of MOS capacitor 4204 and whose gate and drain are connected, PMOS 4206 whose source and gate are respectively connected to the drain and source of nMOS 4205 and whose drain is connected to the power source voltage Vpp, PMOS 4207 whose gate is connected to the source of depletion type nMOS 4205 and whose source is connected to the power source voltage Vpp, inverter 4209 having an input connected to the output of NAND gate 37 of write erase control circuit 31 and whose output PE is connected to the gate of PMOS 4203 and to the drain of transfer gate 4210, inverter 4211 for outputting the reverse output of output PE of inverter 4209 to a gate of PMOS 3302 in the storing unit
- the gates of PMOS 4201 and nMOS 4202 receive a clock signal SCLK of a predetermined duty ratio and generated from a clock generator, not shown, which operates upon an "H" of erase control signal SPER.
- the source of transfer gate 4210 is connected to the source of nMOS 4205 of the depletion type and the gate of nMOS 4207 of nMOS 4206.
- the gate of transfer gate 4210 is connected to the power source voltage Vcc.
- EEPROM cell 40 comprises 2 EEPROM cell 40a and 40b, which are connected in parallel. It comprises nMOS 3303 and nMOS 3304 connected in series between the power source voltage Vcc and the ground. The source of EEPROM cell 40 is connected to the source of nMOS 3303 and the drain of nMOS 3304. Storing unit 33 further comprises PMOS 3305 and nMOS 3306 connected in series between the power source voltage Vcc and ground. Output PW of inverter 3209 of write circuit 32a are applied to the gates of nMOS 3305 and nMOS 3306. The source of PMOS 3305 and the drain of nMOS 3306 are connected to the gate of nMOS 3304.
- nMOS 39 of the depletion type, nMOSs 38 and 3309 connected in the OR connection and nMOS 3310 are connected between the drain of EEPROM cell 40 and the power source voltage Vcc.
- the gate of nMOS 3310 receives the output PE of inverter 4209 of erase circuit 32b and the output PW of inverter 3209 of write circuit 32a through NOR circuit 3311.
- the source of depletion type nMOS 39 is connected to inverter 3312 and the output of inverter 3312 is inverted by inverter 3313. It is also connected to one input terminal of NAND circuit 43 of latch circuit 34.
- Storing unit 33 further comprises PMOS 3314, depletion nMOS 3315, nMOS 3316 and OR connected nMOSs 3317 and 3318, which are connected in series with each other between power source voltage Vcc and the ground.
- the gate of depletiontype nMOS 3315 and nMOS 3316 are connected to the drain of depletiontype nMOS 315.
- the gate of PMOS 3214 receives the signal INT through inverters 3301 and 3319 when the signal INT generate a fall of pulse upon a rise of the power source voltage Vcc.
- the output PR of inverter 3301 is input to NOR circuit 3211 of write circuit 32a.
- the output of inverter 3319 is input to the gates of nMOS 3318 and PMOS 3307.
- nMOS 3320, nMOS 3302 and nMOS 3321 are connected in series between the power source voltage Vcc and the ground.
- the gate of nMOS 3320 is connected to the drain of depletiontype nMOS 3315.
- the drain of depletiontype nMOS 3315 is connected to nMOS 3322 and the other terminal is grounded.
- the gate of nMOS 3322 receives the other output of inverter 3319.
- nMOS 3321, nMOS 3322 and nMOS 3318 are connected to the output terminal of inverter 3319 and the source of nMOS 3320 is connected to the gate of EEPROM cells 40a and 40b, and to the drain of nMOS 4207 of erase circuit 32b.
- the reading mode is carried out when the power source voltage Vcc is applied the apparatus body or the write or erase of the stored data (logic state) is performed for EEPROM cell 40 by write erase circuit 32.
- the signal INT produces a fall pulse.
- “L” is applied to respective gates of PMOS 3314, PMOS 3307, nMOS 3318, nMOS 3321 and nMOS 3322 through inverters 3301 and 3319, thereby turning on PMOSs 3314 and 3307 and turning off nMOS's 3318, 3321 and 3322.
- PMOS 3314 is turned on
- nMOS 3316 is turned on through nMOS 3315 of the depletion type and when nMOS 3316 is turned on, nMOS 3317 is also turned on.
- the source voltage of the depletion type nMOS 3315 becomes about 2V and is applied to the gates of nMOS 3320 and nMOS 38. As a result, both nMOS 3320 and nMOS 38 become "ON".
- nMOS 3320 As nMOS 3320 is turned on, nMOS 3321 and nMOS 4207 are turned off, and about 2V is applied to the gate of EEPROM cells 40a and 40b. Then, as nMOS 3304 is turned on, the source voltages of EEPROM cells 40a and 40b become 0V. Further, as PMOS 3307, depletiontype nMOS 39 nMOS 38 and nMOS 3310 are turned on, respective drains of EEPROM cells 40a and 40b and power source voltage Vcc become conductive.
- a logic "0" is set in EEPROM cells 40a and 40b and the electron is released from the floating gate of EEPROM cells 40a and 40b.
- PMOS 3201 and nMOS 3202 repeat an on and off operation alternatelyin accordance with clock SCLK. Therefore.
- one terminal of MOS capacitor 3204 is set at about 5V (power source voltage Vcc) when PMOS 3201 is turned on, and it is set at about 0V (ground voltage) when nMOS 3202 and nMOS 3203 are on.
- Vcc power source voltage
- nMOS 3202 and nMOS 3203 ground voltage
- the output PW ("H") of inverter 3209 is applied to respective gates of nMOS 3206 andS 3207 through transfer gate 3210, thus ng on nMOS 3206 and 3207.
- the source voltage of nMOS 3206 is applied to the drain and source of depletion type nMOS 3206 and the other terminal of nMOS capacitor 3204. Therefore, MOS capacitor 3204 is gradually charged up to the power source voltage Vpp (about 20V). Therefore, when the voltage of MOS capacitor 3204 increases to the power source voltage Vpp (about 20V), the source voltage of depletion type nMOS 3205 becomes about 20V. Thus, the gate voltage of nMOS 3206 and nMOS 3207 becomes about 20V. Therefore, the power source voltage Vpp (about 20V) is applied to the drain of EEPROM cells 40a and 40b through nMOS 3207.
- nMOS 3320 and nMOS 4207 are turned off and nMOS 3302 and nMOS 3321 are turned on, thereby applying "L” to the gates of EEPROM cells 40a and 40b.
- the output of the NOR circuit 3311 is turned to “L” and "L” is aplied to the gate of nMOS 3310. Therefore, EEPROM cell 40 is separated from latch circuit 34 by nMOS 3310.
- Vcc (about 5V) is applied to the source of EEPROM cells 40a and 40b.
- logic "1" " is set at EEPROM cells 40a and 40b, i.e., an electron is injected to the floating gate of EEPROM cells 40a and 40b.
- a clock SCLK with a predetermined frequency is applied from a clock generator (not shown) to the gate of PMOS 4201 and nMOS 4202. Therefore, PMOS 4201 and nMOS 4202 alternately repeat an on and off operation in accordance with clock SCLK. Therefore, one terminal of MOS capacitor 4204 is set at about 5V (power source voltage Vcc) when PMOS 4201 is turned on and at about 0V (ground voltage) when nMOS 4202 and 4203 are on. Thus, the voltage of one terminal of nMOS capacitor 4204 varies alternately.
- the output PE ("H") of inverter 4209 is applied to respective gates of nMOS 4206 and 4207 through transfer gate 4210, turning on nMOSs 4206 and 4207. Therefore, the source voltage of nMOS 4206 is applied to the drain and source of depletion type nMOS 4206 and the other terminal of nMOS capacitor 4204. Therefore, MOS capacitor 4204 is gradually charged up (to the power source voltage Vpp about 20V). Therefore, when the voltage of MOS capacitor 4204 increases to the power source voltage Vpp (about 20V), the source voltage of depletion type nMOS 4205 becomes about 20V. Thus, the gate voltage of nMOSs 4206 and 4207 becomes about 20V. Therefore, the power source voltage Vpp (about 20V) is applied to the gate of EEPROM cells 40a and 40b through nMOS 4207.
- the drain of EEPROM cells 40a and 40b are separated from the source of nMOS 38 and 3309 by nMOS 3310.
- the output PR("L") of inverter 3301 is inverted by inverter 3319 to "H”, and applied to respective gates of PMOS 3314 and nMOSs 3318, 3321 and 3322.
- PMOS 3314 is turned off and nMOS 3322 is turned on.
- "1" " is applied to the gate of nMOS 3320 and nMOS 3316, thereby turning both of them off.
- nMOS 3321 is also turned on.
- the output PE("H") of inverter 4209 is inverted by inverter 4211 to "L” and applied to nMOS 3302, thereby turning off nMOS 3302.
- both nMOS 3302 and 3320 turn off and about 20V is applied to the gate of EEPROM cells 40a and 40b through nMOS 4207.
- the output PW of inverter 3209 become “L”
- PMOS 3305 is turned on
- nMOSs 3303 and 3306 are turned off.
- PMOS 3305 is turned on
- nMOS 3304 is turned on. Therefore, the sources of EEPROM cells 40a and 40b are made about 0V.
- the output of NOR circuit 3211 is turned to "H”
- nMOS 3208 is turned on, thereby turning the drains of EEPROM cells 40a and 40b to about 0V.
- the gate of EEPROM cells 40a and 40b are made about 20V and the source and drain thereof are made to be at about 0V. Therefore, the electron is injected to the floating gates of EEPROM cells 40a and 40b, thereby setting logic "1 " in them. In other words the software data protection is released.
- nMOS 3320 is turned off and nMOSs 3302 and 3321 are turned on and, as described above, nMOS 4207 is turned off, thereby enabling about 0V to be applied to the gate of EEPROM cells 40a and 40b.
- PMOS 3305 As output PW of inverter 3209 is turned to "L", PMOS 3305 is turned on and nMOSs 3303 and 3306 are turned off. Further, PMOS 3305 turns on, thereby turning on nMOS 3304. Therefore, nMOS 3303 is turned off and nMOS 3304 is turned on, and the sources of EEPROM cells 40a and 40b become about 0V.
Abstract
Where an electrically erasable and programmable non-volatile semiconductor memory element (EEPROM cell) for storing a setting and releasing of the software data protection has already been set in the logic state designating the software data protection setting state, an operation of setting the logical state designating the software data protection setting is not applied to the EEPROM cell even if the address and data for setting the software data protection is input. Further, where the logic state designating the releasing of the software data protection has been set in the electrically erasable and programmable non-volatile semiconductor memory element, the operation of setting the logical state designating the release of the software data protection is not set to the EEPROM cell, even if the address and the data for releasing the software data protection is input.
Description
- The present invention relates to a semiconductor memory device and more particularly to an electrically erasable and programmable non-volatile memory device, namely, an electrically erasable and programmable read only memory, called an EEPROM hereinafter.
- Generally speaking, an EEPROM receives a chip enable signal CE , an output enable signal OE or a write enable signal WE as a control signal and determines various modes for waiting, erasing, writing or reading based on the logical state of those signals. However, these control signals CE , OE and WE are apt to be affected by variations in power source voltage or noise, and their logical states are made wrong by the variations in power source voltage or noise. As a result, sometimes a writing mode is incidentally set and error data is written, thereby resulting in an error writing operation. Such error writing can be avoided by providing a so-called software data protection circuit within the memory device.
- Conventionally, an EEPROM equipped with a software data protection circuit, as shown in Figure 1, is utilized.
- In Figure 1, the EEPROM comprises a row-
decoder 1, acell matrix 2, aread column decoder 3, aread column gate 4, a sense amplifier 5, an I/0buffer 6, an E/W (erase/write)column decoder 7, anEfW column gate 8 and a page register 9. It further comprises a controlsignal logic circuit 10, an E/W timing signal generating circuit 11, an increasedvoltage generating circuit 12, and a softwaredata protection circuit 13. - In such an EEPROM, the chip enable signal CE , the output enable signal OE and the write enable signal WE are put in the state shown in the following table 1, thereby enabling the EEPROM to be set in the write mode.
data protection circuit 13 is for preventing an error write caused as described above. Softwaredata protection circuit 13 has anEEPROM cell 13A, which sets a softwaredata protection circuit 13 to prevent the data from being written in respective memory cells incell matrix 2 by setting storing and maintaining a discretional logic value inEEPROM cell 13A. An address signal of 16 bits comprising, for example, the row-address and column- address input tomatrix 2 and the data output fromI /0buffer 6,are input to the softwaredata protection circuit 13. The software data protection is set by sequentially providing the address and the data to the softwaredata protection circuit 13. - That is, in the software
data protection circuit 13, a writing operation is performed for theEEPROM cell 13A when (1) address = 5555, data = AA, (2) address = 2AAA, data = 55, and (3) address = 5555, data = AO are sequentially input to the softwaredata protection circuit 13. The address and data will be expressed by a hexadecimal notation herein. Then logic "0" (conduction state) is set in theEEPROM cell 13A, thereby setting, storing and maintaining a software data protection state. Thereafter, when this state is not released, providing the address and data for setting the software data protection is not input to thatcircuit 13, i.e., providing write data is not input to thecircuit 13 following the address and data for setting the software data protection is not input thereto, the increased voltage VPP necessary to write the data in respective EEPROM cells formingcell matrix 2 is prevented from being output from the increasedvoltage generating circuit 12, thereby preventing the data from being written into respective memory cells incell matrix 2. - Therefore, when such software
data protection circuit 13 is provided, even if the logic state of the above control signals CE , OE and WE incorrectly set by the variation of the power source voltage and the noise and thuslogic circuit 10 for a control signal is set write mode incorrectly, the increase voltage Vpp is not applied to a control gate of respective EEPROM cell formingcell matrix 2 and thus the data is prevented from writing into respective EEPROM cells ofcell matrix 2. - When (1) address = 5555, data = AA, (2) address = 2AAA, data = 55, (3) address = 5555, data = 10, (4) address = 5555, data = AA, (5) address = 2AAA, data = 55, and (6) address = 5555, data = 20 are sequentially input to software
data protection circuit 13, a deletion operation is performed forEEPROM cell 13A and logic "1" (non conductive state) is set inEEPROM cell 13A and thus software data protection testing state is removed. - As described above, in the conventional EEPROM, when the software data protection state is set, data is not written in
cell matrix 2 if an address and data for setting the software data protection is not input toEEPROM cell 13A. In other words, the software data protection state is set, the write operation is performed forEEPROM cell 13A whenever the data is written intocell matrix 2. When write mode is set, write operation is not performed to all the EEPROM cells performingcell matrix 2. Namely, when the setting and releasing operation of software data protection are frequently performed, the writing operation for EEPROM in softwaredata protection circuit 13 is performed more than that for the writing operation for thediscretional EEPROM cell 13A. - In a write mode, a write operation is not carried out for all the EEPROM cells forming a
cell matrix 2. Namely, the number of a write operation by which data is written in EEPROM 13A in softwaredata protection circuit 13 is sometimes larger than that of a write operation by which data is written in a discretional EEPROM cell formingcell matrix 2. - Therefore, in the conventional EEPROM, there is a problem that
EEPROM cell 13A forming the softwaredata protection circuit 13 is deteriorated before EEPROM cell forming thecell matrix 2 is deteriorated. - An object of the present invention is to provide EEPROM of capable of decreasing the deterioration of the EEPROM cell forming the software data protection circuit so that EEPROM cell can maintain function or in longer period of time.
- EEPROM is equipped with a software data processing circuit having an EEPROM cell. The software data protection circuit can memorize and maintain the software data protection setting state by setting the EEPROM cell to one logic state, for example, logic "0" (conductive state) where it receives the address and data for setting the software data protection and memorize and maintain the software data protection releasing state by setting the EEPROM cell to be in the other logic state, for example, logic "1" (nonconductive state) where it receives an address and data for removing the software data protection.
- The first invention provides the logic state setting control means for controlling the logic state setting operation of the EEPROM cell so that, where the EEPROM cell is set to be in one logic state, for example, logic "0", one logic state, namely, the state of logic "0" is not repeatedly set in the EEPROM, even if the address and data for setting the software data protection is received.
- An increase voltage for setting one logic state "0" is not supplied to a drain or source of EEPROM cell therefore the increase voltage for software data protection is prevented from being applied to the EEPROM cell and the EEPROM cell for forming the software data protection circuit is prevented from being deteriorated largely.
- The second invention further provides a logic state setting control circuit for controlling the logic state setting operation of the EEPROM cell so that, where the EEPROM cell is already set in the other logic state, namely, logic "1", the other logic state, namely the state of logic "1 " is not repeatedly set, even if the address and data for removing the software data protection is input.
- In the second invention, in addition to the setting of the software data protection, the unnecessary increase voltage is prevented from being applied to EEPROM upon the release of the data protection and thus the second invention can prevent the deterioration of the EEPROM cell for a longer period time than the first invention.
-
- Figure 1 shows a block diagram of a circuit of a conventional EEPROM,
- Figure 2 shows a timing chart of the data write in the conventional EEPROM shown in Figure 1,
- Figure 3 shows a block diagram of an embodiment of the present invention,
- Figure 4 shows a circuit diagram of an increased voltage generating circuit and a software data protection circuit according to one embodiment of the present invention,
- Figure 5 shows a timing chart for obtaining an address and data for setting the software data protection,
- Figure 6 designates a timing chart for obtaining an address and data for releasing the software data protection,
- Figure 7 shows a detailed circuit diagram of a logic circuit used in the software protection circuit in the embodiment shown in Figure 4, and
- Figure 8 shows a detailed circuit diagram of a write and erase circuit and memory unit of the software data protection circuit in the embodiment shown in figure 4.
- The embodiment of the present invention will be described by referring to the drawings.
- Figure 3 shows a block diagram designating one embodiment of the present invention. In Figure 3, EEPROM of the present invention provides the software
data protection circuit 14 with detail circuit shown in Figure 4, in place of softwaredata protection circuit 13 shown in Figure 1 as a prior art and the other part of EEPROM shown in Figure 1 is formed in the same manner as the prior art EEPROM shown in Figure 1. Therefore, the same block as that shown in Figure 1 is designated by the same reference number as Figure 1 and the explanation of the block is abbreviated. - Figure 4 shows an example of increased
voltage generating circuit 12 in the above recited softwaredata protection circuit 14. As shown in Figure 4, increasedvoltage generating circuit 12 comprises voltage increase circuit clocksignal generating circuit 15 andvoltage increasing circuit 16. Voltage increase circuit clocksignal generating circuit 15 comprises aring oscillator 22 comprisingNAND circuit 17, andinverters buffer inverters -
NAND circuit 17 andinverters inverter 21 is connected to one input terminal ofNAND circuit 17, thereby forming aring oscillator 22. The increased voltage generating control signal VPACT is input to the other input terminal ofNAND circuit 17 and when increased voltage generating control signal VPACT is at a high level "H",ring oscillator 22 performs an oscillation operation.Inverters inverters - Voltage increased
circuit 16 comprises n-channel MOS transistors (which is called nMOS) 25, 26-1, 26-2...26-n, for example n=20), capacitors 27-1, 27-2...27-n and increased voltage output terminal 28. nMOS 25 has drain and gate connected topower source line 29 to which power source voltage VCC (5V) is applied and its source connected to the drain and gate of nMOS 26-1. nMOS 26-1 has its source connected a drain and gate of nMOS 26-2. The same connection is made from nMOS 26-1 to nMOS 26-n. The source of nMOS 26-n is connected to increased voltage outputting terminal 28. A connecting point between a drain of nMOS 26-1 and gate thereof, a connecting point between a drain of nMOS 26-3 (not shown) and a gate thereof, ... and a connecting point between a drain of nMOS 26-n-1 and a gate thereof are connected to an output terminal ofinverter 23 of voltage increased circuit clocksignal generating circuit 15 through capacitors 27-1, 27-3...27-n-1, respectively. A connecting point between a drain and a gate of nMOS 26-2, a connecting point between a drain and a gate of nMOS 26-n are connected to the output terminal of theinverter 24 of increased voltage circuit clocksignal generating circuit 15 through capacitors 27-2...27-n. - In
voltage increase circuit 16 constructed above, capacitors 27-1, 27-2...27-n are charged up when voltage increased circuit clock signal CLK and CLK are applied thereto and the voltages on the side of nMOS 26-1, 26-2...26-n are sequentially increased. The increased voltage VPP of 20V, for example, can be obtained at increased voltage output terminal 28. - Software
data protection circuit 14 compriseslogic circuit 30, write erasecontrol circuit 31, write erasecircuit 32,memory unit 33,latch circuit 34 and increased voltagegenerating control circuit 35. -
Logic circuit 30 outputs write control signal SPWR and erase control signal SPER from twooutput terminals control circuit 31. The write control signal SPWR and erase control signal SPER enables a setting and releasing of the software data protection and an ordinary operation (data erase, data write and data read) forcell matrix 2 in a state of releasing the software data protection. - In this embodiment, where SPWR equal "H" and SPER equal "L" are output, then software data protection can be set. Where SPWR equal "L" and SPER equal "H" are output, the software data protection can be released. Further, where both SPWR and SPER become "L" during the period when software data protection is released, then the above ordinary operation can be performed for respective EEPROM cell in
cell matrix 2. Thelogic circuit 30 outputs the control signals SPWR and SPER when the address and data output from the external CPU (not shown) are input in a series of sequence as shown below. Namely, where thelogic circuit 30 receives (1) address=5555, data=AA, (2) address=2AAA, data=55 and address=5555, data=AO in sequence, it outputs SPWR="H" and SPER="L" for setting the software data protection. Where thelogic circuit 30 receives (1) address=5555, data=AA, (2) address = 2AAA, data = 55, (3) address = 5555, data = 80, (4) address = 5555, data=AA, (5) address = 2AAA,data 55, and (6) address=5555, data=20 in sequence, it outputs SPWR="L" and SPER="H" for releasing the software data protection. - In the ordinary operation SPWR = "L" SPER = "L" are output.
- The address and data for setting the software data protection can be provided such that in address is received upon a fall of WE , and data is received upon a right of WE as shown in Figure 5. The address and data for releasing software data protection can be provided such that the address is received upon a fall of WE and the data is received upon the rise of WE .
- Write erase
control circuit 31 comprisesNAND circuit 36 for outputting write control signal SPWR andNAND circuit 37 for outputting erase control signal SPER . Such one input terminal ofNAND circuit 36 receives a reverse signal SPS of the output signal SPS oflatch circuit 34 designating whether the software data protection state is set or is released. (When software data protection state is set, the signal SPS is at "H" and when it is released, the signal SPS is at "L".) The other input terminal ofNAND circuit 36 receives the signal SPWR oflogic circuit 30.NAND circuit 37 receives the output signal SPS oflatch circuit 34 at one input terminal and receives the output signal SPER fromlogic circuit 30 at the other input terminal. -
NAND circuit 36 outputs SPWR ="L" (write instruction signal= signal for setting logic "0" in EEPROM 40) to write erasecircuit 32, only when SPWR output fromlogic circuit 30 is at "H", namely, only when the address and data for setting the software data protection is input to thelogic circuit 30 during the period of SPS = "H", namely, the release of the software data protection.NAND circuit 36 outputs SPWR = "H" (non-write instruction) in the case other than described above.NAND circuit 37 outputs SPER'= "H" (erase instruction signal = signal for setting logic "1 " in EEPROM 40) to write erasecircuit 32 and outputs SPER "H" (non erase construction signal) in the case other than described above. A write and erasecircuit 32 has one and the other input terminals connected to the output terminal ofNAND circuit other output terminals 32W and 32E connected to drain 40d ofEEPROM cell 40 and control gate 40g thereof. Write erasecircuit 32 outputs increased voltage VPP (V) and 0(V) to theoutput terminal 32W and 32E, respectively upon SPWR "L" and SPER= "H" and performs a write operation forEEPROM cell 40 to set logic "0" inEEPROM 40. Upon SPWR' = "H" and SPER' = "L", write and erasecircuit 32 outputs 0(V) and increased voltage VPP(V) tooutput terminals 32W and 32E, respectively to perform an erase operation forEEPROM cell 40, thereby settingEEPROM cell 40 at logic "1". Write erasecircuit 32 outputs 0(V) tooutput terminals 32W and 32E where SPWR' = "L" and SPER' = "L" in write mode in the above ordinary operation. - Storing
unit 33 comprisesnMOS EEPROM cell 40 as shown in Figure 4.nMOS 38 is a selection transistor for controlling a read of data stored inEEPROM cell 40 and has the drain connected topower source line 41 and has the gate connected to read control circuit input terminal 42 for receiving read control signal SG and has the source connected to the drain andnMOS 39.nMOS 39 forms a load ofEEPROM cell 40 and has the gate and source connected to each other and has the connection point connected to the drain ofEEPROM cell 40.nMOS 39 comprises nMOS of depletion type. The source ofEEPROM cell 40 is grounded in the drawing but is made floating upon writing of the data. - In Figure 4
nMOS 38 operating as a selection transistor is provided on the side of the power source voltage Vcc and by reversing the connection relation betweennMOS 38 andload transistor nMOS 39,load transistor nMOS 39 may be provided on the side of the power source voltage Vcc.Latch circuit 34 latches the current memory data (logic state) of EEPROM cell and outputs signals SPS and SPS toNAND circuits NAND circuit inverters circuit 49.NAND circuit 43 has one input terminal connected to the drain ofEEPROM cell 40 and the output terminal connected to one input terminal ofNAND circuit 45 and one input terminal ofNAND circuit 44. - NOR
circuit 49 has one and the other input terminals connected to theoutput terminals logic circuit 30, respectively, and has the output terminal connected to the other input terminal ofNAND circuit 43 and the other input terminal ofNAND circuit 44.NAND circuit 45 has the other input terminal connected to an output terminal ofNAND circuit 46 and input terminal ofinverter 48 and has the output terminal connected to one input terminal ofNAND circuit 46 and the input terminal ofinverter 47. -
NAND circuit 46 has the other input terminal connected to an output terminal ofNAND circuit 44.Inverter 47 has the output terminal ( SPS output) connected to one input terminal of NAND.circuit 37 of write erasecontrol circuit 31. Inverter 48 (SPS output) connected to one input terminal ofNAND circuit 36 of write erasecontrol circuit 31. - When the
EEPROM cell 40 stores logic "0" (conductive state), i.e., where the software data protection state is set, SPS = "H" and SPS = "L" are output. When theEEPROM cell 40 stores logic "1" " (non conductive state), i.e., where the software data protection state is released, SPS = "L" and SPS = "H" are output. The write erasecircuit 32 performs a write operation to theEEPROM cell 40 and sets logic "0" (conductive state) in it. Thereafter, thelogic circuit 30 outputs SPWR="L" and SPER="L", reads the stored data (logic "0") newly set in the EEPROM cell and outputs the stored data to one input terminal ofNAND circuit 43 of thelatch circuit 34. Then, both SPWR and SPER are set at "L", the output ofNAND circuit 49 becomes "H" and the stored data (logic "0") read from theEEPROM cell 40 is latched atlatch circuit 34, thereby enabling SPS = "H" and SPS = "L" to be output fromlatch circuit 34. - The write erase
circuit 32 performs an erase operation on theEEPROM cell 40 and sets logic "1 " in it. Thereafter,logic circuit 30 outputs SPWR = "L" and SPER = "L" and reads the stored data (logic "1 ") newly set in theEEPROM cell 40 through the write erasecontrol circuit 31 and the write erasecircuit 32. The stored data is output to one input terminal ofNAND circuit 43 of thelatch circuit 34 and is latched in thelatch circuit 34, thereby enabling SPS = "L" and SPS = "H" to be output from it. - The increased voltage
generating control circuit 35 outputs increased voltage generating control signal VPACT to control the oscillation operation of thering oscillator 22 of the voltage increase clocksignal generating circuit 15 and comprises a NORcircuit 50,NAND circuits 51, 52 and aninverter 53. One and the other input terminals of the NORcircuit 50 are connected to oneoutput terminal 30W and theother output terminal 30E of thelogic circuit 30, respectively. One or the other input terminal of the NAND circuit 51 are connected to the output terminals ofinverter 47 and the NORcircuit 50. One input terminal of theNAND circuit 52 is connected to the output terminal of the NAND circuit 51. The other input terminal of theNAND circuit 52 receives write signal WR (which becomes "H" during a normal write mode) which is produced by a control circuit (not shown) in the EEPROM and is used for the EEPROM. The output terminal of theNAND circuit 52 is connected to the input terminal of theinverter 53 and the output terminal of theinverter 53 is connected to the other input terminal of theNAND circuit 17 of the voltage increase circuit clocksignal generating circuit 15. -
- As is clear from this table, where SPS = "H", i.e., when the software data protection state is set, and further, where SPWR="L" and SPER="L", i.e., the write mode in the normal operation, is set VPACT= "L". Therefore, in this case the
ring oscillator 22 of the voltage increase circuit clocksignal generating circuit 15 stops the oscillation operation. Therefore, the increased voltage VPP used for data erase and write for respective EEPROM cells in thecell matrix 2 is not output from thevoltage increase circuit 16. This prevents data from being written in the EEPROM cell inmatrix 2. On the other hand, where the software data protection state is set, either SPWR or SPER is made "H" and the address and data for setting and releasing the software data protection state is input to thelogic circuit 30. When the write data is supplied to thecell matrix 2, or where SPS="L", i.e., the software data protection state is released, VPACT="H". Regardless of the address of the logic state of SPWR and SPER. In this case, thering oscillator 22 of the voltage increase clocksignal generating circuit 15 performs an oscillation and increased voltage VPP is output from thevoltage increase circuit 16. Therefore, data write and erase to thecell matrix 2 becomes possible. - As described above, the present embodiment can realize a software data protection function by writing and storing logic "0" in the
EEPROM cell 40. -
- Even if SPS = "H" in write mode, i.e., the state of the software data protection is set. the
logic circuit 30 outputs SPWR="H" and SPER="L" to set the software data protection. However, the voltages atoutput terminals 32W and 32E of the write erasecircuit 32 are made 0(V), the write operation, i.e., the write of logic "0" for setting the software data protection is not performed for theEEPROM cell 40 in which logic "0" has already been stored. - In other words, when the logic state "0" for setting the software data protection is already stored in the
EEPROM cell 40, even if SPWR="H" for setting the software data protection is output from thelogic circuit 30, SPS = "L" is input to one input terminal of theNAND circuit 36 of write erasecontrol circuit 31. Thus, SPWR , applied to the write erasecircuit 32, is maintained at "H" (non-write instruction signal) and the write erasecircuit 32 does not write the logic "0" (for setting the software data protection) inEEPROM cell 40. That is, when theEEPROM cell 40 stores the logic "0" for setting the software data protection, the operation of writing logic "0" in theEEPEOM cell 40 again is prevented. - Where SPS="L" in write mode, namely, where the software data protection state is released, even if SPWR = "L" and SPER = "H", the voltage of the
output terminals 32W and 32E of the write erasecircuit 32 are made 0(V). Thus, the erase operation, namely, the operation of writing logic "1", is not performed forEEPROM cell 40, in which logic "1 " is already stored. - In other words, when the logic state "1" for releasing the software data protection is already stored in the
EEPROM cell 40, even if SPER = "H" for releasing the software data protection is output from thelogic circuit 30, SPS="L" is input to one input terminal ofNAND circuit 37 of the write erasecontrol circuit 31. Thus, SPER , applied to the write erasecircuit 32 is maintained at "H" (non-erase instruction signal) and thus the write erasecircuit 32 does not write logic "1 " (for releasing the software data protection) inEEPROM cell 40. That is, when theEEPROM cell 40 stores logic "1" for releasing the software data protection, the operation of writing logic "1 " in it again is prevented. - The present embodiment reads and stores in
latch circuit 34 the logic state (store data) ofEEPROM cell 40 which stores a setting state or releasing state of the software data protection, every time a switching operation for setting or releasing the software data protection is conducted. Then, the present embodiment prevents the same logic state as that stored in theEEPROM cell 40 from being set therein by using the write and erasecontrol circuit 31, based on the signals SPS and SPS for setting and releasing the software data protection and output from thelatch circuit 34. Thus, unnecessary write and erase operations conventionally conducted for theEEPROM cell 40 can be avoided. - This decreases the number of write and erase operations to the
EEPROM cell 40 and thus preventing its deterioration and maintaining its function for a long time. - The above embodiment can prevent the same data from being written into the
EEPROM cell 40 again. It can also prevent the erase operation from being performed again or repeatedly. It is operable even if only repeated writing of the same data intoEEPROM cell 40 is prevented. This case can achieve almost the same effect as the above embodiment although its advantage is not as great. - Figure 7 shows a detailed circuit structure of the
logic circuit 30. As shown in Figure 7, thelogic circuit 30 comprises five flip-flops inverter 354 of flip-flop 350 in the last stage is connected to one input terminal of fourinput NAND circuits - The above five flip-
flops circuits flip 310. - Flip-
flop 310 is a reset flip-flop (called R-S-FF hereinafter) comprising aNAND circuit 311,NAND circuit NAND circuit 312, aninverter circuit 314 whose input terminal is connected to the output terminal ofNAND circuit 312, and aninverter 315 whose input terminal is connected to the output terminal ofNAND circuit 312. The output ofinverter 314 is connected to one input terminal ofNAND circuit 323 of flip-flop circuit 320 in the next stage, thereby forming a serial connection of flip-flop circuit 310 and flip-flop circuit 320. Flip-flop circuits NAND circuits flop circuits inverter 1407 to reset flip-flop circuits flop circuit 310 is connected to power source voltage Vcc (5V) and is normally kept at "H". The other input terminal is connected to the output terminal ofinverter 401. The output terminal of inverter 361 is also connected to the other input terminal ofNAND circuit 353 of flip-flop 350. -
Address selection circuit 400 receives 15 address signals A0-A14 and a control signal PRAD output from a control unit not shown.Address selection signal 400 comprisesNAND circuit 409 for receiving address signals Ao and A2 and address signals Ai and A3 throughrespective inverters NAND circuit 410 for receiving address signals A4 and As and address signals As and A7 throughrespective inverters NAND circuit 411 for receiving address signals As and A10 and for receiving address signals As and A" throughrespective inverters 406 and 407 andNAND circuit 412 for receiving address signals A12 and A14 and for receiving address signals PRDD and A12 through theinverter 408. It further comprises NAND circuit 417 for receiving the outputs ofNAND circuits respective inverters inverter 401 for providing the output to the other input terminal of NAND circuit 417.Address selection circuit 400 turns the output ofinverter 401 to "H" only when the 16-bit address comprising address signals Ao to A14 and signal PRAD becomes "5555", thereby providing "H" toNAND circuit 313 of flip-flop circuit 310. -
Data selection circuit 500 receives 8-bit data signals Do-D7 and output signal PRDD of a control unit not shown and comprisesNAND circuit 506 for receiving data signals Do and D2 and for receiving data signal D, throughinverter 502,NAND circuit 507 for receiving data signal D4 and for receiving data signals D3 and D5 through resepctive inverters 503 and 504, andNAND circuit 508 for receiving data signal D6 and signal PRDD, and data signal D7 through inverter 505. - It further comprises
NAND circuit 512 for receiving the outputs ofNAND circuits respective inverters inverter 501 for receiving the output ofNAND circuit 512 and providing the output to the other input terminal ofNAND circuit 323 of flip-flop circuit 320. - The
data selection circuit 500 turns the output ofinverter 501 to "H" only when data signals Do-D7 become "AA" and the signal PRDD becomes "H", thereby providing "H" signal toNAND circuit 323 of flip-flop circuit 320. -
Address selection circuit 600 receives 15 address signals A0-A1 and a control signal PRAD of a control unit not shown in the same manner as inaddress selection circuit 400.Address selection signal 600 comprisesNAND circuit 610 for receiving address signal A2 and address signals Ao, A, and A3 throughrespective inverters NAND circuit 611 for receiving address signals A4 and A6 and address signals As and A7 throughrespective inverters NAND circuit 612 for receiving address signals As and A,o and for receiving address signals As and A11 throughrespective inverters 607 and 608, andNAND circuit 613 for receiving address signals A12 and A1 and for receiving the signal PRAD and the address signal A12 through theinverter 609. It further comprisesNAND circuit 618 for receiving the outputs ofNAND circuits respective inverters NAND circuit 618 and for providing the output toNAND circuit 333 in flip-flop circuit 330.Address selection circuit 600 turns the output of inverter 601 to "H" only when the 16- bit address comprising address signals Ao to A15 and signal PRAD becomes "2AAA(H), thereby providing "H" toNAND circuit 333 of the flip-flop circuit 330. - Data selection circuit 700 receives 8-bit data signals Do-D7 and control output signal PRDD of a control unit not shown and comprises
NAND circuit 707 for receiving data signal D1 and for receiving data signals Do and D2 throughinverters 702 and 703,NAND circuit 708 for receiving data signals D3 and D5 and for receiving data signals D4 throughresepctive inverter 710, andNAND circuit 709 for receiving data signal D7 and control signal PRDD and for receiving data signal 6 throughinverter 708. - It further comprises
NAND circuit 713 for receiving the outputs ofNAND circuits respective inverters inverter 701 for receiving the output ofNAND circuit 713 and providing the output to the other input terminal ofNAND circuit 343 of flip-flop circuit 340. - The data selection circuit 700 turns the output of
inverter 701 to "H" only when data signal Do-D7 becomes "55" and the control signal PRDD becomes "H", thereby providing "H" signal to the other input terminal ofNAND circuit 343 of flip-flop circuit 340. - The logic circuit further comprises
data selection circuits 800, 900 and 1000, which receive 8-bit data signals Do-D7 and control signal PRDD in the same asdata selection circuit 500 and 700. -
Data selection circuit 800 comprisesNAND circuit 807 for receiving data signals Do and D2 and for receiving data signal D1 throughinverter 802,NAND circuit 808 for receiving data signal D4 and for receiving data signals D3 and Ds throughinverters NAND circuit 809 for receiving control signal PRDD and for receiving data signals Ds and D7 throughresepctive inverters -
NAND circuits NAND circuit 801 throughrespective inverters NAND circuit 801 is supplied to one input terminal ofNAND circuit 1101 of flip-flop circuit 1100 and three-input NAND circuit 1401 - The
data selection circuit 800 produces the output "H" fromNAND circuit 801, only when the 8-bit data signal comprising data signals Do to D7 becomes "AO" and control signal PRDD becomes "H". - Data selection circuit 900 comprises
NAND circuit 909 for receiving data signal Do and for receiving data signals D, and D2 throughrespective inverters NAND circuit 910 for receiving data signals D3, D4. and Ds throughrespective inverters 904, 905 and 906 andNAND circuit 911 for receiving control signal PRDD and for receiving data signals D6 and D7 throughrespective inverters NAND circuit 901 for receiving the output ofNAND circuits respective inverters NAND circuit 901 is input toNAND circuit 1401. The data selection circuit 900 produces the output "H" fromNAND circuit 1001 only when the 8-bit data comprising data signals Do to D7 becomes "20" and control signal PRDD becomes "H", thereby providing "H" signal toNAND circuit 1401. - Data selection circuit 1000 comprises
NAND circuit 1009 for receiving data signal D2 and for receiving data signals Do and D, throughinverters 1002 and 1003,NAND circuit 1010 for receiving data signals D3, D4 and D5 throughinverters NAND circuit 1011 for receiving signal PRDD and for receiving data signal Ds and D7 throughinverters NAND circuit 1001 for receiving the outputs ofNAND circuits respective inverters NAND circuit 1001 is applied to one input terminal ofNAND circuit 1201 in flip-flop circuit 1200 andNAND circuit 1401. - Data selection circuit 1000 produces the output "H" from
NAND circuit 1001 only when data signals Do-D7 become "20" and controls signal PRDD becomes "H", thereby providing "H" toNAND circuit 1401 and to one input terminal ofNAND circuit 1201 of flip-flop circuit 1200. - NOR
circuit 1402 has one input terminal connected to the output terminal ofNAND circuit 1401 and the other input terminal receive signal INT of a falling pulse upon a rise of the power source Vcc after the signal INT is inverted byinverter 1408. -
Inverter 1403 inverts the output ofinverter 1408, signal INT , and provides the output to the other input terminal ofNAND circuit 1102 of flip-flop circuit 1100 and to the other input terminal ofNAND circuit 1202 of flip-flop circuit 1200. The output terminal of NORcircuit 1402 is directly connected to one input terminal ofNAND circuit 1406 and is connected to the other input terminal ofNAND circuit 1406 throughinverters NAND circuit 1406 forms the signal SRST throughinverter 1407 so that the signalSRST is input to one input terminal ofNAND circuit 311 in flip-flop circuit 310. - Flip-
flop circuit 1100 comprises an R-S-FF formed ofNAND circuits inverter 1103 for inverting the output ofNAND circuit 1101 andinverter 1104 for inverting the output ofNAND circuit 1102 and providing the output ofinverter 1104 to write erasecontrol circuit 31 shown in Figure 4 as the write control signal SPWR. - Flip-
flop circuit 1200 comprisesNAND circuits NAND circuit 1201 and inverter 1204 for inverting the output ofNAND circuit 1202. The output of inverter 1204 is supplied to write erasecontrol circuit 31, shown in Figure 4 as erase control signal SPER. - In the above structure of
logic circuit 30, address signals Ao-Ais and data signals Do-D7 are respectively supplied through an address bus and a data bus from an external control circuit (comprising a micro processor, for example), not shown. - The operation of
logic circuit 30 will be explained sequentially as follows. - When the power source Vcc rises, the signal INT falls, thereby producing a falling pulse. This causes the output signal SRST of
inverter 1407 to also become a falling pulse, similar to the signal INT. When the signal from "H" to "L" then fall, flip-flop circuits 3010, 3020, 3030, 3040 and 3050, connected in series, are reset and outputs OUT1, OUT2, OUT3, OUT4 and SPINT from the flip-flop circuits become "L". The control signal PRDD is kept at "H". The explanation will be made for the case where write control signal SPWR is set at "H" and erase control signal SPER is set at "L" to set the software data protection. In this case, - (1) when the address signal "5555" is output on the address bus, data signal "AA" is output on the data bus.
- (2) when address signal "2AA" is output on the address bus, data signal "55" is output on the data bus.
- (3) and finally, when the address signal "5555" is output on the address bus, data signal "AO" is output on the data bus.
- By sequentially outputting the address signals and data signals on the address bus and data bus in the order (1), (2) and (3), the output SPW of
NAND circuit 801 ofdata selection circuit 800 changes from "H" to "L" and then output signal SPWR of flip-flop circuit 1100 becomes "H". At this time, the output signal SPE of data selection circuit 1000 is kept at "H" and flip-flop circuit 1200 provides the "L" of the output signal SPER. - The address signals "5555" in the above (1), changes the output of
inverter 401 ofaddress selection circuit 400 from "L" to "H" so that "H" is input to the other input terminal ofNAND circuit 313 of flip-flop circuit 310. Thus, output signal OUT1 of flip-flop circuit 310 becomes "H" and is input to one input terminal ofNAND circuit 312 of flip-flop circuit 320 in the next stage. A further data signal "AA", the output ofinverter 501 ofdata selection circuit 500 from "L" to "H", is output in the above (1), thereby providing "H" to the other input terminal ofNAND circuit 323 of flip-flop circuit 320, and outputting signal OUT2 of flip-flop circuit 320 to be provided to one terminal ofNAND circuit 333 of flip-flop circuit 330 in the next stage. - Next, when address signal "2AAA" and data signal "55" in the above (2) are output, output signal OUT3 of flip-flop circuit 330 and output signal OUT4 of flip-
flop circuit 340 sequentially become "H", in the same manner as described above. Further, as described in (3) above, when address signal "5555" is output, the output signal SPINT of flip-flop circuit 350 becomes "H" and "H" is input toNAND circuit 801 ofdata selection circuit 800. Then, as described (3) above, when data signal "AO" is output, output signal SPW ofdata selection circuit 800 changes from "H" to "L" and output signal SPWR ofinverter 1104 of flip-flop circuit 1100 becomes "H", so that the output signal SPWR is provided to the write erasecontrol circuit 31. However, the output signal SPE ofNAND circuit 1001 of data selection circuit 1000 is kept at "H", and output signal SPER of inverter 1204 of flip-flop circuit 1200 is kept at "L", so that "L" is applied to write erasecontrol circuit 31. Therefore, the address signal and data signal are output in the order (1) to (3) above and SPWR = "H" and SPER = "L" are output through write erasecontrol circuit 31. Thus, write erasecontrol circuit 31 controls write erasecircuit 32 as described before, so that the logic "0" designating the setting of the software data protection is written inEEPROM cell 40 in storingunit 33, shown in Figure 4. - Next, the case where write control signal SPWR is set at "L" and erase control signal SPER is set at "H" to remove the software data protection will be explained. In this case,
- (1) when address signal "5555" is output on the address bus, data signal "AA" is output on the data bus.
- (2) when address signal "2AAA" is output on the address bus, data signal "55" is output on the data bus.
- (3) when address signal "5555" is output on the address bus, data signal "80" is output on the data bus.
- (4) when address signal "5555" is output on the address bus, data signal "AA" is output on the data bus.
- (5) when address signal "2AAA" is output on the address bus, data signal "55" is output on the data bus, and
- (6) when address signal "5555" is output on the address bus, data signal "20" is output on the data bus.
- When address signals and data signals are output on the address bus and data bus, respectively, in the order (1) to (6) as described above, the address signals and the data signals, as described in (1) to (3) above, set the outputs of flip-
flop circuits flop circuit 1200 becomes "H". At this time, the output signal SPW ofdata selection circuit 800 is kept at "H" and the output signal SPWR from flip-flop circuit 1100 becomes "L". - That is, the address signal "5555" and data signal "AA" described in (1) above sequentially set the output OUT1, OUT2 of flip-
flop circuits flop circuits 330 and 340 to "H". Further, address signal "5555" described in (3) above, sets the output signal SPINT of flip-flop circuit 350 at "H" and then when data signal "80" is output, output signal SPR ofNAND circuit 901 of flip-flop circuit 900 changes from "H" to "L". Therefore, the output ofNAND gate 1401 becomes "H" and the output SRST ofinverter 1407 changes from "H" to "L". As the output S RST changes from "H" to "L", all the outputs of flip-flop circuits - The address signals and data signals are sequentially output in the above (4) and (5) in the same way as in (1) and (2) above. Thus, the output OUT4 of flip-
flop circuit 340 becomes "H". Next, in (6) above, address signal "5555" is output. Thus, the output signal SPINT of flip-flop circuit 350 becomes "H" and a further data signal "20" is output. Thus, the output signal SPE of flip-flop circuit 1000 changes from "H" to "L", but output signal SPW of flip-flop circuit 800 is maintained at "H". Therefore, the output signal SPWR of flip-flop circuit 1100 is set at "L" and the output signal SPER of flip-flop circuit 1200 is set at "H". These output signals SPWR and SPER are input to write erasecontrol circuit 31. As the address signals and data signals are output in the order shown in (1 )-(6), write erasecontrol circuit 31 receives SPWR = "L" and SPER = "H", thereby enabling write erasecontrol circuit 31 to enable write erasecircuit 32 to write logic "1 intoEEPROM cell 40 of storingunit 33 in order to remove the software data protection. - Figure 8 shows the detailed circuit structure of the write erase
control circuit 31, the write erasecircuit 32, the storingunit 33 and thelatch circuit 34 shown in the embodiment shown in Figure 4. - The write erase
circuit 32 comprises awrite circuit 32a and an erasecircuit 32b. - First, in the following explanation, the transistor, not specifically recited as being of the depletion type, is of the enhancement type. Write
circuit 32a comprisesPMOS 3201,nMOS 3202 andnMOS 3203 connected in series between power source voltage Vcc and the ground,MOS capacitor 3204 connected between the source ofPMOS 3201 and the drain ofnMOS 3202,nMOS 3205 of the depletion type connected to the other terminal ofMOS capacitor 3204 and whose gate and drain are connected,PMOS 3206 having its source and gate respectively connected to the drain and source ofnMOS 3205 and having its drain connected to the power source Vpp,PMOS 3207 having its gate connected to the source ofdepletion type nMOS 3205 and its source connected to the power source voltage Vpp,PMOS 3208 having its drain commonly connected to the drain ofPMOS 3207 and its source connected to ground,inverter 3209 having the output ofNAND gate 36 of the write erasecontrol circuit 31 connected to the input terminal and having the output PN connected to the gate ofPMOS 3203 and to the drain oftransfer gate 3210, NORcircuit 3211 for receiving the output PW ofinverter 3209 and for receiving the output PR ofinverter 3301 in the storingunit 33.MOS capacitor 3212 has one of its terminals connected to the output terminal of NORcircuit 3211 and the other connected to ground. The gates ofPMOS 3201 andnMOS 3202 receive a clock signal SCLK of a predetermined duty ratio. This signal is generated from a clock generator, not shown, which operates when an "H" of write control signal SPWR is transmitted, and the source oftransfer gate 3210 is connected to the source ofnMOS 3205 of the depletion type and the gate ofnMOS 3207 and ofnMOS 3206. The gate oftransfer gate 3210 is connected to the power source voltage Vcc. - Erase
circuit 32b has a similar configuration to that ofwrite circuit 32a. - Erase
circuit 32b comprisesPMOS 4201.nMOS 4202, andnMOS 4203 which are connected in series between power source voltage Vcc and the ground,MOS capacitor 4204 connected between the source ofPMOS 4201 and the drain ofnMOS 4202,nMOS 4205 of the depletion type connected to the other terminal ofMOS capacitor 4204 and whose gate and drain are connected,PMOS 4206 whose source and gate are respectively connected to the drain and source ofnMOS 4205 and whose drain is connected to the power source voltage Vpp,PMOS 4207 whose gate is connected to the source ofdepletion type nMOS 4205 and whose source is connected to the power source voltage Vpp,inverter 4209 having an input connected to the output ofNAND gate 37 of write erasecontrol circuit 31 and whose output PE is connected to the gate ofPMOS 4203 and to the drain oftransfer gate 4210,inverter 4211 for outputting the reverse output of output PE ofinverter 4209 to a gate ofPMOS 3302 in the storingunit 33. The gates ofPMOS 4201 andnMOS 4202 receive a clock signal SCLK of a predetermined duty ratio and generated from a clock generator, not shown, which operates upon an "H" of erase control signal SPER. The source oftransfer gate 4210 is connected to the source ofnMOS 4205 of the depletion type and the gate ofnMOS 4207 ofnMOS 4206. The gate oftransfer gate 4210 is connected to the power source voltage Vcc. - Next, the configuration of storing
unit 33 is explained.EEPROM cell 40 comprises 2EEPROM cell nMOS 3303 and nMOS 3304 connected in series between the power source voltage Vcc and the ground. The source ofEEPROM cell 40 is connected to the source ofnMOS 3303 and the drain of nMOS 3304. Storingunit 33 further comprises PMOS 3305 and nMOS 3306 connected in series between the power source voltage Vcc and ground. Output PW ofinverter 3209 ofwrite circuit 32a are applied to the gates of nMOS 3305 and nMOS 3306. The source of PMOS 3305 and the drain of nMOS 3306 are connected to the gate of nMOS 3304.PMOS 3307 andPMOS 3308 of OR connection,nMOS 39 of the depletion type,nMOSs nMOS 3310 are connected between the drain ofEEPROM cell 40 and the power source voltage Vcc. The gate ofnMOS 3310 receives the output PE ofinverter 4209 of erasecircuit 32b and the output PW ofinverter 3209 ofwrite circuit 32a through NORcircuit 3311. The source ofdepletion type nMOS 39 is connected toinverter 3312 and the output ofinverter 3312 is inverted byinverter 3313. It is also connected to one input terminal ofNAND circuit 43 oflatch circuit 34. Storingunit 33 further comprisesPMOS 3314,depletion nMOS 3315,nMOS 3316 and OR connectednMOSs depletiontype nMOS 3315 andnMOS 3316 are connected to the drain ofdepletiontype nMOS 315. The gate of PMOS 3214 receives the signal INT throughinverters inverter 3301 is input to NORcircuit 3211 ofwrite circuit 32a. The output ofinverter 3319 is input to the gates ofnMOS 3318 andPMOS 3307. Further,nMOS 3320,nMOS 3302 andnMOS 3321 are connected in series between the power source voltage Vcc and the ground. The gate ofnMOS 3320 is connected to the drain ofdepletiontype nMOS 3315. The drain ofdepletiontype nMOS 3315 is connected to nMOS 3322 and the other terminal is grounded. The gate of nMOS 3322 receives the other output ofinverter 3319. Therefore, the gates ofnMOS 3321, nMOS 3322 andnMOS 3318 are connected to the output terminal ofinverter 3319 and the source ofnMOS 3320 is connected to the gate ofEEPROM cells nMOS 4207 of erasecircuit 32b. - The operations of respective modes comprising a mode for reading data from EEPROM cell 40 (reading mode), a mode for writing the storing data into EEPROM (writing mode) a mode for erasing the stored data from EEPROM (erasing mode), and a mode for writing and reading the data into and from respective EEPROMs in cell matrix (normal mode), are described as follows.
- The reading mode is carried out when the power source voltage Vcc is applied the apparatus body or the write or erase of the stored data (logic state) is performed for
EEPROM cell 40 by write erasecircuit 32. - First, the signal INT produces a fall pulse. During the period "L" of the signal INT , "L" is applied to respective gates of
PMOS 3314,PMOS 3307,nMOS 3318,nMOS 3321 and nMOS 3322 throughinverters PMOSs PMOS 3314 is turned on,nMOS 3316 is turned on throughnMOS 3315 of the depletion type and whennMOS 3316 is turned on,nMOS 3317 is also turned on. The source voltage of thedepletion type nMOS 3315 becomes about 2V and is applied to the gates ofnMOS 3320 andnMOS 38. As a result, bothnMOS 3320 andnMOS 38 become "ON". - At this time, as signal SPER is set at "L", the output of
NAND circuit 37 becomes "H". Further the output PE ofinverter 4209 turns to "L" and is applied to the gate ofnMOS 4203, thereby turning offnMOS 4203. The output PE ofinverter 4209 is reversed byinverter 4211 and "H" is applied to the gate ofnMOS 3302, thereby turning onnMOS 3302. Further, the output PE ("L") ofinverter 4209 is applied to respective gates ofnMOSs transfer gate 4210, thereby turning offnMOSs - Further, as signal SPWR is set at "L", the output of
NAND circuit 36 becomes "H" and the output PW ofinverter 3209 becomes "L" and is applied to the gate ofnMOSs nMOS 3203, one terminal of NORcircuit 3211 andtransfer gate 3210, thereby turning offnMOSs inverter 3301 is at "H', the output of NORcircuit 3211 becomes "L" and is applied to the gate ofnMOS 3208. - As described above, respective outputs PE and PW of
inverters circuit 3211 becomes "H" and is applied to the gate ofnMOS 3310, thereby turning onnMOS 3310. - Therefore, as the output PW of
inverter 3209 turns to "L", PMOS 3305 turns on andnMOS 3303 and nMOS 3306 turn off. Thus, the source voltage of PMOS 3305 becomes "H" and is applied to the gate of nMOS 3304, thereby turning on nMOS 3304. - Therefore, as
nMOS 3320 is turned on,nMOS 3321 andnMOS 4207 are turned off, and about 2V is applied to the gate ofEEPROM cells EEPROM cells PMOS 3307,depletiontype nMOS 39nMOS 38 andnMOS 3310 are turned on, respective drains ofEEPROM cells - In this case, if
EEPROM cells EEPROM cells EEPROM cells inverter 3312. - On the other hand, when
EEPROM cells EEPROM cells depletion type nMOS 39 is applied toinverter 3312. Therefore, whenEEPROM cell 40 is set at logic "0", "L" is applied to one input terminal ofNAND circuit 43 oflatch circuit 44 throughinverters circuit 49 becomes "H" and is applied to the other input terminal ofNAND circuit 43. Therefore, the output "L" ofinverter 3313 is latched atlatch circuit 34 and the output SPS oflatch circuit 34 is set at "H". - When
EEPROM cell 40 is set at logic "1", "H" is applied to one input terminal ofNAND circuit 43 oflatch circuit 34 throughinverters latch circuit 34 and thus the output SPS oflatch circuit 34 is set at "L". - According to the write mode, a logic "0" is set in
EEPROM cells EEPROM cells - This write mode operation is performed only when SPWR = "H", SPER = "L" and SPS="H" (SPS="L"), i.e., logic "1" is currently set in
EEPROM cells - At this time, as
SPS = "H" and SPWR = "H", the output ofNAND circuit 36 becomes "L". As a result, the output PW ofinverter 3209 turns to "H". As the signalINT is "H", the output PR ofinverter 3301 is "L". Therefore, the output of NORcircuit 3311 becomes "L" and is applied to the gate of thenMOS 3208, thereby turning offnMOS 3208. As the output PW("H") ofinverter 3209 is also applied tonMOS 3203,nMOS 3203 is turned on. When SPWR becomes "H", clock SPLK with a predetermined frequency is applied from the not-shown clock generator to the gate ofPMOS 3201 andnMOS 3202. Therefore,PMOS 3201 andnMOS 3202 repeat an on and off operation alternatelyin accordance with clock SCLK. Therefore. one terminal ofMOS capacitor 3204 is set at about 5V (power source voltage Vcc) whenPMOS 3201 is turned on, and it is set at about 0V (ground voltage) whennMOS 3202 andnMOS 3203 are on. Thus.the voltage of one terminal ofnMOS capacitor 3204 varies alternately. The output PW ("H") ofinverter 3209 is applied to respective gates ofnMOS 3206andS 3207 throughtransfer gate 3210, thus ng onnMOS nMOS 3206 is applied to the drain and source ofdepletion type nMOS 3206 and the other terminal ofnMOS capacitor 3204. Therefore,MOS capacitor 3204 is gradually charged up to the power source voltage Vpp (about 20V). Therefore, when the voltage ofMOS capacitor 3204 increases to the power source voltage Vpp (about 20V), the source voltage ofdepletion type nMOS 3205 becomes about 20V. Thus, the gate voltage ofnMOS 3206 andnMOS 3207 becomes about 20V. Therefore, the power source voltage Vpp (about 20V) is applied to the drain ofEEPROM cells nMOS 3207. - When both SPER and SPS are set at "L", the output of
NAND circuit 37 becomes "H", thereby setting the output PE ofinverter 4209 at "L". The output PE ("L") ofinverter 4209 is applied tonMOS transfer gate 4210. As a result,nMOS inverter 4209 is reversed byinverter 4211 and it becomes "H", and is thereby applied to the gate ofnMOS 3302.nMOS 3302 is turned on. The output PR("L") ofinverter 3301 is inverted byinverter 3319 to "H" and is applied to respective gates ofPMOS 3314 andnMOSs PMOS 3314 is turned off and nMOS 3322 are turned on, thereby enabling "L" to be applied to the gate ofnMOS 3320 andnMOS 3316, thus turning offnMOSs - As described above,
nMOS 3320 andnMOS 4207 are turned off andnMOS 3302 andnMOS 3321 are turned on, thereby applying "L" to the gates ofEEPROM cells circuit 3311 is turned to "L" and "L" is aplied to the gate ofnMOS 3310. Therefore,EEPROM cell 40 is separated fromlatch circuit 34 bynMOS 3310. Further, as PW is set at "H", PMOS 3305 is turned off andnMOSs 3303 and 3306 are turned on and further PMOS 3305 is turned off, and nMOS 3306 is turned on, thereby turning off nMOS 3304. As a result, Vcc (about 5V) is applied to the source ofEEPROM cells - Therefore, about 0V is applied to the gates of
EEPROM cells EEPROM cells EEPROM cells EEPROM cells latch circuit 34 is fixed at "H" and SPS is fixed at "L". Therefore, in the later cycle, SPWR = "H" and SPER = "L" are set in order to set the software data protection state, the output ofNAND circuit 36 of write erasecontrol circuit 31 is kept at "H" and the output PW ofinverter 3209 ofwrite circuit 32a becomes "L". Therefore,nMOSs EEPROM cells EEPROM cells - According to this erase mode, logic "1" " is set at
EEPROM cells EEPROM cells - The operation of the erase mode is performed only when the release of the software protection state is requested (when SPWR = "L", SPER = "H" and SPS="H" (SPS="L")), i.e., only when the request for releasing the software data protection is made when the
current EEPROM cells - At this time, as SPS = "H" and SPER = "L", the output of
NAND circuit 37 becomes "L". As a result, the output PE ofinverter 4209 becomes "H" andnMOS 4203 is turned on. - When SPWR becomes "H", a clock SCLK with a predetermined frequency is applied from a clock generator (not shown) to the gate of
PMOS 4201 andnMOS 4202. Therefore,PMOS 4201 andnMOS 4202 alternately repeat an on and off operation in accordance with clock SCLK. Therefore, one terminal ofMOS capacitor 4204 is set at about 5V (power source voltage Vcc) whenPMOS 4201 is turned on and at about 0V (ground voltage) whennMOS nMOS capacitor 4204 varies alternately. The output PE ("H") ofinverter 4209 is applied to respective gates ofnMOS transfer gate 4210, turning onnMOSs nMOS 4206 is applied to the drain and source ofdepletion type nMOS 4206 and the other terminal ofnMOS capacitor 4204. Therefore,MOS capacitor 4204 is gradually charged up (to the power source voltage Vpp about 20V). Therefore, when the voltage ofMOS capacitor 4204 increases to the power source voltage Vpp (about 20V), the source voltage ofdepletion type nMOS 4205 becomes about 20V. Thus, the gate voltage ofnMOSs EEPROM cells nMOS 4207. - When both SPWR and SPS are set at "L", the output of
NAND circuit 36 becomes "H", thereby enabling the output PW ofinverter 3209 to be set at "L". The output PE ("L") ofinverter 3209 is applied tonMOSs transfer gate 3210. As a result,nMOSS inverter 3209 is applied to NORcircuit 3211. As INT = "H", the output PR ofinverter 3301 is turned to "L". Therefore, the output of NORcircuit 3211 becomes "H" and is applied to the gate ofnMOS 3208, thereby turning it on. - As described above, PE="H", PW="L", and the output of NOR
circuit 3211 becomes "L" and is applied tonMOS 3310, thereby turning offnMOS 3310. The drain ofEEPROM cells nMOS nMOS 3310. - The output PR("L") of
inverter 3301 is inverted byinverter 3319 to "H", and applied to respective gates ofPMOS 3314 andnMOSs result PMOS 3314 is turned off and nMOS 3322 is turned on. Thus, "1" " is applied to the gate ofnMOS 3320 andnMOS 3316, thereby turning both of them off.nMOS 3321 is also turned on. Further, the output PE("H") ofinverter 4209 is inverted byinverter 4211 to "L" and applied tonMOS 3302, thereby turning offnMOS 3302. - As described above, both
nMOS EEPROM cells nMOS 4207. - As described above, the output PW of
inverter 3209 become "L", PMOS 3305 is turned on, andnMOSs 3303 and 3306 are turned off. As PMOS 3305 is turned on, nMOS 3304 is turned on. Therefore, the sources ofEEPROM cells circuit 3211 is turned to "H",nMOS 3208 is turned on, thereby turning the drains ofEEPROM cells - Therefore, the gate of
EEPROM cells EEPROM cells - After
EEPROM cells EEPROM cells latch circuit 34 and output SPS oflatch circuit 34 is fixed at "L" and SPS is fixed at "L". Therefore, even if SPWR="L" and SPER="H" are set to remove the software data protection state again, the output ofNAND circuit 37 of write erasecontrol circuit 31 is turned to "H" and the output ofinverter 4209 of erasecircuit 32b is turned to "L". Therefore, bothnMOSs EEPROM cells EEPROM cells - According to this normal mode, read and write of the data for respective EEPROM cells in
cell matrix 2 are performed. The operation in this normal mode is not related to the subject of the present invention, but will be explained briefly. - In the normal mode, SPWR = "L" and SPER = "L" and INT is set at "H".
- As SPWR is set at "L", the output of
NAND circuit 36 become "H", regardless of whether SPS is set at "L" or "H", and PW ofinverter 3209 turns to "L", thereby turning offnMOSs - As SPER is set at "L", the output of
NAND circuit 37 is made "H" regardless of whether SPS is set at "L" or "H". As a result, the output PE ofinverter 4209 turns to "L" and is applied to reskpective gate ofnMOS inverters 4211, the gate ofnMOS 4203 andtransfer gate 4210. As a result,nMOS 4207 is turned off. Further, the output PE ofinverter 4209 is inverted to "H" byinverter 4211 and is applied to the gate ofnMOS 3302, thereby turning onnMOS 3302. - As the signal INT="H", the output PR of
inverter 3301 turns to "L". It is then inverted to "H" byinverter 3319 and applied to respective gates ofPMOSs nMOSs PMOSs nMOSs nMOS 3320 andnMOS 38 to be turned off. Therefore,nMOS 3320 is turned off andnMOSs nMOS 4207 is turned off, thereby enabling about 0V to be applied to the gate ofEEPROM cells - As output PW of
inverter 3209 is turned to "L", PMOS 3305 is turned on andnMOSs 3303 and 3306 are turned off. Further, PMOS 3305 turns on, thereby turning on nMOS 3304. Therefore,nMOS 3303 is turned off and nMOS 3304 is turned on, and the sources ofEEPROM cells - As described above, the PW and PER are set at "L" and the output of NOR
circuit 3211 becomes "H", thereby turning onnMOS 3208. Therefore, the drains ofEEPROM cells EEPROM cells EEPROM cells latch circuit 34 becomes "H" and the output ofinverter 3313 of storingunit 33 is latched atlatch circuit 34. In the normal mode, the potential at the node n2 betweeninverter 3212 and inverter 3213 is fixed at the logic level which is read fromEEPROM cells - In this case, as both PE and PW become "L", the output of NOR
circuit 3211 becomes "H" andnMOS 3310 turns on. Therefore, the source ofnMOS 3309 is at about 0V. - Where the logic level of the node N2 is at "H",
PMOS 3308 is turned off andnMOS 3309 is turned on. Therefore, L" is applied to the input terminal ofinverter 3312 throughnMOSs inverter 3312, namely, the potential of node N2, is again set to "H". - Where the logic level of node N2 is "L",
PMOS 3308 is turned on andnMOS 3309 is turned off. Therefore, the input terminal ofinverter 3212 receives "H" throughPMOS 3308 anddepletion type 39. Therefore, the output ofinverter 3312, namely, the potential of node N2, is again set at "L". Therefore, the potential of node N2 is fixed at the logic level which is read out from EEPROM cells in the read mode.
Claims (12)
1. An electrically erasable programmable non-volatile semiconductor memory device comprising:
an electrically erasable programmable non-volatile semiconductor memory element;
a software data protection circuit for storing and maintaining the setting state of the software data protection by setting one logic state in said electrically erasable programmable non-volatile semiconductor memory element where the address and data for setting the software data protection is input, and for storing and maintaining the releasing state of the software data protection by setting the other logic state in said electrically erasable programmable non-volatile semiconductor memory element where the address and data for releasing the software data protection is input, and
a logic state setting control circuit means for controlling an operation of setting the logic state of said erasable programmable non-volatile semiconductor memory element to prevent one logic state from being set again for said electrically erasable programmable non-volatile semiconductor memory element even if the address and data for setting the software data protection is input, where said electrically erasable programmable non-volatile semiconductor memory element is already set in one logic state.
2. An electrically erasable programmable non-volatile semiconductor memory device comprising:
an electrically erasable programmable non-volatile semiconductor memory element;
a software data protection circuit for storing and maintaining the setting state of the software data protection by setting one logic state in said electrically erasable programmable non-volatile semiconductor memory element where the address and data for setting the software data protection is input, and for storing and maintaining the releasing state of the software data protection by setting the other logic state in said electrically erasable programmable non-volatile semiconductor memory element where the address and data for releasing the software data protection is input, and
a logic state setting control circuit means for controlling an operation of setting the logic state of said erasable programmable non-volatile semiconductor memory element to prevent one logic state from being set again for said electrically erasable programmable non-volatile semiconductor memory element even if the address and data for setting the software data protection is input, where said electrically erasable programmable non-volatile semiconductor memory element is already set in one logic state for controlling the logic state setting operation of said electrically erasable programmable non-volatile semiconductor memory element to prevent the other logic state from being set again for said electrically erasable programmable non-volatile semiconductor memory element even if the address and data for releasing said software data protection is received when said electrically erasable programmable non-volatile semiconductor memory element is set in the other logic state.
3. The electrically erasable programmable non-volatile semiconductor memory device according to claim 1, wherein
said logic state setting control means comprises:
a memory circuit for storing a logic state which is currently set in said electrically erasable programmable non-volatile semiconductor element,
a logic circuit for outputting a control signal for setting the other logic state in said electrically erasable programmable non-volatile semiconductor element where the address and data for setting the software data protection is received, and
a circuit means for preventing said electrically erasable programmable non-volatile semiconductor memory element from being set in one logic state where it is stored in said storing circuit means and said electrically erasable programmable non-volatile semiconductor memory element is set in the other logic state and when the control signal for setting said electrically erasable programmable non-volatile semiconductor memory element from being set in said other logic state is output from said logic circuit.
4. The electrically erasable programmable non-volatile semiconductor memory device according to claim 3, wherein
said storing circuit comprises a latch circuit.
5. The electrically erasable programmable non-volatile semiconductor memory device according to claim 2, wherein
said logic state setting control circuit comprises a storing circuit means for storing a logic state set in said electrically erasable programmable non-volatile semiconductor memory element,
a logic circuit means for outputting a first control signal for setting said electrically erasable programmable non-volatile semiconductor memory element where said logic circuit receives the address and data for setting said software data protection and for outputting a second control signal for setting said electrically erasable programmable non-volatile semiconductor memory element to the other logic state where said logic circuit receives the address and data for releasing said software data protection, and
a prohibiting means for prohibiting an operation of said electrically erasable programmable non-volatile semiconductor memory element to be set in said one logic state, where said storing circuit stores that said electrically erasable programmable non-volatile semiconductor element is set in said one logic state when said logic circuit outputs said first control signal for setting said one logic state in said electrically erasable programmable non-volatile semiconductor memory element, and for prohibiting said electrically erasable programmable non-volatile semiconductor memory element to be set in the other logic state, where said storing means stores that said electrically erasable programmable non-volatile semiconductor memory element is set in the other logic state, when said logic circuit outputs a second control signal for setting said electrically erasable programmable non-volatile semiconductor memory .element to be set in the other logic state.
6. The electrically erasable programmable non-volatile semiconductor memory device according to claim 5, wherein
said storing circuit comprises a latch circuit.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1244553A JPH03108196A (en) | 1989-09-20 | 1989-09-20 | Electrically erasable writable nonvolatile semiconductor storage device |
JP244553/89 | 1989-09-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0419260A2 true EP0419260A2 (en) | 1991-03-27 |
EP0419260A3 EP0419260A3 (en) | 1992-08-26 |
Family
ID=17120418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900310303 Withdrawn EP0419260A3 (en) | 1989-09-20 | 1990-09-20 | Electrically erasable and programmable non-volatile semiconductor memory device |
Country Status (4)
Country | Link |
---|---|
US (1) | US5173876A (en) |
EP (1) | EP0419260A3 (en) |
JP (1) | JPH03108196A (en) |
KR (1) | KR910006995A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0460648A2 (en) * | 1990-06-05 | 1991-12-11 | Kabushiki Kaisha Toshiba | Programming circuit for use in nonvolatile semiconductor memory device |
US5214605A (en) * | 1990-08-20 | 1993-05-25 | Samsung Electronics Co., Ltd. | Automatic erasing optimization circuit for an electrically erasable and programmable semiconductor memory and method thereof |
EP0609893A2 (en) * | 1993-02-05 | 1994-08-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device using a command control system |
EP0728360A1 (en) * | 1993-11-08 | 1996-08-28 | Turbo Ic, Inc. | Single transistor per cell eeprom memory device with bit line sector page programming |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5546561A (en) * | 1991-02-11 | 1996-08-13 | Intel Corporation | Circuitry and method for selectively protecting the integrity of data stored within a range of addresses within a non-volatile semiconductor memory |
KR940005696B1 (en) * | 1991-11-25 | 1994-06-22 | 현대전자산업 주식회사 | Rom device with security |
JP3305737B2 (en) * | 1991-11-27 | 2002-07-24 | 富士通株式会社 | Confidential information management method for information processing equipment |
GB2263348B (en) * | 1992-01-14 | 1995-08-09 | Rohm Co Ltd | Microcomputer and card having the same |
US5506757A (en) * | 1993-06-14 | 1996-04-09 | Macsema, Inc. | Compact electronic data module with nonvolatile memory |
US5418751A (en) * | 1993-09-29 | 1995-05-23 | Texas Instruments Incorporated | Variable frequency oscillator controlled EEPROM charge pump |
US5539252A (en) * | 1995-05-16 | 1996-07-23 | Macsema, Inc. | Fastener with onboard memory |
FR2771839B1 (en) * | 1997-11-28 | 2000-01-28 | Sgs Thomson Microelectronics | PROGRAMMABLE AND ELECTRICALLY ERASABLE NON-VOLATILE MEMORY |
US6654847B1 (en) * | 2000-06-30 | 2003-11-25 | Micron Technology, Inc. | Top/bottom symmetrical protection scheme for flash |
US6902481B2 (en) | 2001-09-28 | 2005-06-07 | Igt | Decoupling of the graphical presentation of a game from the presentation logic |
US7931533B2 (en) | 2001-09-28 | 2011-04-26 | Igt | Game development architecture that decouples the game logic from the graphics logics |
US20070102529A1 (en) * | 2005-11-08 | 2007-05-10 | Macsema, Inc. | Information devices |
US7908118B2 (en) * | 2005-11-14 | 2011-03-15 | Macsema, Inc. | System and methods for testing, monitoring, and replacing equipment |
WO2007059173A2 (en) * | 2005-11-14 | 2007-05-24 | Macsema, Inc. | Systems and methods for monitoring system performance |
US20080106415A1 (en) * | 2006-11-08 | 2008-05-08 | Macsema, Inc. | Information tag |
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US4744062A (en) * | 1985-04-23 | 1988-05-10 | Hitachi, Ltd. | Semiconductor integrated circuit with nonvolatile memory |
US4763305A (en) * | 1985-11-27 | 1988-08-09 | Motorola, Inc. | Intelligent write in an EEPROM with data and erase check |
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US4975878A (en) * | 1988-01-28 | 1990-12-04 | National Semiconductor | Programmable memory data protection scheme |
-
1989
- 1989-09-20 JP JP1244553A patent/JPH03108196A/en active Pending
-
1990
- 1990-09-19 US US07/584,673 patent/US5173876A/en not_active Expired - Fee Related
- 1990-09-20 EP EP19900310303 patent/EP0419260A3/en not_active Withdrawn
- 1990-09-20 KR KR1019900014914A patent/KR910006995A/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US4744062A (en) * | 1985-04-23 | 1988-05-10 | Hitachi, Ltd. | Semiconductor integrated circuit with nonvolatile memory |
US4763305A (en) * | 1985-11-27 | 1988-08-09 | Motorola, Inc. | Intelligent write in an EEPROM with data and erase check |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0460648A2 (en) * | 1990-06-05 | 1991-12-11 | Kabushiki Kaisha Toshiba | Programming circuit for use in nonvolatile semiconductor memory device |
EP0460648A3 (en) * | 1990-06-05 | 1994-07-20 | Toshiba Kk | Programming circuit for use in nonvolatile semiconductor memory device |
US5214605A (en) * | 1990-08-20 | 1993-05-25 | Samsung Electronics Co., Ltd. | Automatic erasing optimization circuit for an electrically erasable and programmable semiconductor memory and method thereof |
EP0609893A2 (en) * | 1993-02-05 | 1994-08-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device using a command control system |
EP0609893A3 (en) * | 1993-02-05 | 1995-11-02 | Toshiba Kk | Nonvolatile semiconductor memory device using a command control system. |
EP0728360A1 (en) * | 1993-11-08 | 1996-08-28 | Turbo Ic, Inc. | Single transistor per cell eeprom memory device with bit line sector page programming |
EP0728360A4 (en) * | 1993-11-08 | 1998-10-21 | Turbo Ic Inc | Single transistor per cell eeprom memory device with bit line sector page programming |
Also Published As
Publication number | Publication date |
---|---|
KR910006995A (en) | 1991-04-30 |
US5173876A (en) | 1992-12-22 |
EP0419260A3 (en) | 1992-08-26 |
JPH03108196A (en) | 1991-05-08 |
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