EP2181520A2

EP2181520A2 - Transceiver circuits

Info

Publication number: EP2181520A2
Application number: EP08787301A
Authority: EP
Inventors: Stephan Bolz
Original assignee: Continental Automotive GmbH
Current assignee: Continental Automotive GmbH
Priority date: 2007-08-22
Filing date: 2008-08-19
Publication date: 2010-05-05
Also published as: US20110187405A1; WO2009024564A2; DE102007039616B4; DE102007039616A1; WO2009024564A3; US8174286B2

Abstract

The present invention relates to a transceiver circuit (200) which supports a bidirectional mode. The present invention relates particularly to a bidirectional transceiver circuit (200) which is signal-compatible with JEDEC SSTL 2. The present invention also relates to a differential transceiver circuit (500) which supports a bidirectional mode and is signal-compatible with JEDEC SSTL 2. Finally, the present invention relates to transceiver circuits (700, 800) which, in interaction with the bidirectional transceiver circuits (200, 500), allow a bus system to be set up.

Description

description

Transceiver circuits

The present invention relates to a transceiver circuit that supports bidirectional operation. More particularly, the present invention relates to a bidirectional transceiver circuit that is signal compatible with JEDEC SSTL 2. The present invention further relates to a differential transceiver circuit which supports bidirectional operation and is signal compatible with JEDEC SSTL 2. Finally, the present invention relates to transceiver circuits that enable the construction of a bus system in cooperation with said bidirectional transceiver circuits.

The performance of modern microcontroller and microprocessor systems, in addition to the system clock, is essentially determined by the access time of the arithmetic unit to stored data. Thus, a part of the program and data memory is usually integrated together with the arithmetic unit on a chip (often referred to as a cache). Limiting factors for the size of this memory are chip area and manufacturing costs. Although the overall cost of the integrated functions decreases with integration, the chip area generally grows with integration, and the chip area also increases the chip production reject rate, which in turn reduces the profitability of the manufacturing process. Therefore, in practice, a size is selected for the program and data memory integrated on a chip together with the arithmetic unit, which represents a favorable compromise between economic aspects and technical requirements.

As a rule, the size of this memory does not correspond to the total memory requirement for a given microcontroller or microprocessor system. It follows that a part the memory must be provided as external memory outside the controller / processor chip.

For the communication between the arithmetic unit and external memory electrical signal lines are required, which are usually passed over a substrate, such as a printed circuit board. The transmission speed of the data on the signal lines is limited by the propagation speed of electrical waves. For the propagation velocity v, the following applies:

v = c / Vε _r

For the common circuit board material FR4 results in a propagation velocity v = 20 cm / ns. A signal with a frequency of 1 GHz has a wavelength λ = 20 cm in this material, which follows from the relationship λ = f ^• v.

If the frequency components contained in the data signals are in a corresponding relationship to the length of the communication lines, signal distortions due to line reflections can occur in the case of simple, non-impedance-matched lines. This typically applies from a ratio of line length 1 to wavelength λ of the frequency f to be taken into account of 1: 8.

1 / λ <1/8

There is a relationship between the rise and fall times t _r , f of a digital signal and an assignable frequency. t _r , f ~ 1 / f

Since modern digital CMOS circuits certainly have switching times t _r , f of 1 ns and less, this results, for example, in the following:

1 / λ <1/8

1 <λ / 8 at λ = 20 cm: 1 <2.5 cm Communication cables up to 2.5 cm in length can therefore still be laid as simple electrical connections, for example, in the layout of a printed circuit board. On the other hand, if the line length exceeds approx. 2.5 cm, line adaptation is required to avoid signal distortion due to reflections.

Line adaptation means that the source impedance and / or the termination impedance correspond to the line impedance. In the context under consideration, the inductive and capacitive components of said impedances can be neglected relative to the resistive component, so that adaptation (approximately) can be achieved by selecting the source resistance R _q and / or the terminating resistor R _a equal to the line resistance Ri. There are three technically important configurations:

1. R _q = R i, R _a φ R i 2. R _q φ R i, R _a = R i 3. R _q = R _a = R i whose properties will be briefly examined below with reference to FIG. Shown schematically in FIG. 1 is a simplified transmission path 100 comprising a signal source 110, a signal line 120 and a signal sink 130. The signal source has the source resistance R _q , the signal sink the terminating resistor R _a and the signal line the line resistance Ri.

1. R _q = Ri, R _a φ Ri The source resistance R _q corresponds to the line resistance Ri.

The termination resistance R _a is chosen in practice in this configuration as against infinity (R _a → ∞). A rising signal edge at the signal source 110 is halved at the voltage divider Rq, Ri and travels at the propagation speed through the signal line 120. At the signal sink 130, a portion of the energy is reflected (depending on the value R _a ) and returns to the signal source 110, where it is absorbed at the source resistance Rq. Along the line 120 is a to observe a two-part edge, which makes digital signal evaluation considerably more difficult.

This configuration is suitable only for unidirectional data transmission from a signal source (e.g., a series resistor gate output) to a high impedance signal sink (e.g., gate input). Because of the signal distortion, it makes no sense to connect further gate inputs along the signal line 120.

2. R _q Φ Ri, R _a = Ri

The terminating resistor R _a corresponds to the line resistance Ri. The source resistance R _q is designed in this configuration, for example, as going to zero. A rising signal edge at the signal source 110 is fed at full amplitude into the signal line 120 and travels at the propagation speed through the signal line 120. At the signal sink 130, the energy in R _{a is} absorbed so that no energy returns to the signal source 110. Along the line 120 is an edge with the amplitude of

Watching the source signal, which favors a digital signal evaluation.

This configuration is suitable for unidirectional data transmission from a signal source (e.g., gate output) to a matched signal sink (e.g., gate input with termination resistance). There is no signal distortion, and it is therefore possible to connect further high-impedance signal sinks (eg gate inputs without terminating resistor) along the signal line 120.

3. Rq = R _a = Rl

Both the source resistance R _q and the termination resistance R _a correspond to the line resistance Ri. A rising signal edge at the signal source 110 is halved at the voltage divider R _q , Ri and travels at the propagation speed through the signal line 120. At the signal sink 130, the energy in R _a so that no energy is available to signal source 110 runs back. If, due to a slight mismatch, some of the energy returns, this part of the energy is then absorbed at the source resistance R _q . Along the line 120, an edge with half the amplitude of the source signal is observed, which favors a digital signal evaluation.

This configuration is particularly well suited for bi-directional data transfer from a data source (e.g., a series resistor with a series resistor) to a matched sink (e.g., gate input with termination resistance), because of the symmetry properties of this configuration it is readily possible to swap source and drain. In addition, no signal distortion takes place, and it is therefore possible to connect further high-impedance signal sinks along the signal line 120.

A special feature of this configuration is the fact that at the entrance of the sink only half the voltage of the signal generated by the source is applied. In a microcontroller system with a standard operating voltage of 2.5V, the signal swing is thus 1.25V. As a rule, therefore, a receiver with defined detection thresholds for the states HIGH and LOW is required for reliable detection of the transmitted data.

In the JEDEC standard JESD8-9A, which was published in December 2000 and concerns the "Stub Series Terminated Logic for 2.5V (SSTL 2)", a 2.5V bus system is described. In particular, FIG. 5 of this standard shows a realization of the third-named configuration, in which R _q = R _a = R ₁ . The same principle of operation is also found in Figures 4, 9, 12 and 13a, wherein in Figures 12 and 13a so-called differential characteristics are shown.

A disadvantage of the methods described in JESD8-9A circuits is in particular that a termination voltage V _ττ is required which corresponds to half the operating voltage V _DDQ, moving which still has to be available in relatively low impedance since it is loaded with the signal current I ₃ = V _ττ / (R ₃ + R _T ), cf. eg Figure 4 in JESD8-9A. It is also disadvantageous that only point-to-point connections are provided in JESD8-9A. A coupling of further transmitters or receivers along the line is not provided. Finally, a bidirectional data transfer is not provided and not possible.

It is therefore an object of the invention to provide a transceiver circuit which supports bidirectional operation and is signal compatible with JEDEC SSTL 2.

It is a further object of the invention to provide a differential transceiver circuit which supports bidirectional operation and is signal compatible with JEDEC SSTL 2.

It is a further object of the invention to provide transceiver circuits with which a bus compatible with JEDEC SSTL 2 can be constructed.

In accordance with these objects, a transceiver circuit according to the invention comprises:

a first terminal for feeding in a transmission / reception selection signal;

- A second terminal for feeding a data signal to be transmitted;

a third terminal for outputting a data signal;

a fourth connection for a transmission line; and - circuit means which:

provide a voltage corresponding to approximately half the operating voltage in response to a receive signal at the first terminal at the fourth terminal, the terminal resistance effective at the fourth terminal being approximately equal to the resistance of the transmission line to achieve receiver-side line matching, and wherein via the transmission line received signal is evaluated and output at the third port; and provide a voltage approximately corresponding to the operating voltage in response to a send signal at the first terminal at the fourth terminal, if a HIGH signal is applied to the second terminal and provide a voltage at the fourth terminal which is approximately equal to that of the second terminal

Ground level corresponds to if a LOW signal is applied to the second terminal, the effective source resistance in both cases being approximately equal to the resistance of the transmission line in order to achieve a transmitter-side line adaptation.

An advantage of this transceiver circuit is first seen in the fact that with a circuit both transmission and reception is possible and thus bidirectional transmission lines can be constructed, which can be operated by selecting a suitable operating voltage signal compatible with JEDEC SSTL 2. From JEDEC SSTL 2, however, circuits are known that are suitable for unidirectional operation.

Another advantage is that the circuit _according to the invention is not dependent on a termination voltage V _ττ . This voltage provided in JEDEC SSTL 2 is therefore not needed for the present circuit.

The invention further relates to a transceiver circuit, which can be connected to an existing bidirectional transmission line and thus enables a signal-compatible with JEDEC SSTL 2 bus operation. A bus operation is not provided in JEDEC SSTL 2 and becomes possible only by using this aspect of the invention. A transceiver circuit according to this aspect of the invention comprises:

a first terminal for feeding in a transmission / reception selection signal;

- A second terminal for feeding a data signal to be transmitted;

a third terminal for outputting a data signal; a fourth connection for a transmission line; and

- circuit means which:

- in response to a receive signal at the first terminal at the fourth terminal establish a high-impedance state and evaluate a received signal via the transmission line and output at the third terminal; and

provide a voltage approximately corresponding to the operating voltage in response to a transmit signal at the first terminal at the fourth terminal if a HIGH signal is applied to the second terminal and provide a voltage at the fourth terminal which is approximately equal to the ground level, if at the second terminal LOW signal is input, wherein the value of the effective source resistance in both cases corresponds to approximately half the value of the resistance of the transmission line in order to achieve a transmitter-side line adaptation.

Another aspect of the present invention relates to a transceiver circuit for driving a differential link, i. a transmission path having two transmission lines, over which a data signal to be transmitted are transmitted simultaneously with opposite signal level and which allows reproduction of the transmitted signal on the receiver side regardless of any deviations of the transmitter and receiver side operating voltage or ground potentials. A limitation is given only by the common mode range of transmitter and receiver. A transceiver according to this aspect of the invention comprises: a first terminal for inputting a transmit / receive select signal;

- A second terminal for feeding a data signal to be transmitted;

a third terminal for outputting a data signal; a fourth connection for a first transmission line;

a fifth terminal for a second transmission line; and

- circuit means which: provide a voltage corresponding to approximately half the operating voltage in response to a receive signal at the first terminal at the fourth terminal and at the fifth terminal, wherein the terminal resistance effective at the fourth terminal is approximately equal to the resistance of the first transmission line, at a receiver side lead match wherein the terminator effective at the fifth terminal is approximately equal to the resistance of the second transmission line to achieve receiver side line matching, and wherein the signals received over the transmission lines are evaluated and output as a received data signal at the third terminal; and

provide a voltage approximately corresponding to the operating voltage in response to a transmit signal at the first terminal at the fourth terminal and provide a voltage approximately equal to the ground level at the fifth terminal if a HIGH signal is applied to the second terminal and approximately at ground level at the fourth terminal provide appropriate voltage and provide approximately the operating voltage corresponding voltage at the fifth terminal, if a LOW signal is fed to the second terminal, wherein the effective source resistances each corresponding approximately to the resistance of the corresponding transmission line to achieve a transmitter-side line adaptation.

Also for this transceiver circuit for driving a differential transmission path, the present invention provides a circuit for expansion to a bus system.

Finally, the invention relates to data transmission systems with bidirectional transmission and bus systems using said transceiver circuits.

Preferred embodiments of the invention are specified in the subclaims. In the following, embodiments of the present invention will be explained in more detail with reference to FIGS. FIG. 1 shows a simplified transmission path in a schematic representation; FIG. FIG. 2 shows a first transceiver circuit; FIG.

FIG. 3 shows a bidirectional data transmission system comprising two identically constructed transceivers according to FIG. 2; FIG. 4 shows a circuit for detecting the state of the transmission line; 5 shows a differential bidirectional data transmission system comprising two identically constructed differential transceivers;

6 shows a circuit for state detection of the transmission line for a differential bidirectional data transmission system;

FIG. 7 shows a circuit for connecting additional sources or sinks to a data transmission system according to FIG. 3; FIG. and FIG. 8 shows a circuit for connecting additional sources or sinks to a data transmission system according to FIG. 5.

FIG. 2 shows a transceiver circuit 200 in accordance with an exemplary embodiment of the present invention with which an interface to a transmission line 240 can be signal-conformed to JEDEC SSTL 2.

Transceiver 200 has five ports 201-205, namely, a first port 201 for inputting a transmission / reception selection signal, a second port 202 for inputting a data signal to be transmitted, a third port

203 for outputting a data signal, a fourth terminal

204 for coupling the circuit 200 to the transmission line 240 and a fifth terminal 205 for feeding a reference voltage V _re f. It should be noted that the terminal 205 for feeding the reference voltage is not required in each embodiment of the invention, since it is readily possible, for example by means of voltage dividers, the reference For example, the circuit voltage can be obtained from the operating voltage.

Transceiver 200 consists of two circuit parts, wherein the send / receive selection signal at the first terminal 201 signals whether the circuit 200 operates in the receive mode or in the transmit mode, in the present embodiment, a LOW level at the first terminal 201, the circuit in the receive mode and a HIGH level puts the circuit in the transmit mode.

The receiving part of the circuit consists of a hysteresis comparator 220, whose non-inverting input is connected to the reference voltage V _re f, in which case the reference voltage corresponds to half the operating voltage, ie Vr _e f = 0.5 * V _DDQ . The inverting input is connected to the fourth terminal 204 and thus to the transmission line 240. The output of the comparator 220 is connected to the terminal 203 and thus provides the received signal RXD. If the voltage at the I / O terminal 204 of the circuit 200 is greater than V _re f plus half the hysteresis voltage, the RXD terminal 203 is high. If the voltage at I / O terminal 204 of circuit 200 is less than V _ref minus half the hysteresis voltage, then RXD terminal 203 will be low. As the switching level, for example, those of Tables 2 and 3 of the aforementioned JEDEC specification can be provided.

The transmission part of the circuit 200 consists of two NAND gates 211, 212 and two XOR gates 213, 214 and the resistors 231, 232, via which the I / O terminal 204 of the circuit and thus the transmission line 240 to the outputs of XOR Gate 213, 214 is coupled. Since the connection of the I / O port 204 to the receive comparator 220 is permanent, data to be input to the TXD port 202 and sent over the transmission line 240 may be checked at the RXD port 203. receive mode

In the receive mode, a LOW signal is applied to the first terminal 201. This LOW signal is applied to both inputs of the first NAND gate 211, whose output is therefore a HIGH signal, which is applied to the first input 1 of the first XOR gate 213. Instead of the NAND gate 211, any other logic circuit may be provided which causes inversion of the signal at the REC / TRAN terminal 201, e.g. an inverter. The use of a NAND gate 211 has the advantage that the output signal is subject to the same delays as the signal output from the second NAND gate 212, which would not always be the case in the case of differently selected gates 211, 212.

The LOW signal at the first terminal 201 is also located at the first input 4 of the second NAND gate, the output of which therefore independent of the signal at the second input 5 is a HIGH signal which equally to the second input 2 of the first XOR gate 213 and is supplied to the first input 4 of the second XOR gate 214.

The first XOR gate 213 thus receives a HIGH signal at both inputs 1 and 2 in the receive mode and therefore outputs a LOW signal. The second XOR gate 214 functions here as a simple signal forwarding, since the second input 5 of the second XOR gate 214 is grounded and its output thus follows the signal applied to the first input 4 (here: HIGH). The advantage of using an XOR gate 214 at this point is again to be seen in the fact that the output signal is subject to the same delays as the signal output from the first XOR gate 213, whereby other circuit variants are readily apparent to those skilled in the art are.

The outputs 3 and 6 of the XOR gates 213, 214 thus have in

Receive mode different levels. The outputs of the XOR gates 213, 214 are each coupled to a resistor 231, 232 to the I / O port 204, which are preferably the same value have, in the present embodiment, each 100 Ω. Thus, due to the voltage divider formed by the resistors R1 and R2 231, 232, a voltage corresponding to half the operating voltage is established at the I / O connection. For JEDEC SSTL 2 with an operating voltage of 2.5 V, therefore, there is just a voltage value of 1.25 V, which corresponds to the termination voltage V _ττ , without a separate supply of this termination voltage would be required. The conclusion resulting from the view of the transmission line 240 at the I / O port 204 substantially corresponds to the parallel connection of the two resistors Rl, R2 and has a value of R _a = 50 Ω in the present embodiment. The transmission line 240, which in the present case has an - at least approximately - purely resistive impedance of 50 Ω, is thus adapted to the drain (ie receiver side).

transmission mode

In the transmission mode, a HIGH signal is applied to the first connection 201. This HIGH signal is applied to both inputs of the first NAND gate 211, whose output is therefore a LOW signal, which is applied to the first input 1 of the first XOR gate 213. The HIGH signal at the first terminal 201 is also at the first input 4 of the second NAND gate 212, the output of which therefore inverted the signal at the second input 5 follows. At the second input 5 of the second NAND gate 212 is to be transmitted signal TXD, which is fed to the second terminal 202. The output of the second NAND gate 212 and thus, as explained above, also of the second XOR gate 214 thus follow the inverted signal to be transmitted.

The same applies to the output of the first NAND gate 213, since a LOW signal from the first NAND gate 211 is applied to its first input 1 independently of the signal a, TXD connection 202, and the inverted TXD signal is applied to the second input 2 from the second NAND gate 212.

The outputs 3 and 6 of the XOR gates 213, 214 thus always have identical levels in the transmission mode. At the I / O port 204 Therefore, by means of the resistors Rl and R2 231, 232 a LOW level at a HIGH signal at the TXD terminal 202 and a HIGH level at a LOW signal at the TXD terminal 202. From the perspective of the transmission line 240 am I / O terminal 204 resulting source resistance substantially corresponds to the parallel connection of the two resistors Rl, R2 and has a value of R _q = 50 Ω in the present embodiment. The transmission line 240, which in the present case has an - at least approximately - purely resistive impedance of 50 Ω, is thus matched at the source (ie transmitter side).

By a conclusion of the transmission line 240 at the other end (not shown) with a terminating resistor R _a = 50 Ω, for example, by an identically constructed

Circuit operating in the receive mode is divided by the resulting voltage divider of the voltage value to allowable values according to JEDEC SSTL 2 Tables 4 and 5.

It should be noted that an additional advantage of the transceiver 200 shown in Fig. 2 is that the outputs 3 and 6 of the two XOR gates 213, 214 each provide only half the load current. This makes it possible to dimension the output transistors of the XOR gates 213, 214 correspondingly small, whereby costs and space can be saved.

FIG. 3 shows a bidirectional data transmission system which consists of two identically constructed transceivers 200, 200 'according to FIG. 2. On the transmission line 240, a transceiver 200, 200 'is connected on both sides. For data transmission from the first transceiver 200 to the second transceiver 200 ', a HIGH signal is applied to the first terminal 201 of the first transceiver 200 to switch it to the transmission mode, and at the first terminal 201' of the second transceiver 200 'becomes a LOW signal created, in order to put this into the receiving mode. As described above, a signal applied to the second terminal 202 of the first transceiver 200 is output in an inverted manner at the I / O terminal 204, whereby the level at the I / O terminal 204 'of the second transceiver is influenced accordingly and by the comparator 220 'is evaluated, whereupon at the third terminal 203' of the second transceiver 200 'due to the inverting operation of the comparator 203' the originally applied to the second terminal 202 of the first transceiver 200 signal is output.

For data transmission from the second transceiver 200 'to the first transceiver 200, a HIGH signal is correspondingly applied to the first terminal 201' of the second transceiver 200 'to switch it into the transmission mode, and at the first terminal 201 of the first transceiver 200 a LOW signal

Signal is applied in order to switch it to receive mode.

It should be noted that at any time the transmission line is terminated on both sides.

In the example of FIG. 3, the reference voltage V _ref for both transceivers 200, 200 'is generated by a voltage divider with identical resistors R _re fi / R ref 2 251, 252. Alter ^¬ natively, the reference voltage for each circuit can be provided separately.

If there is no control, for example as part of a microcontroller, with which the direction of the data transmission is controlled, the transceiver circuit according to FIG. 2 can be supplemented by a circuit which provides state recognition (free / occupied) of the transmission line 240 supplies. An asynchronous operation of the system illustrated in FIG. 3 is then possible by means of two transceiver circuits that have been supplemented in this way.

In the operation of the circuit according to FIG. 3, due to the resistance ratios of the transmission line 24 terminated on both sides, levels for HIGH and LOW which are set by deviate from the idling levels of an isolated transceiver circuit 200, 200 'described in connection with FIG. 2. The HIGH level is 75% of the operating voltage and the LOW level is 25% of the operating voltage. This results, as one skilled in the art can immediately recognize, from the fact that

the fourth terminal 204 'of the receiver 200' in the receive mode, as explained above with reference to FIG. 2, is supplied with half the operating voltage,

- The I / O port 204 of the transmitter 200 is supplied with the full operating voltage or to the ground level, and

- The respectively effective resistors (source resistance of the transmitter 200 and terminator of the receiver 200 ') were chosen to be substantially identical.

4 shows an exemplary circuit 400 for state detection (free / busy) of the transmission line. The circuit 400 has a first terminal 401 for coupling to the transmission line and a second terminal 402 for outputting a free / busy signal (BUSY). The signal received via the transmission line is fed to a window comparator which consists of two comparators 421, 422 and whose upper switching point lies between the minimum permissible voltage value for "HIGH" on the transmission line and half the operating voltage and whose lower switching point between half the operating voltage and the maximum allowable voltage value for "LOW" on the transmission line. This circuit makes use of the fact that a free line has a level corresponding to half the operating voltage and an occupied line has either a HIGH or a LOW level according to JEDEC SSTL 2 tables 2a, 2b, 4 and 5.

Based on the maximum allowable voltage value for "LOW" and the minimum allowable voltage value for "HIGH", the dimensioning of three resistors 411, 412, 413 can easily be carried out, which supply the reference voltages for the comparators 421, 422 as voltage dividers. A dimensioning example for the resistors 411, 412, 413 is given below. According to JEDEC SSTL 2 Table 2a, the following applies: Minimum "HIGH" level = V _ref + 0, 18V = 1, 43V Maximum "LOW" level = V _ref -0, 18V = 1, 07V

In order to take into account the component tolerances of the resistors 411, 412 and 413 as well as any offset errors of the comparators 421, 422, it makes sense to set the switching thresholds between the reference voltage V _ref and the minimum "HIGH" level, or the maximum "LOW" Set level: upper switching threshold V _H , _min = V _ref + 0, 09V = 1, 34V lower switching threshold V _L , _max = V _ref -0, 09V = 1, 16V

The voltage dividers formed from the resistors 411-413 lead to the following relationships:

V _H , _min = V _DDQ ^• (Rb2 + Rb3) / (Rbl + Rb2 + Rb3)

V _L , _ma χ = V _DDQ ^• Rb3 / (Rbl + Rb2 + Rb3)

Transformed results:

(Rb2 + Rb3) ^• V _DDQ / V _H , _min = RbI + Rb2 + Rb3

Rb3 ^• V _DDQ / V _L , _max = RbI + Rb2 + Rb3

It follows:

(Rb2 + Rb3) ^• V _DDQ / V _H , _min = Rb3 ^• V _DDQ / V _L , _max

or further simplified: Rb2 / Rb3 = V _H , _min / V _L , _max - 1

For the three resistors there are only two determinative equations, a resistance value is thus optional. Now Rb3 is chosen to be 10 kΩ. This leads to Rb2: Rb2 = Rb3 ^• (V _H, _min / V _L, _max - 1) = 10 k ^• (1.34 / 1.16 -1) = 1.55 kΩ RbI results from substituting one of the initial equations for 10 kΩ.

In the operating state, the circuit according to FIG. 4 behaves as follows: If a voltage at the first terminal 401 is above the minimum permissible voltage value for "HIGH" or below the maximum permissible voltage value for "LOW", then either the output of the first comparator 421 or Output of the second comparator 422 a LOW level. Accordingly, the output of a NAND gate 430, to which the outputs of the comparators 421, 422 are linked and which is connected to the second terminal 402, results in a HIGH level indicating the occupancy of the line. If, on the other hand, the voltage at the first terminal 401 lies above the maximum permissible voltage value for "LOW" and below the minimum permissible voltage value for "HIGH", the outputs of both comparators 421, 422 carry a HIGH level, and the output of the NAND gate 430 and thus the second port 402 is a LOW level indicating that the line is idle.

The embodiments described above relate to a non-differential transmission line, i. a single transmission line, at both the transmitter and the receiver identical operating voltage and

Ground potential must be present in order to ensure a correct signal evaluation. In faulty systems, however, it may happen that the potentials mentioned differ from one another at the transmitter and at the receiver, so that signal evaluation is no longer possible because then e.g. the transmitted HIGH / LOW levels no longer match the corresponding detection thresholds at the receiver. As a result, transmission errors occur.

In addition, an adverse effect inevitably arises from the fact that the two transceivers 200, 200 'are spatially separated from each other and the data transmitted between them a corresponding alternating current in the mass network or supply cause voltage supply network. At high data rates, the always present, unavoidable inductances of these networks then become noticeable as alternating voltage amplitudes. This can then lead, for example, to the fact that an AC voltage amplitude can be measured between the ground terminal of the first transceiver 200 and the ground terminal of the second transceiver 200 '. Despite careful design of the mass network or supply voltage network, this effect can lead to considerable impairment of data quality in complex circuits.

Finally, it may be disadvantageous to have to provide a separate reference voltage.

Therefore, so-called differential data transmission is already used in JEDEC SSTL 2 Chapter 5, especially for circuits with high clock rates. In differential data transmission, data of the opposite level is transmitted simultaneously via two transmission lines of the same type as possible.

In the following it will be described with reference to Fig. 5 how the differential operation circuit according to the invention can be adapted. In FIG. 5, for those circuit parts which are identical to those of FIG. 3 and perform the same function, the reference numerals (201-240) of FIG. 3 have been adopted. For a description of their function, reference is made to the description of FIG. 3 in order to avoid repetition. Added elements bear the reference number beginning with the number 5.

FIG. 5 shows two identically constructed transceivers 500 and 500 '. A transceiver 500, 500 'for differential operation has 5 terminals 201-204, 506: in accordance with Figs. 2 and 3, a first terminal 201 for inputting a transmission / reception selection signal, a second terminal 202 for inputting one data signal to be transmitted, a third terminal 203 for outputting a data signal In addition to FIGS. 2 and 3, the transceiver 500 does not require a reference voltage V _re f, but has a fifth terminal 506 for connecting the second transmission line 560.

Transceiver 500 consists of two circuit parts, in turn, the send / receive selection signal at the first terminal 201 signals whether the circuit 500 operates in the receive mode or in the transmit mode, in the present embodiment, a LOW level at the first terminal 201, the circuit in the Reception mode is offset and a HIGH level puts the circuit in the transmit mode.

The receiving part of the circuit again consists of a

Comparator 220 whose non-inverting input is connected here to the fifth terminal 506 and thus to the second transmission line 560. The inverting input is unchanged with respect to FIG. 2, 3 with the fourth terminal 204 and thus connected to the first transmission line 240.

The output of the comparator 220 is connected to the terminal 203 and thus provides the received signal RXD. When the voltage at the first I / O terminal 204 of the circuit 500 corresponds to a HIGH signal, the voltage at the second I / O terminal 506 necessarily corresponds to a LOW signal at the same time. the voltage at the first I / O port 204 is greater than the voltage at the second I / O port 506, so the RXD port 203 LOW level. On the other hand, if the voltage on the first I / O terminal 204 of the circuit 500 is LOW, then the voltage on the second I / O terminal 506 necessarily coincides with a HIGH signal, i. the voltage at the first I / O port 204 is less than the voltage at the second I / O port 506, so the RXD port 203 carries HIGH level.

The transmission part of the circuit 500 consists of a first circuit part, which is substantially identical to that shown in FIG. 2, comprising the gates 211-214 as well as the resistors 231, 232 for connection to the first transmission line 240 and a second circuit part comprising an AND gate 511, two XOR gates 513, 514 and two resistors 531, 532 for coupling the outputs of the XOR gates 513, 514 to the second one Transmission line 560. The second circuit part is functionally complementary to the first circuit part, ie constructed so that a LOW signal is output via the second transmission line when a HIGH signal is output via the first transmission line and vice versa. Also for the transceiver 500, the connection of the I / O ports 204, 506 to the receive comparator 220 is permanent, so that data to be input to the TXD port 202 and sent over the transmission lines 240, 560 is at the RXD port 203 can be checked.

receive mode

In the receive mode, a LOW signal is applied to the first terminal 201. For the behavior of the first circuit part, the statements on FIG. 2 apply accordingly. The LOW signal at the REC / TRAN terminal 201 is also located at both inputs of the

AND gate 511, which thus shows no logic function and is only intended to effect a signal delay corresponding to the signal delay of the signal output by NAND gate 212. The output of the AND gate 511 is therefore a LOW signal, which is applied to the first input 10 of the third XOR gate 513.

The third XOR gate 513 receives at its second input 9 the output from the second NAND gate 212 of the first circuit part signal (HIGH). Thus, at the inputs 9 and 10 of the third XOR gate 513 in the receive mode, there are various signals, therefore, the output of the XOR gate is a HIGH signal. The fourth XOR gate 514 also receives at its first input 12 the signal output by the second NAND gate 212 of the first circuit part (HIGH) and is connected at its second input 13 to the operating voltage. The fourth XOR gate 514 functions as an inverter, so its output is LOW in receive mode. The advantage of Use of an XOR gate 514 at this point is again to be seen in that the output signal is subject to the same delays as the signal output from the other XOR gates 213, 214, 513, and here again other circuit variants readily apparent to those skilled in the art are.

The outputs 8 and 11 of the XOR gates 513, 514 thus also have different levels in the receive mode, and the behavior of the second I / O port 506 is the same for the

I / O terminal 204 in connection with FIG. 2 made statements.

Also, the second transmission line 560, which in the present case has a - at least approximately - purely resistive impedance of 50 Ω, is thus matched at the sink (i.e., receiver side).

Transmission mode In the transmission mode, a HIGH signal is present at the first connection 201. The function of the first circuit part is again as described above with reference to FIG. The second circuit part receives this HIGH signal at both inputs of the AND gate 511, the output of which is therefore a HIGH signal, which is applied to the first input 10 of the third XOR gate 513.

Both XOR gates 513, 514 of the second circuit part receive at each input 9, 12, the output of the second NAND gate 212, the output of which inverts the TXD signal at the second terminal 202 follows. The fourth XOR gate 514 re-inverts this signal so that the non-inverted TXD signal is output at the output 11 of the fourth XOR gate. The same applies to the output 8 of the third XOR gate, since in the transmission mode whose first input 10 also has a constant HIGH signal. The outputs 8 and 11 of the XOR gates 513, 514 thus have - as well as the outputs 3 and 6 of the XOR gates 213, 214 - in transmit mode always identical levels. Therefore, at the second I / O terminal 506, a high level at a high signal at the TXD terminal 202 and a low level at a low signal at the TXD terminal 202 are established by means of the resistors R1 and R2 531, 532 - Just inverse to the behavior of the first I / O port 204. The resulting from the view of the second transmission line 560 at the I / O port 506 source resistance substantially corresponds to the parallel connection of the two resistors Rl, R2 and has a value of R _q = 50 Ω in the present embodiment. The second transmission line 560, which in the present case has an - at least approximately - purely resistive impedance of 50 Ω, is thus matched at the source (ie transmitter side).

By terminating the transmission lines 240, 560 at the other end with a termination resistance R _a = 50 Ω, for example by an identically constructed circuit 500 'operating in the receive mode, the resulting voltage divider will change the voltage value to allowable values according to JEDEC SSTL 2 tables 4 and 5 divided.

Advantageously, the arrangement according to FIG. 5 requires neither a termination voltage nor a reference voltage in order to reliably detect transmitted data, and the AC voltage swing on the mass network or the supply voltage network is substantially lower than in the arrangement in FIG Arrangement of Fig. 5 is true that both transmission lines 240, 560 are completed at both times on both sides. For the adjusting in the operating level for HIGH and LOW, the statements to Fig. 3 apply accordingly.

The transceiver circuits 500, 500 'according to FIG. 5 can also be supplemented by a circuit which provides a state detection (free / occupied) of the transmission lines 240, 560 and allows asynchronous operation of the system shown in FIG.

6 shows an exemplary circuit 600 for state detection (free / occupied) of the transmission line, which essentially consists of a respective circuit 400 according to FIG. 4 for each of the two transmission lines. Circuit 600 has a first terminal 601 for coupling to the first transmission line, a second terminal 602 for outputting a clear / busy signal (BUSY), and a third terminal

603 Coupling to the second transmission line. The signal received via the transmission lines is in each case supplied to a window comparator which consists of two comparators 621, 622 or 623, 624 and whose upper switching points lie between the minimum permissible voltage value for "HIGH" on the transmission lines and half the operating voltage and their lower switching points between half the operating voltage and the maximum allowable voltage value for "LOW" lie on the transmission lines. Again, the maximum allowable voltage value for "LOW" and the minimum allowable voltage value for "HIGH" can easily be used to dimension three resistors 611, 612, 613, which as voltage dividers provide the reference voltages for the comparators 621, 622 and the comparators 623 , 624 deliver.

The behavior of the circuit is similar to that of circuit 400 described with reference to FIG. 4 except that the outputs of all four comparators 621-624 are coupled to a quad NAND gate 630 to the BUSY output signal. Of course, instead of the quadruple NAND gate, those skilled in the art will have access to numerous circuit variants with equivalent logical function, which are made up of several of the more common gates, each with only two inputs.

The bidirectional data transmission systems according to the invention according to FIGS. 3 and 5 can be easily expanded to bus systems. For a non-differential transmission system according to FIG. 3, a transceiver 700 shown by way of example in FIG. 7 can be used to connect further data sources / lower to the transmission line. Transceiver 700 again has a first terminal 701 for inputting a transmit / receive selection signal, a second terminal 702 for inputting a data signal to be transmitted, a third terminal 703 for outputting a data signal, a fourth terminal 704 for coupling the circuit 700 to the (only) transmission line 240, and a fifth terminal 705 for feeding the reference voltage V _ref .

The insertion point of the circuit 700 into the transmission system is along the transmission line 240. The data signal must therefore be sent in both sub-lines. The effective one

Resistance is thus composed of a parallel connection of two line sections, each with the line resistance (here: 50 Ω) and therefore corresponds to half the line resistance (here: 25 Ω). The source resistance should be equal to half the line resistance to achieve the best possible match.

FIG. 7 shows the transmission line 240 of FIG. 3 divided into two sections 240a and 240b. Coupled thereto is the I / O terminal 704 of the circuit 700, which is connected in-circuit to the inverting input of a comparator 720 since the TXD Signals in the system of FIG. 3 are transmitted inverted on the transmission line 240. The non-inverting input of the comparator 720 is coupled to the reference voltage. The wiring of the comparator 720 is therefore identical to the circuit of the comparator 220 of FIG. 2, so that its function is as described there.

For the transmitter part of the circuit 700, an inverting tristate driver 711 is provided, which is connected via a resistor 730, the dimensioning of which has been explained above, to the I / O terminal 704 and which via the signal applied to the REC / TRAN terminal 701 either high impedance is controlled (in the case of REC / TRAN = LOW, ie circuit in the receive mode) or the signal applied to the TXD terminal 702 inverted signal outputs (in the case of REC / TRAN = HIGH, ie circuit in the transmission mode). A suitable driver for use in this circuit is, for example, the module 74HC240.

For a differential transmission system according to FIG. 5, a transceiver 800 shown by way of example in FIG. 8 can be used to connect further data sources / lower to the transmission line. Transceiver 800 again has a first terminal 801 for inputting a transmit / receive selection signal, a second terminal 802 for inputting a data signal to be transmitted, a third terminal 803 for outputting a data signal, a fourth terminal 804 for coupling the circuit 800 to the first transmission line 240 and a fifth terminal 806 for coupling the circuit 800 to the second transmission line 560.

For the insertion point of the circuit 800 in the transmission lines and the dimensioning of the source resistors, the corresponding statements apply to FIG. 7.

7 shows the first transmission line 240 of FIG. 5 divided into two sections 240a and 240b. Coupled thereto, the first I / O terminal 804 of the circuit 800, which is coupled in-circuit to the inverting input of a comparator 820, since the TXD signals on the first transmission line 240 are transmitted inverted in the system of FIG. The non-inverting input of the comparator 820 is coupled to the second transmission line 560 via the second I / O port 806, via which the TXD signals are transmitted non-inverted. The wiring of the comparator 820 is therefore identical to the wiring of the comparator 220 of FIG. 5, so that its function is as described there. For the transmitter part of the circuit 800, an inverting tristate driver 811 is provided, which is connected via a resistor 830 to the first I / O terminal 804 and outputs the signal applied to the TXD terminal 802 inverted via the first transmission line 240 (in the case

REC / TRAN = HIGH, i. Circuit in transmission mode). A second, noninverting tristate driver 812 is provided, which is connected via a resistor 831 to the second I / O terminal 806 and outputs the signal applied to the TXD terminal 802 noninverted via the second transmission line 560 (in the case of REC / TRAN = HIGH, ie switching in transmit mode). If the circuit is in the receive mode (REC / TRAN = LOW), the outputs of the drivers 811, 812 are controlled with high resistance.

Of course, a plurality of transceivers according to FIG. 7 or FIG. 8 can be inserted into a transmission system according to FIG. 3 or FIG. 5.

With the circuit arrangements described above, it is possible to build digital transmission links application. A correspondingly multiply repeated bidirectional transmission system according to FIG. 3 or FIG. 5 can advantageously be used to optimize the connections between a microprocessor and an external memory in such a way that addresses and data are transmitted on the same lines. This significantly reduces the total number of lines required. The differential embodiment according to FIG. 5 permits transmission rates which are limited only by the logic used and the HF properties of the transmission lines or their carriers.

Claims

claims

A transceiver circuit (200) comprising:

- a first terminal (201) for supplying a transmit / receive selection signal;

- a second terminal (202) for feeding a data signal to be transmitted;

a third terminal (203) for outputting a data signal; - a fourth connection (204) for a transmission line (240); and

- switching means (211, 212, 213, 214, 220, 231, 232) which:

providing a voltage corresponding to approximately half the operating voltage in response to a receive signal at the first terminal (201) at the fourth terminal (204), the termination resistance effective at the fourth terminal being approximately equal to the resistance of the transmission line, at a receiver-side line match and wherein a signal received via the transmission line (240) is evaluated and output at the third port (203); and

provide a voltage approximately corresponding to the operating voltage in response to a send signal at the first terminal (201) at the fourth terminal (204) if a LOW signal is applied to the second terminal (202) and provide a voltage at the fourth terminal (204) , which corresponds approximately to the ground level, if a HIGH signal is applied to the second terminal (202), the effective source resistance in both cases being approximately equal to the resistance of the transmission line

(240) to achieve a transmitter-side line adaptation.

A transceiver circuit (200) according to claim 1, wherein said circuit means comprises:

a first logic circuit (211) for inverting the transmit / receive select signal; - a second logic circuit (212) for NAND-linking the transmit / receive select signal to the data signal to be transmitted;

- a third logic circuit (213) for XORing the output of the first logic circuit (211) with the output of the second logic circuit (212);

- a fourth logic circuit (214) for passing the output of the second logic circuit (212);

- A comparator circuit (220) which compares the signal applied to the fourth terminal (204) with a reference voltage and at the third terminal (203) outputs a HIGH level when the signal applied to the fourth terminal (204) represents the value "LOW" and outputs a LOW level at the third terminal (203) when the signal applied to the fourth terminal (204) represents "HIGH"; such as

- A first resistor (231) which connects the output of the third logic circuit (213) with the fourth terminal (204) and

- A second resistor (232) connecting the output of the fourth logic circuit (214) to the fourth terminal (204).

The transceiver circuit (200) of claim 2, wherein the resistance values of the first and second resistors (231, 232) are approximately equal.

The transceiver circuit (200) of claim 3 wherein the resistance values of the first and second resistors (231, 232) are approximately equal to twice the resistance of the transmission line (240).

A transceiver circuit (200) according to any one of the preceding claims, comprising a fifth terminal (205) for supplying a reference voltage.

A transceiver circuit (200) according to any one of the preceding claims, comprising additional circuit means (400) for detecting whether the state of the transmission line (240) is "busy" or "free" and issuing this state via a sixth port (402).

7. A transceiver circuit (200) according to claim 6, wherein the circuit means (400) for detecting whether the state of the transmission line is "busy" or "free" comprises a window comparator whose upper switching point between the minimum allowable voltage value for "HIGH" is on the transmission line and half the operating voltage and whose lower switching point between the half operating voltage and the maximum allowable voltage value for "LOW" on the transmission line (240).

A transceiver circuit (700) comprising: - a first terminal (701) for inputting a transmit / receive select signal;

- a second terminal (702) for feeding a data signal to be transmitted;

a third port (703) for outputting a data signal;

- a fourth connection (704) for a transmission line (240); and

- switching means (711, 720, 730), which:

- in response to a receive signal at the first terminal (701) on the fourth terminal (704) establish a high-impedance state and evaluate a signal received via the transmission line (240) and output at the third terminal (703); and

provide a voltage approximately corresponding to the operating voltage in response to a transmit signal at the first terminal (701) at the fourth terminal (704) if a LOW signal is applied to the second terminal (702) and provides a voltage at the fourth terminal (704) , which corresponds approximately to the ground level, if a HIGH signal is applied to the second terminal (702), wherein the value of the effective source resistance in both cases is approximately half the value of the resistance the transmission line (240) corresponds to achieve a transmitter-side line adaptation.

9. A transceiver circuit according to claim 8, wherein the circuit means comprise:

a tristate output inverting driver circuit (711) for inverting the data signal to be transmitted under tri-state control of the transmit / receive select signal; - A comparator circuit (720) which compares the signal applied to the fourth terminal (704) with a reference voltage and at the third terminal (703) outputs a HIGH level when the signal applied to the fourth terminal (704) represents the value "LOW" and outputs a LOW level at the third terminal (703) when the signal applied to the fourth terminal (704) represents "HIGH"; such as

- A resistor (730), which connects the output of the driver circuit (711) with the fourth terminal (704).

The transceiver circuit (700) of claim 9, wherein the value of the resistor (730) is approximately half the resistance of the transmission line (240).

11. Transceiver circuit (700) according to any one of claims 8 to 10, which has a fifth terminal (705) for feeding a

Reference voltage has.

A transceiver circuit (700) according to any one of claims 8 to 11, comprising additional circuit means (400) detecting whether the state of the transmission line (240) is "busy" or "idle" and passing this state via a sixth port (402 ) output.

13. A transceiver circuit (700) according to claim 12, wherein the circuit means (400) for detecting whether the state of the transmission line (240) is "busy" or "free" comprises a window comparator whose upper switching point is between the minimum allowable voltage value for "HIGH" on the over- tragungsleitung and half the operating voltage and whose lower switching point between the half operating voltage and the maximum allowable voltage value for "LOW" on the transmission line (240).

14. A data transmission system comprising a transmission line (240) and two transceiver circuits (200, 200 ') according to one of claims 1 to 7.

The data transmission system of claim 14, further comprising one or more transceiver circuits (700) according to any one of claims 8 to 13.

A transceiver circuit (500) comprising: - a first terminal (501) for inputting a transmit / receive select signal;

- a second terminal (502) for feeding a data signal to be transmitted;

a third port (503) for outputting a data signal;

- a fourth terminal (504) for a first transmission line (240);

a fifth terminal (506) for a second transmission line (560); and - switching means (211, 212, 213, 214, 511, 513, 514, 231, 232, 531, 532, 220) which:

provide a voltage approximately equal to half the operating voltage in response to a receive signal at the first terminal (501) at the fourth terminal (504) and at the fifth terminal (506);

Terminal (504) has an effective termination resistance approximately equal to the resistance of the first transmission line (240) to achieve receiver-side line matching, wherein the termination resistance effective at the fifth terminal (506) is approximately equal to the resistance of the second

Transmission line (560) in order to achieve a receiver-side line adaptation, and wherein the signals received via the transmission lines (240, 560) correspond to one another. nals are evaluated and output as a received data signal at the third port (503); and provide a voltage approximately corresponding to the operating voltage in response to a send signal at the first terminal (501) at the fourth terminal (504) and provide a voltage approximately equal to the ground level at the fifth terminal (506) if at the second terminal (502 ) provides a LOW signal and at the fourth terminal (504) provide an approximately ground level voltage and at the fifth terminal (506) provide an approximately voltage corresponding voltage if a HIGH signal is applied to the second terminal (502) , where the effective source resistances are each approximately equal to the resistance of the corresponding transmission line (240, 560) to achieve a transmitter-side line adaptation.

17. A transceiver circuit (500) according to claim 16, the circuit means comprising: - a first logic circuit (211) for inverting the transmit / receive select signal;

- a second logic circuit (212) for NAND-linking the transmit / receive select signal to the data signal to be transmitted; - A third logic circuit (213) for XOR-linking the

Outputting the first logic circuit (211) with the output of the second logic circuit (212);

- a fourth logic circuit (214) for passing the output of the second logic circuit (212); a fifth logic circuit (511) for passing the transmission / reception selection signal;

- a sixth logic circuit (513) for XORing the output of the fifth logic circuit (511) with the output of the second logic circuit (212); a seventh logic circuit (514) for inverting the output of the second logic circuit (212);

a comparator circuit (220) which connects the signal present at the fourth connection (204) to the one at the fifth connection (506). and outputs a LOW level at the third terminal (203) when the signal applied to the fourth terminal (204) represents the value "HIGH" and the signal applied to the fifth terminal (506) represents the value "LOW" and at the third Terminal (203) outputs a HIGH level when the signal applied to the fourth terminal (204) represents the value "LOW" and the signal applied to the fifth terminal (506) represents the value "HIGH"; such as

a first resistor (231) connecting the output of the third logic circuit (213) to the fourth terminal (204),

- a second resistor (232) connecting the output of the fourth logic circuit (214) to the fourth terminal (204), - a third resistor (531) connecting the output of the sixth logic circuit (513) to the fifth terminal (506) connects, and

a fourth resistor (532) connecting the output of the seventh logic circuit (514) to the fifth terminal (506).

The transceiver circuit (500) of claim 17, wherein the resistance values of the first, second, third and fourth resistors (231, 232, 531, 532) are approximately equal.

The transceiver circuit (500) of claim 18, wherein the resistance values correspond to approximately twice the resistance value of the transmission lines (240, 560).

A transceiver circuit (500) according to any one of claims 16 to 19, comprising additional circuit means (600) for detecting whether the state of the transmission lines (240, 560) is "busy" or "idle" and that state via a sixth port (602).

The transceiver circuit (500) of claim 20, wherein the circuit means (600) for detecting whether the state of the transmission lines (240, 560) is "busy" or "free" for each of the two transmission lines (240, 560) each having a window comparator whose upper switching point between the minimum allowable voltage value for "HIGH" on the transmission lines (240, 560) and the half operating voltage is located and whose lower switching point between half the operating voltage and the maximum allowable voltage value for "LOW" on the transmission lines (240, 560).

A transceiver circuit (800) comprising: - a first terminal (801) for inputting a transmit / receive select signal;

- a second terminal (802) for feeding a data signal to be transmitted;

a third port (803) for outputting a data signal;

a fourth terminal (804) for a first transmission line (240);

a fifth terminal (806) for a second transmission line (560); and - switching means (811, 812, 820, 830, 831) which:

- in response to a receive signal at the first terminal (801) at the fourth and fifth terminal (804, 806) each produce a high-impedance state and the over the transmission lines (240, 560) receive signals received and as a received data signal on output third port (803); and

provide a voltage approximately corresponding to the operating voltage in response to a send signal at the first terminal (801) at the fourth terminal (804) and a voltage approximately at the ground level at the fifth terminal (806), if at the second terminal (802) a LOW Signal is fed and at the fourth terminal (804) provide an approximately ground level voltage and the fifth terminal (806) provide an approximately voltage corresponding to the voltage at the second terminal (802), a HIGH signal is fed, wherein value of effective source resistances each about half the value of the resistance of the corresponding Transmission line (240, 560) corresponds to achieve a sender-side line adaptation.

The transceiver circuit (800) of claim 22, wherein the circuit means comprises:

a tristate output inverting driver circuit (811) for inverted output of the data signal to be transmitted under tri-state control of the transmit / receive select signal; a tristate output non-inverting driver circuit (812) for outputting in reverse the data signal to be transmitted under tri-state control of the transmit / receive select signal;

- A comparator circuit (820) which compares the signal applied to the fourth terminal (804) to the signal present at the fifth terminal (806) and outputs a LOW level at the third terminal (803) when the signal applied to the fourth terminal (804) the value "HIGH" and the fifth connection

(806) signal represents the value "LOW" and at the third terminal (803) outputs a HIGH level when the signal applied to the fourth terminal (804) the signal "LOW" and the signal applied to the fifth terminal (805) signal Value "HIGH" represents; such as

a first resistor (830) connecting the output of the inverting driver circuit (811) to the fourth terminal

(804) connects, and

a second resistor (831) connecting the output of the non-inverting driver circuit (812) to the fifth terminal (806).

The transceiver circuit (800) of claim 23, wherein the values of the resistors (830, 831) correspond to approximately half the resistance of the transmission lines (240, 560).

25. Transceiver circuit (800) according to one of claims 22 to 24, which has additional circuit means (600) which detect whether the state of the transmission lines (240, 560) is "busy" or "free" and will output this state via a sixth port (602).

A transceiver circuit (800) according to claim 25, wherein said circuit means (600) for detecting whether the state of the transmission lines (240, 560) is "busy" or "free" includes one window comparator for each of the two transmission lines (240, 560) whose upper switching point lies between the minimum permissible voltage value for "HIGH" on the transmission lines (240, 560) and half the operating voltage and whose lower switching point between the half operating voltage and the maximum permissible voltage value for "LOW" on the transmission lines (240, 560).

27. A data transmission system comprising two transmission lines (240, 560) and two transceiver circuits (500, 500 ') according to one of claims 16 to 21.

28. The data transmission system of claim 28, additionally comprising one or more transceiver circuits (800) according to any one of claims 22 to 26.