US20010013639A1 - Ball-grid-array semiconductor with protruding terminals - Google Patents
Ball-grid-array semiconductor with protruding terminals Download PDFInfo
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- US20010013639A1 US20010013639A1 US09/465,755 US46575599A US2001013639A1 US 20010013639 A1 US20010013639 A1 US 20010013639A1 US 46575599 A US46575599 A US 46575599A US 2001013639 A1 US2001013639 A1 US 2001013639A1
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- array semiconductor
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Definitions
- the present invention relates to a ball-grid-array semiconductor device and a manufacturing method therefor, and more particularly, to a ball-grid-array semiconductor device having a lead frame with terminal portions formed to protrude by etching, and its manufacturing method.
- a package including a lead frame is available as one of semiconductor device packages that have been manufactured to meet the requirements for semiconductor devices such as higher-integration, miniaturization, decreasing in thickness, and higher pin count.
- a technique relating to a method for manufacturing lead frames that is applicable to ball-grid-array semiconductor devices is described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050.
- FIG. 1 is a cross-sectional view showing a conventional semiconductor device having a lead frame described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050.
- a method of mounting solder balls onto the projected portions 110 a is available to solve this problem, however, this method also presents a problem that material and manufacturing costs are hardly reduced.
- An object of the present invention is to provide a ball-grid-array semiconductor device and manufacturing method therefor, which facilitates cleaning flux residues remaining in between the package and the substrate after having been mounted onto the substrate, and which provides drastically reduced material and manufacturing costs.
- a ball-grid-array semiconductor device comprises: a semiconductor element; a resin material which seals the semiconductor element; and a lead frame connected to the semiconductor element in the resin material.
- the lead frame has a terminal portion that protrudes through a surface of the resin material.
- a method for manufacturing a ball-grid-array semiconductor device comprises the steps of: forming a lead frame having a terminal portion that protrudes in the direction of thickness thereof; mounting a semiconductor element on the lead frame; connecting an electrode provided on the semiconductor device to the lead frame by means of a bonding wire; and sealing the semiconductor element with a resin material.
- the terminal portion protrudes through a surface of the resin material.
- the present invention allows the terminal portions to protrude through the surface of the resin material.
- the terminal portions can used as connecting terminals, as they are, to be mounted directly to the substrate, and cleaning of flux residues after mounting can be readily carried out. Therefore, conventional ball-grid-array semiconductor devices have required solder balls to be mounted on packages to facilitate cleaning flux residues, whereas the present invention requires no such necessity, allowing for providing remarkably reduced material and manufacturing costs.
- FIG. 1 is a cross-sectional view showing a conventional semiconductor device having a lead frame described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050.
- FIG. 2 is a cross-sectional view showing the structure of a ball-grid-array semiconductor device according to an embodiment of the present invention.
- FIG. 3 is a bottom view showing the structure of the ball-grid-array semiconductor device according to the embodiment of the present invention.
- FIG. 4 is a view showing the method for manufacturing the ball-grid-array semiconductor device according to the embodiment of the present invention, illustrating the step where the device is sealed with resin.
- FIG. 2 is a cross-sectional view showing the structure of a ball-grid-array semiconductor device according to the embodiment of the present invention.
- FIG. 3 is a bottom view showing the structure of the ball-grid-array semiconductor device similarly according to the embodiment of the present invention.
- a ball-grid-array semiconductor device 1 allows a semiconductor element 14 to be mounted with an adhesive tape 12 on a lead frame 10 provided with terminal portions 10 a which protrude in the direction of thickness thereof.
- the lead frame 10 is formed, for example, by etching a sheet of metal approximately a half of the thickness thereof.
- bonding wires 16 connect the lead frame 10 to electrodes provided on the semiconductor element 14 . Then, they are sealed with a resin material 18 to be formed in a predetermined package shape. Incidentally, the terminal portions 10 a protrude through the substrate mount surface of the resin material 18 . Moreover, a solder layer 19 is formed on the edges of the terminal portions 10 a.
- the ball-grid-array semiconductor device 1 of this embodiment constructed as such allows the terminal portions 10 a , on which the solder layer 19 is formed, to be used as terminals as they are for being mounted on a substrate.
- the terminal portions 10 a can be etched into a variety of shapes such as a cylinder or a rectangular column.
- a cylindrical shape is desirable in which stress is unlikely to occur, when considering the heat-cycle resisting performance thereof after having been mounted on the substrate.
- the terminal portions 10 a have desirably a height ranging from 0.1 to 0.3 mm from the substrate mount surface, when considering the easiness of cleaning flux residues after having been mounted.
- solder layer 19 to be formed on the edges of terminal portions 10 a is desirably about 5 to 10 ⁇ m in thickness, which is equivalent in thickness to a solder layer to be applied to outer leads of resin-sealed semiconductor devices, typified by conventional QFP (Quad Flat Pack) semiconductor devices.
- QFP Quad Flat Pack
- FIG. 4 is a cross-sectional view showing the method for manufacturing the ball-grid-array semiconductor device according to the embodiment of the present invention, illustrating the step where the device is sealed with resin.
- a sheet of metal is etched approximately by half the thickness thereof to form a lead frame 10 having the terminal portions 10 a that protrude in the direction of thickness.
- a semiconductor element 14 is mounted onto the lead frame 10 with an adhesive tape. Then, the electrodes provided on the semiconductor element 14 are connected to the lead frame 10 by means of bonding wires 16 .
- the lead frame 10 , the semiconductor element 14 and the like are sandwiched in between an upper metal mold 22 having a cavity 22 a of a predetermined shape and a lower metal mold 20 having recessed portions 20 a as a cavity for accommodating the terminal portions 10 a .
- resin is allowed to flow in from an injection portion (not shown) which is in connection with the cavities 20 a and 22 a , thereby sealing the lead frame 10 and the semiconductor element 14 with the resin.
- this embodiment allows the terminal portions 10 a to protrude through the substrate mount surface of the package and the solder layer 19 to be formed on the edges thereof. Therefore, the terminal portions 10 a can be used as connecting terminals, as they are, for being mounted directly to the substrate, and the cleaning of flux residues after the portions have been mounted can be readily carried out. Therefore, conventional ball-grid-array semiconductor devices have required solder balls to be mounted on packages to facilitate cleaning flux residues, whereas this embodiment requires no such necessity, allowing for providing remarkably reduced material and manufacturing costs.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a ball-grid-array semiconductor device and a manufacturing method therefor, and more particularly, to a ball-grid-array semiconductor device having a lead frame with terminal portions formed to protrude by etching, and its manufacturing method.
- 2. Description of the Related Art
- A package including a lead frame is available as one of semiconductor device packages that have been manufactured to meet the requirements for semiconductor devices such as higher-integration, miniaturization, decreasing in thickness, and higher pin count. A technique relating to a method for manufacturing lead frames that is applicable to ball-grid-array semiconductor devices is described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050. FIG. 1 is a cross-sectional view showing a conventional semiconductor device having a lead frame described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050.
- According to the prior art described in this publication, in a process where a sheet of metal is etched to form a lead frame, approximately a half of one side of the metal sheet is etched. This allows for forming projected
portions 110 a for use as external terminals on the side, which protrude in the direction of thickness of the metal sheet. Subsequently, an integratedcircuit 114 is attached with abonding portion 112 to the other side where the projectedportions 110 a of thelead frame 110 have not been formed. Then, these are sealed withresin 118. At this time, edges of the projectedportions 110 a and part of the sides of theresin 118 are coplanar. For the conventional semiconductor devices, such method was employed to manufacture thelead frame 110 having terminals for external connection in one process. - However, this presents a problem that it is difficult to clean flux residues remaining between a package and a substrate after the package has been mounted onto the substrate. This happens because the edges of the projected
portions 110 a, or external terminals, and part of sides of theresin 118 are coplanar. - A method of mounting solder balls onto the projected
portions 110 a is available to solve this problem, however, this method also presents a problem that material and manufacturing costs are hardly reduced. - An object of the present invention is to provide a ball-grid-array semiconductor device and manufacturing method therefor, which facilitates cleaning flux residues remaining in between the package and the substrate after having been mounted onto the substrate, and which provides drastically reduced material and manufacturing costs.
- According to one aspect of the present invention, a ball-grid-array semiconductor device comprises: a semiconductor element; a resin material which seals the semiconductor element; and a lead frame connected to the semiconductor element in the resin material. The lead frame has a terminal portion that protrudes through a surface of the resin material.
- According to another aspect of the present invention, a method for manufacturing a ball-grid-array semiconductor device comprises the steps of: forming a lead frame having a terminal portion that protrudes in the direction of thickness thereof; mounting a semiconductor element on the lead frame; connecting an electrode provided on the semiconductor device to the lead frame by means of a bonding wire; and sealing the semiconductor element with a resin material. The terminal portion protrudes through a surface of the resin material.
- The present invention allows the terminal portions to protrude through the surface of the resin material. Thus, the terminal portions can used as connecting terminals, as they are, to be mounted directly to the substrate, and cleaning of flux residues after mounting can be readily carried out. Therefore, conventional ball-grid-array semiconductor devices have required solder balls to be mounted on packages to facilitate cleaning flux residues, whereas the present invention requires no such necessity, allowing for providing remarkably reduced material and manufacturing costs.
- FIG. 1 is a cross-sectional view showing a conventional semiconductor device having a lead frame described in Japanese Patent Application Laid-Open No. Sho 60 (1985)-52050.
- FIG. 2 is a cross-sectional view showing the structure of a ball-grid-array semiconductor device according to an embodiment of the present invention.
- FIG. 3 is a bottom view showing the structure of the ball-grid-array semiconductor device according to the embodiment of the present invention.
- FIG. 4 is a view showing the method for manufacturing the ball-grid-array semiconductor device according to the embodiment of the present invention, illustrating the step where the device is sealed with resin.
- The embodiment of the present invention is to be explained specifically with reference to the accompanying drawings. FIG. 2 is a cross-sectional view showing the structure of a ball-grid-array semiconductor device according to the embodiment of the present invention. FIG. 3 is a bottom view showing the structure of the ball-grid-array semiconductor device similarly according to the embodiment of the present invention.
- A ball-grid-
array semiconductor device 1 according to this embodiment allows asemiconductor element 14 to be mounted with anadhesive tape 12 on alead frame 10 provided withterminal portions 10 a which protrude in the direction of thickness thereof. Thelead frame 10 is formed, for example, by etching a sheet of metal approximately a half of the thickness thereof. - Moreover,
bonding wires 16 connect thelead frame 10 to electrodes provided on thesemiconductor element 14. Then, they are sealed with aresin material 18 to be formed in a predetermined package shape. Incidentally, theterminal portions 10 a protrude through the substrate mount surface of theresin material 18. Moreover, asolder layer 19 is formed on the edges of theterminal portions 10 a. - The ball-grid-
array semiconductor device 1 of this embodiment constructed as such allows theterminal portions 10 a, on which thesolder layer 19 is formed, to be used as terminals as they are for being mounted on a substrate. - Incidentally, the
terminal portions 10 a can be etched into a variety of shapes such as a cylinder or a rectangular column. However, a cylindrical shape is desirable in which stress is unlikely to occur, when considering the heat-cycle resisting performance thereof after having been mounted on the substrate. - In addition, the
terminal portions 10 a have desirably a height ranging from 0.1 to 0.3 mm from the substrate mount surface, when considering the easiness of cleaning flux residues after having been mounted. - Furthermore, the
solder layer 19 to be formed on the edges ofterminal portions 10 a is desirably about 5 to 10 μm in thickness, which is equivalent in thickness to a solder layer to be applied to outer leads of resin-sealed semiconductor devices, typified by conventional QFP (Quad Flat Pack) semiconductor devices. - Next, a method for manufacturing the aforementioned semiconductor device of this embodiment is to be explained. FIG. 4 is a cross-sectional view showing the method for manufacturing the ball-grid-array semiconductor device according to the embodiment of the present invention, illustrating the step where the device is sealed with resin.
- First, a sheet of metal is etched approximately by half the thickness thereof to form a
lead frame 10 having theterminal portions 10 a that protrude in the direction of thickness. Subsequently, asemiconductor element 14 is mounted onto thelead frame 10 with an adhesive tape. Then, the electrodes provided on thesemiconductor element 14 are connected to thelead frame 10 by means ofbonding wires 16. - Subsequently, as shown in FIG. 4, the
lead frame 10, thesemiconductor element 14 and the like are sandwiched in between anupper metal mold 22 having acavity 22 a of a predetermined shape and alower metal mold 20 having recessedportions 20 a as a cavity for accommodating theterminal portions 10 a. Then, resin is allowed to flow in from an injection portion (not shown) which is in connection with thecavities lead frame 10 and thesemiconductor element 14 with the resin. - After the encapsulation with the resin has been completed, there will exist thin fins on the edges of the
terminal portions 10 a. Thus, those thin fins are removed by laser honing, sand blasting, water jet honing or the like in order to allow theterminal portions 10 a of thelead frame 10 to be exposed. Thereafter, asolder layer 19 is formed on the edges of theterminal portions 10 a. - Such method as mentioned above allows the
terminal portions 10 a of thelead frame 10 to protrude through the substrate mount surface of theresin material 18. - As described above, this embodiment allows the
terminal portions 10 a to protrude through the substrate mount surface of the package and thesolder layer 19 to be formed on the edges thereof. Therefore, theterminal portions 10 a can be used as connecting terminals, as they are, for being mounted directly to the substrate, and the cleaning of flux residues after the portions have been mounted can be readily carried out. Therefore, conventional ball-grid-array semiconductor devices have required solder balls to be mounted on packages to facilitate cleaning flux residues, whereas this embodiment requires no such necessity, allowing for providing remarkably reduced material and manufacturing costs.
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP36355798A JP3169919B2 (en) | 1998-12-21 | 1998-12-21 | Ball grid array type semiconductor device and method of manufacturing the same |
JP10-363557 | 1998-12-21 |
Publications (2)
Publication Number | Publication Date |
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US20010013639A1 true US20010013639A1 (en) | 2001-08-16 |
US6410979B2 US6410979B2 (en) | 2002-06-25 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/465,755 Expired - Fee Related US6410979B2 (en) | 1998-12-21 | 1999-12-17 | Ball-grid-array semiconductor device with protruding terminals |
Country Status (5)
Country | Link |
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US (1) | US6410979B2 (en) |
JP (1) | JP3169919B2 (en) |
KR (1) | KR100350759B1 (en) |
CN (1) | CN1258935A (en) |
TW (1) | TW437026B (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020020907A1 (en) * | 2000-03-25 | 2002-02-21 | Amkor Technology, Inc. | Semiconductor package |
US20020190396A1 (en) * | 2000-08-16 | 2002-12-19 | Brand Joseph M. | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
US6667544B1 (en) * | 2000-06-30 | 2003-12-23 | Amkor Technology, Inc. | Stackable package having clips for fastening package and tool for opening clips |
US20040256188A1 (en) * | 2001-10-05 | 2004-12-23 | Taylor Pty Ltd. | Retractable cable assemblies and devices including the same |
US20060079027A1 (en) * | 2002-05-16 | 2006-04-13 | Renesas Technology Corporation | Semiconductor device and its manufacturing method |
US20080296759A1 (en) * | 2007-06-04 | 2008-12-04 | Stats Chippac, Inc. | Semiconductor packages |
US20090079049A1 (en) * | 2007-09-20 | 2009-03-26 | Byung Tai Do | Integrated circuit package system with warp-free chip |
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Also Published As
Publication number | Publication date |
---|---|
TW437026B (en) | 2001-05-28 |
JP3169919B2 (en) | 2001-05-28 |
US6410979B2 (en) | 2002-06-25 |
CN1258935A (en) | 2000-07-05 |
KR100350759B1 (en) | 2002-08-28 |
KR20000048222A (en) | 2000-07-25 |
JP2000188353A (en) | 2000-07-04 |
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