US20010040460A1 - Method of making a high density integral test probe - Google Patents

Method of making a high density integral test probe Download PDF

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Publication number
US20010040460A1
US20010040460A1 US09/198,179 US19817998A US2001040460A1 US 20010040460 A1 US20010040460 A1 US 20010040460A1 US 19817998 A US19817998 A US 19817998A US 2001040460 A1 US2001040460 A1 US 2001040460A1
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Prior art keywords
contact
substrate
elongated
enlarged
electrically conductive
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US09/198,179
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US6332270B2 (en
Inventor
Brian Samuel Beaman
Keith Edward Fogel
Paul Alfred Lauro
Maurice H. Norcott
Da-Yuan Shih
George Frederick Walker
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GlobalFoundries Inc
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Individual
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Priority to US09/972,622 priority patent/US20020011001A1/en
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Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49204—Contact or terminal manufacturing
    • Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals

Definitions

  • the present invention is directed to probe structrues for testing of electrical interconnections to integrated circuit devices and other electronic components and particularly to testing integrated circuit devices with high density area array solder ball interconnections at high temperatures.
  • Integrated circuit (IC) devices and other electronic components are normally tested to verify the electrical function of the device and certain devices require high temperature burn-in testing to accelerate early life failures of these devices.
  • Wafer probing is typically done at temperatures ranging from 25 C. to 125 C. while typical burn-in temperatures ramge from 80 C. to 140 C.
  • Wafer probing and IC chip burn-in at elevated temperatures of up to 200 C. has several advantages and is becoming increasingly important in the semiconductor industry.
  • the various types of interconnection methods used to test these devices include permanent, semi-permanent, and temporary attachment techniques.
  • the permanent and semi-permanent techniques techniques athat are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fan out wiring or a metal lead frame package.
  • the temporary attachment techniques include rigid and flexible probes that are used to connect the IC device to a substrate with fan out wiring or directly to the test equipment.
  • the semi-permanent attachment techniques used for testing integrated circuit devices such as wire bonding to a leadframe of a plastic lead chip carrier are typically used for devices that have low number of interconnections and the plastic leaded chip carrier package is relatively inexpensive.
  • the device is tested through the wire bonds and leads of the plastic leaded chip carrier and plugged into a test socket. If the integrated circuit device is defective, the device and the plastic leaded chip carrier are discarded.
  • the semi-permanent attachment techniques used for testing integrated circuit devices such as solder ball attachment to a ceramic or plastic pin grid aray package are typically used for devices that have high number of interconnections and the pin grid array package is relatively expensive.
  • the device is tested through the solder balls and the internal fan out wiring and pins of the pin grid array package that is plugged into a test socket. If the integrated circuit device is defective, the device can be removed from the pin grid array package by heating the solder balls to their melting point. The processing cost of heating and removing the chip is offset by the cost saving of reusing the pin grid array package.
  • High temperature wafer probing and burn-in testing has a number of technical challenges.
  • Gold plated contacts are commonly used for testing and burn-in of IC devices.
  • the gold plated probes will interact with the solder balls on the IC device to form an intermatallic layer that has high electrical resistance andl brittIe mechanical properties.
  • the extent of the intermetallic formation is dependant on the temperature and duration of the contact between the gold plated probe and the solder balls on the IC device.
  • the gold-tin intermatallic contamination of the solder balls has a further effect of reducing the reliability of the flip chip interconection to the IC device.
  • Another problem caused by the high temperature test environment is diffusion of the base metal of the probe into the gold plated on the surface. The diffusion process is accelerated at high temperatures and causes a high resistive oxide layer to form on the surface of the probe contact.
  • a further object of the present invention is to provide an enlarged probe tip to facilitate alignment of the probe array to the contact array on the IC device for wafer probing.
  • An additional object of the present invention is to provide an enlarged probe tip to facilitate on the probe surface to inhibit oxidation, intermetallic formation, and out-diffusion of the contact interface at high temperatures.
  • Yet another object of the present invention is to provide a suitable polymer material for supporting the probe contacts that has a coefficient of thermal expansion that is matched to the substrate material and has a glass transition temperature greater than 200 C.
  • Yet a further object of the present invention s to provide a probe with a cup shaped geometry to contain the high temperature creep of the solder ball interconnection means on the integrated circuit devices during burn-in testing.
  • Yet an addition object of the present invention is to provide a probe with a cup shaped geometry to facilitate in aligning the solder balls on the integrated circuit device to the probe contact.
  • a broad aspect of the claimed invention is an apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon having: a substrate having a first surface and a second surface: a plurality of first electrical contact locations of the first side; a plurality of probe tips disposed on the first contact locations; each of the probe tips having an elongated electrically conductive member projecting from an enlarged base, the base being disposed on said contact locations; and, means for moving said substrate towards the work piece so that the plurality of probe tips are pressed into contact with plurality of contact locations on said work pieces.
  • Another broad aspect of the present invention is a method including the steps of: providing a substrate having a surface; shearing said elongated conductor from said ball bond leaving an exposed end of said elongated conductor, and flattening the exposed end.
  • FIG. 1 shows a cross section of a high density integral rigid test probe attached to a substrate and pressed against the solder balls on an integrated circuit device.
  • FIG. 2 shows an enlarged cross section of a single high density integral rigid test probe attached to the fan out wiring on the test substrate.
  • FIGS. 3 - 7 show the proccesses used to fabricate the high density itegral rigid test probe structure on a fan out wiring substrate.
  • FIG. 8 shows an alternate embodiment of the high density integral rigid test probe structure with a cup shaped geometry surronding the probe contact.
  • FIG. 9 shows an alternate embodiment of the high density integral rigid test probe with multiple probe arrays on a single substrate.
  • FIG. 10 shows the structure of FIG. 1 with contact locations on a second surface.
  • FIG. 11 shows the structure of FIG. 6 with conductive pins at the contact locations on the second surface.
  • FIG. 12 schematically shows the structure of FIG. 1 in combination with a means for moving the probe into engagement.
  • FIG. 1 shows a cross section of a test substrate ( 10 ) and high density integral rigid test probe ( 12 ) according to the present invention.
  • the test substrate ( 10 ) provides a rigid base for attachment of the probes structures ( 12 ) and fan out wiring from the high density array of probe contacts to a larger grid of pins or other interconnection means to the equipment used to electrically test the integrated circuit device.
  • the fan out substrate can be made from various materials andl constructions including single and multi-layer ceramic with thick or thin film wiring, silicon wafer with thin film wiring, or epoxy glass laminate construction with high density copper wiring.
  • the integral rigid test probes ( 12 ) are attached to the first surface ( 11 ) of the substrate ( 10 ).
  • the probes are used to contact the solder bralls ( 22 ) on the integrated circuit device ( 20 ).
  • the solder balls ( 22 ) are attached to the first surface ( 21 ) of the integrated circuit device ( 20 ).
  • FIG. 2 shows an enlarged cross section of the high density integral rigid test probe ( 12 ).
  • the probe tip is enlarged ( 13 ) to provide better alignment tolerance of the probe array to the array of solder balls ( 22 ) on the IC device ( 20 ).
  • the integral rigid test probe ( 12 ) is attached directly to the fan out wiring ( 15 ) on the first surface ( 11 ) of the substrate ( 10 ) to minimize the resistance of the probe interface.
  • the probe geometry includes the ball bond ( 16 ), the wire stud ( 17 ), and the enlarged probe tip ( 13 ).
  • a sheet of polymer material ( 40 ) with holes ( 41 ) corresponding to the probe positions is used to support the enlarged tip ( 13 ) of the probe geometry.
  • the BPDA-PDA polyimide can be used with a silicon wafer substrate since both have a coefficient of thermal expansion (TCE) of 3 ppm/C. This material is also stable up to 350 C.
  • FIG. 3 shows the first process used to fabricate the integral rigid test probe.
  • a thermosonic wire bonder tool is used to attach ball bonds ( 16 ) to the first surface ( 11 ) of the rigid substrate ( 10 ).
  • the wire bonder tool uses a first ceramic capillary ( 30 ) to press the ball shaped end of the bond wire against the first surface ( 11 ) of the substirite ( 10 ).
  • Compression force and ultrasonic energy ( 31 ) are applied through the first capillary ( 30 ) tip and thermal energy is applied from thle wire bonder stage through the substrate ( 10 ) to bond the ball shaped end of the bond wire to the first surface ( 11 ) of the substrate.
  • the bond wire is cut, sheared, or broken to leave a small stud ( 17 ) protruding vertically from the ball bond ( 16 ).
  • a first sheet of polymer material ( 40 ) with holes ( 41 ) corresponding to the probe locations on the substrate is placed over the array of wire studs ( 17 ) as shoown in FIG. 4.
  • the diameter of the holes ( 41 ) in the polymer sheet ( 40 ) is slightly larger than the diameter of the wire studs ( 17 ).
  • a second shect of metal or a hard polymer ( 42 ) with holes ( 43 ) corresponiding to the probe locations is also placed over the array of wire studs ( 17 ).
  • the diameter of the holes ( 43 ) in the metal sheet ( 42 ) is larger than the diameter of the holes ( 41 ) in the polymer sheet ( 40 ).
  • the enlarged ends of the probe tips are formed using a hardened anvil tool ( 50 ) as shown in FIG. 5. Compression force and ultrasonic energy ( 51 ) are applied through the anvil tool ( 50 ) to deform the ends of the wire studs ( 17 ).
  • the size of the enlarged probe tip ( 13 ) is controlled by the length of the wire stud ( 17 ) protruding through the polymer sheet ( 40 ), the thickness of the metal sheet ( 42 ), and the diameter of the holes ( 43 ) in the metal sheet ( 42 ).
  • the enlarged ends of the probes ( 13 ) can be formed individually or in multiples depending on the size of the anvil tool ( 50 ) that is used. Also, the surface finish of the anvil tool( 50 ) can be modified to provide a smooth or textured finish on the enlarged probe tips ( 13 ).
  • FIG 6 shows the high density integral rigid test probe with the metal mask ( 42 ) removed from the assembly.
  • FIG. 7 shows the sputtering or evaporation proces used to deposit the desired contact metallurgy ( 18 ) on the enlarged end ( 13 ) of the probe tip.
  • Contact metallurgies ( 18 ) such as Pt, Ir, Rh, Ru, and Pd can be deposited in the thickness range of 1000 to 5000 angstroms over the probe tip ( 13 ) to ensure low contact resistance with thermal stability and oxidation resistance when operated a elevated temperatures in air.
  • a thin layer of TiN, Cr, Ti, Ni, or Co can be used as a diffusion barrier ( 19 ) between the enlarged probe tip ( 13 ) and the contact metallurgy ( 18 ) on the surgace of the probe.
  • FIG. 8 shows a high density integral test probe ( 12 ) with an additional sheet of polyimide ( 44 ) with enlarged holes ( 45 ) corresponding to the probe location placed on top of the first sheet of polyimide ( 40 ).
  • the enlarged holes ( 45 ) in the second sheet of polyimide ( 44 ) acts as a cup to control and contain the creep of the solder balls at high temperatures.
  • Multiple probe arrays can be fabricated on a single substrate ( 60 ) as shown in FIG. 9. Each array of probes is decoupled from the adjacent arrays by using separate polyimide sheets ( 61 , 62 ). Matched coefficients of thermal expansion for the plymer sheets ( 61 , 62 ) and the substrate ( 60 ) become increasingly more important for multiple arrays of probes on a large substrate. Even slight differences in the coefficient of thermal expansion can result in bowing of the substrate or excessive stresses in the substrate and polymer material over a large area substrate.
  • FIG. 10 shows the structure of FIG. 1 with second contact locations ( 70 ) on surface ( 72 ) of substrate 10 .
  • Contact locations ( 70 ) can be the same as contact locations ( 13 ).
  • FIG. 11 shows the structure of FIG 6 with elongated ( 74 ) such as pins fixed to the surface ( 76 ) of pad ( 70 ).
  • FIG. 12 shows substrate ( 10 ) disposed spaced apart from the IC device ( 20 ).
  • Substrate ( 11 ) is held by arm ( 78 ) of fixture ( 80 ).
  • the IC device ( 20 ) is disposed on support ( 82 ) which is disposed in contact with fixture ( 80 ) by base ( 84 ).
  • Arm ( 78 ) is adapted for movement as indicated by arrow ( 86 ) towards base ( 84 ) so that probe tips ( 12 ) are brought into engagement with conductors ( 22 ).
  • An example of an apparatus providing a means for moving substrate ( 10 ) into engagement with the IC device ( 20 ) can be found in U.S. Pat. No. 4,875,614.

Abstract

A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.

Description

    FEILD OF THE INVENTION
  • The present invention is directed to probe structrues for testing of electrical interconnections to integrated circuit devices and other electronic components and particularly to testing integrated circuit devices with high density area array solder ball interconnections at high temperatures. [0001]
    • BACKGROUND OF THE INVENTION
  • Integrated circuit (IC) devices and other electronic components are normally tested to verify the electrical function of the device and certain devices require high temperature burn-in testing to accelerate early life failures of these devices. Wafer probing is typically done at temperatures ranging from 25 C. to 125 C. while typical burn-in temperatures ramge from 80 C. to 140 C. Wafer probing and IC chip burn-in at elevated temperatures of up to 200 C. has several advantages and is becoming increasingly important in the semiconductor industry. [0002]
  • The various types of interconnection methods used to test these devices include permanent, semi-permanent, and temporary attachment techniques. The permanent and semi-permanent techniques techniques athat are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fan out wiring or a metal lead frame package. The temporary attachment techniques include rigid and flexible probes that are used to connect the IC device to a substrate with fan out wiring or directly to the test equipment. [0003]
  • The semi-permanent attachment techniques used for testing integrated circuit devices such as wire bonding to a leadframe of a plastic lead chip carrier are typically used for devices that have low number of interconnections and the plastic leaded chip carrier package is relatively inexpensive. The device is tested through the wire bonds and leads of the plastic leaded chip carrier and plugged into a test socket. If the integrated circuit device is defective, the device and the plastic leaded chip carrier are discarded. [0004]
  • The semi-permanent attachment techniques used for testing integrated circuit devices such as solder ball attachment to a ceramic or plastic pin grid aray package are typically used for devices that have high number of interconnections and the pin grid array package is relatively expensive. The device is tested through the solder balls and the internal fan out wiring and pins of the pin grid array package that is plugged into a test socket. If the integrated circuit device is defective, the device can be removed from the pin grid array package by heating the solder balls to their melting point. The processing cost of heating and removing the chip is offset by the cost saving of reusing the pin grid array package. [0005]
  • The most cost effective techniques for testing and burn-in of integrated circuit devices provide a direct interconnection between the pads on the device to a probe sockets that is hard wired to the test equipment. Contemporary probes for testing integrated circuits are expensive to fabricate and are easily damaged. The individual probes are typically attached to a ring shaped printed circuit board and support cantilevered metal wires extending towards the center of the opening in the circuit board. Each probe wire must be aligned to a contact location on the integrated circuit device to be tested. The probe wires are generally fragile and easily deformed or damaged. This type of probe fixture is typically used for testing integrated circuit devices that have contacts along the perimeter of the device. This type of probe cannot be used for testing integrated Circuit devices that have high density area array contacts. Use of this type of probe for high temperature testing is limited by the probe structure and material set. [0006]
  • High temperature wafer probing and burn-in testing has a number of technical challenges. Gold plated contacts are commonly used for testing and burn-in of IC devices. At high temperatures, the gold plated probes will interact with the solder balls on the IC device to form an intermatallic layer that has high electrical resistance andl brittIe mechanical properties. The extent of the intermetallic formation is dependant on the temperature and duration of the contact between the gold plated probe and the solder balls on the IC device. The gold-tin intermatallic contamination of the solder balls has a further effect of reducing the reliability of the flip chip interconection to the IC device. Another problem caused by the high temperature test environment is diffusion of the base metal of the probe into the gold plated on the surface. The diffusion process is accelerated at high temperatures and causes a high resistive oxide layer to form on the surface of the probe contact. [0007]
    • OBJECT OF THE INVENTION
  • It is the object of the present invention to provide a probe for testing integrated Circuit devices and other electronic components, that use solder balls for the interconnection means. Another object of the present invention is to provide a probe that is an integral part of the fan out wiring on the test substance or other printed wiring means to minimize the contact resistance of the probe interface. [0008]
  • A further object of the present invention is to provide an enlarged probe tip to facilitate alignment of the probe array to the contact array on the IC device for wafer probing. [0009]
  • An additional object of the present invention is to provide an enlarged probe tip to facilitate on the probe surface to inhibit oxidation, intermetallic formation, and out-diffusion of the contact interface at high temperatures. [0010]
  • Yet another object of the present invention is to provide a suitable polymer material for supporting the probe contacts that has a coefficient of thermal expansion that is matched to the substrate material and has a glass transition temperature greater than 200 C. [0011]
  • Yet a further object of the present invention s to provide a probe with a cup shaped geometry to contain the high temperature creep of the solder ball interconnection means on the integrated circuit devices during burn-in testing. [0012]
  • Yet an addition object of the present invention is to provide a probe with a cup shaped geometry to facilitate in aligning the solder balls on the integrated circuit device to the probe contact. [0013]
    • SUMMARY OF THE INVENIION
  • A broad aspect of the claimed invention is an apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon having: a substrate having a first surface and a second surface: a plurality of first electrical contact locations of the first side; a plurality of probe tips disposed on the first contact locations; each of the probe tips having an elongated electrically conductive member projecting from an enlarged base, the base being disposed on said contact locations; and, means for moving said substrate towards the work piece so that the plurality of probe tips are pressed into contact with plurality of contact locations on said work pieces. [0014]
  • Another broad aspect of the present invention is a method including the steps of: providing a substrate having a surface; shearing said elongated conductor from said ball bond leaving an exposed end of said elongated conductor, and flattening the exposed end.[0015]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • these and other objects, features, and advantages of the present invention will become apparent upon further consideration with the drawing figures, in which: [0016]
  • FIG. 1 shows a cross section of a high density integral rigid test probe attached to a substrate and pressed against the solder balls on an integrated circuit device. [0017]
  • FIG. 2 shows an enlarged cross section of a single high density integral rigid test probe attached to the fan out wiring on the test substrate. [0018]
  • FIGS. [0019] 3-7 show the proccesses used to fabricate the high density itegral rigid test probe structure on a fan out wiring substrate.
  • FIG. 8 shows an alternate embodiment of the high density integral rigid test probe structure with a cup shaped geometry surronding the probe contact. [0020]
  • FIG. 9 shows an alternate embodiment of the high density integral rigid test probe with multiple probe arrays on a single substrate. [0021]
  • FIG. 10 shows the structure of FIG. 1 with contact locations on a second surface. [0022]
  • FIG. 11 shows the structure of FIG. 6 with conductive pins at the contact locations on the second surface. [0023]
  • FIG. 12 schematically shows the structure of FIG. 1 in combination with a means for moving the probe into engagement.[0024]
    • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 shows a cross section of a test substrate ([0025] 10) and high density integral rigid test probe (12) according to the present invention. The test substrate (10) provides a rigid base for attachment of the probes structures (12) and fan out wiring from the high density array of probe contacts to a larger grid of pins or other interconnection means to the equipment used to electrically test the integrated circuit device. The fan out substrate can be made from various materials andl constructions including single and multi-layer ceramic with thick or thin film wiring, silicon wafer with thin film wiring, or epoxy glass laminate construction with high density copper wiring. The integral rigid test probes (12) are attached to the first surface (11) of the substrate (10). The probes are used to contact the solder bralls (22) on the integrated circuit device (20). The solder balls (22) are attached to the first surface (21) of the integrated circuit device (20).
  • FIG. 2 shows an enlarged cross section of the high density integral rigid test probe ([0026] 12). The probe tip is enlarged (13) to provide better alignment tolerance of the probe array to the array of solder balls (22) on the IC device (20). The integral rigid test probe (12) is attached directly to the fan out wiring (15) on the first surface (11) of the substrate (10) to minimize the resistance of the probe interface. The probe geometry includes the ball bond (16), the wire stud (17), and the enlarged probe tip (13). A sheet of polymer material (40) with holes (41) corresponding to the probe positions is used to support the enlarged tip (13) of the probe geometry. It is desirable to match the coefficient of thermal expansion for the polymer sheet (40) material and the substrate material to minimize stress on the interface between the ball bond (16) and the fan out wiring (15). As an example, the BPDA-PDA polyimide can be used with a silicon wafer substrate since both have a coefficient of thermal expansion (TCE) of 3 ppm/C. This material is also stable up to 350 C.
  • FIG. 3 shows the first process used to fabricate the integral rigid test probe. A thermosonic wire bonder tool is used to attach ball bonds ([0027] 16) to the first surface (11) of the rigid substrate (10). The wire bonder tool uses a first ceramic capillary (30) to press the ball shaped end of the bond wire against the first surface (11) of the substirite (10). Compression force and ultrasonic energy (31) are applied through the first capillary (30) tip and thermal energy is applied from thle wire bonder stage through the substrate (10) to bond the ball shaped end of the bond wire to the first surface (11) of the substrate. The bond wire is cut, sheared, or broken to leave a small stud (17) protruding vertically from the ball bond (16).
  • A first sheet of polymer material ([0028] 40) with holes (41) corresponding to the probe locations on the substrate is placed over the array of wire studs (17) as shoown in FIG. 4. The diameter of the holes (41) in the polymer sheet (40) is slightly larger than the diameter of the wire studs (17). A second shect of metal or a hard polymer (42) with holes (43) corresponiding to the probe locations is also placed over the array of wire studs (17). The diameter of the holes (43) in the metal sheet (42) is larger than the diameter of the holes (41) in the polymer sheet (40). The enlarged ends of the probe tips are formed using a hardened anvil tool (50) as shown in FIG. 5. Compression force and ultrasonic energy (51) are applied through the anvil tool (50) to deform the ends of the wire studs (17). The size of the enlarged probe tip (13) is controlled by the length of the wire stud (17) protruding through the polymer sheet (40), the thickness of the metal sheet (42), and the diameter of the holes (43) in the metal sheet (42). The enlarged ends of the probes (13) can be formed individually or in multiples depending on the size of the anvil tool (50) that is used. Also, the surface finish of the anvil tool(50) can be modified to provide a smooth or textured finish on the enlarged probe tips (13). FIG 6 shows the high density integral rigid test probe with the metal mask (42) removed from the assembly.
  • FIG. 7 shows the sputtering or evaporation proces used to deposit the desired contact metallurgy ([0029] 18) on the enlarged end (13) of the probe tip. Contact metallurgies (18) such as Pt, Ir, Rh, Ru, and Pd can be deposited in the thickness range of 1000 to 5000 angstroms over the probe tip (13) to ensure low contact resistance with thermal stability and oxidation resistance when operated a elevated temperatures in air. A thin layer of TiN, Cr, Ti, Ni, or Co can be used as a diffusion barrier (19) between the enlarged probe tip (13) and the contact metallurgy (18) on the surgace of the probe.
  • FIG. 8 shows a high density integral test probe ([0030] 12) with an additional sheet of polyimide (44) with enlarged holes (45) corresponding to the probe location placed on top of the first sheet of polyimide (40). The enlarged holes (45) in the second sheet of polyimide (44) acts as a cup to control and contain the creep of the solder balls at high temperatures.
  • Multiple probe arrays can be fabricated on a single substrate ([0031] 60) as shown in FIG. 9. Each array of probes is decoupled from the adjacent arrays by using separate polyimide sheets (61,62). Matched coefficients of thermal expansion for the plymer sheets (61,62) and the substrate (60) become increasingly more important for multiple arrays of probes on a large substrate. Even slight differences in the coefficient of thermal expansion can result in bowing of the substrate or excessive stresses in the substrate and polymer material over a large area substrate.
  • FIG. 10 shows the structure of FIG. 1 with second contact locations ([0032] 70) on surface (72) of substrate 10. Contact locations (70) can be the same as contact locations (13). FIG. 11 shows the structure of FIG 6 with elongated (74) such as pins fixed to the surface (76) of pad (70).
  • FIG. 12 shows substrate ([0033] 10) disposed spaced apart from the IC device (20). Substrate (11) is held by arm (78) of fixture (80). The IC device (20) is disposed on support (82) which is disposed in contact with fixture (80) by base (84). Arm (78) is adapted for movement as indicated by arrow (86) towards base (84) so that probe tips (12) are brought into engagement with conductors (22). An example of an apparatus providing a means for moving substrate (10) into engagement with the IC device (20) can be found in U.S. Pat. No. 4,875,614.
  • While we have described our perferred embodiments of our invention, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be constructed to maintain the proper protection for the invention first disclosed. [0034]

Claims (43)

What is claimed is:
1. An apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon comprising:
a substrate having a first surface and a second surface;
a plurality of first electrical contact locations on said first side;
a plurality of probe tips disposed on said first contact locations;
each of said probe tips having an elongated electrically conductive member projecting from an enlarged base, said base being disposed on said contact locations:
means for moving said substrate towards said work piece so that said plurality of probe tips ireC pressed into contact with said plurality of contact locations on said work piece.
2. An apparatus according to
claim 1
 wherein said probe tip is formed from a material selected from the group consisting of Cu, Au, Al, Pd and Pt, and their alloys.
3. An apparatus according to
claim 2
 wherein said probe tip has at least one coating selected from the group consisting of Pt, Ir, Rh, Ru, Pd, Cr, Ti, TiN, Zr, ZrN and Co.
4. An apparatus according to
claim 2
 wherein said protuberance has a first coating selected from the group consisting of Cr, Ti, TiN, Ni, Zr, ZrN or Co and a second coating over said first coating selected from the group consisting of Pt, Ir, Rh, Ru and Pd.
5. An apparatus according to
claim 1
, wherein said substrate further includes a decoupling capacitor.
6. An apparatus according to
claim 1
, wherein said elongated member has a flattened end.
7. An apparatus according to
claim 1
 wherein said second surface has a plurality of second electrical contact locations thereon.
8. An apparatus according to
claim 1
, wherein said second contact locations have an elongated electrical conductor attached thereto.
9. An apparatus according to
claim 1
 wherein said substrate has electrical conductor patterns extending from said first surface to said second surface.
10. An apparatus according to
claim 1
, further including a sheet of material having a plurality of openings, said opening being positioned to align wtith said plurality probe tips, said sheet is disposed over said plurality of probe tips, said elongated electrically conductive members being disposecd in said opening.
11. An apparatus according to
claim 10
 wherein said elongated electrically conductive member has a first end disposed in contact with said enlarged base and a second end disposed in contact with an enlarged tip.
12. An apparatus according to
claim 10
 wherein said sheet is disposed between said enlarged base and said enlarged tip.
13. An apparatus according to
claim 10
, further including a layer or material disposed on said sheet, said layer having openings aligned with said probe tipts.
14. An apparatus according to
claim 13
, wherein openings in said layer are larger than said probe tip.
15. An appaaratus according to
claim 14
, wherein said contact locations on said Nvork piece are ball-shaped and wherein said openings in said layer are adapted to receive said contact location on said work piece having said ball shape.
16. A structure comprising:
a substrate having a surface;
a plurality of electrically conductive members disposed on said surface;
said electrically conductive members have an enlarged base, an elongated electrically conductive member in contact with said base and extending away from said base;
a sheet of material having a plurality of openings disposed for alignment with said plurality of electrically conductive members;
said sheet is disposed over said plurality of electrically conductive members with said elongated electrically conductive member extending through said plurality of openings.
17. An apparatus according to
claim 16
 Nwherein said elongated electrically conductive member has a first end disposed in contact with said enlarged base and a second end disposed in contact with an enlarged tip.
18. An apparatus according to
claim 16
 wherein said sheet is disposed between said enlarged base and said enlarged tip.
19. An apparatus according to
claim 16
. further including a layer of material disposed on said sheet, said layer having openings aligned with said probe tips.
20. An apparatus according to
claim 19
, wherein openings in said layer are larger than said probe tip.
21. An apparatus according to
claim 20
 wherein said contact locations on said work piece are ball-shaped and wherein said openings in said layer are adapted to receive said contact location on said work piece having said ball shape.
22. A structure according to
claim 16
 wherein said structure is an apparatus for electrically testing a work piece having a plurality of electrically conductive contact locations thereon.
23. A structure comprising:
a substrate having a surface;
a plurality of electrically conductive members disposed on said surface;
said electrically conductive members have an elongated base, an elongated electrically conductive member in contact with said base and having an end extending away from said base;
said end being enlarged.
24. A method comprising the steps of:
providing a substrate having a surface;
bonding an elongated electrical conductor to said surface by forming a ball bond at said surface;
shearing said elongated conductor from said ball bond leaving an exposed end of said elongated conductor;
flattening said exposed end.
25. A method according to
claim 24
, further including the steps of:
providing a sheet of material having an opening therein;
disposing said sheet with respect to said surface so that said elongated conductor extends within said opening.
26. A method according to
claim 25
, further including disposing on said sheet a layer of material having an opening therein through which said elongated electrically conductive member is exposed.
27. A method according to
claim 24
. further including the step of moving said substrate towards a work piece so that said plurality, of elongated electrical conductors are placed into electrical contact with a plurality of electrical conductors on a work piece.
28. A method according to
claim 24
 wherein said elongated electrical conductor is formed from a material selected from the group consisting of Cu, Au, Al, Pd and Pt, and their alloys.
29. A method according to
claim 28
 further including disposing said exposed end at least one coating selected from the group consisting of Pt, Ir, Rh, Ru, Pd, Dr, Ti, TiN, Zr, ZrN and Co.
30. A method according to
claim 28
 further including disposing on said exposed end a first coating selected from the group consisting of Cr, Ti, TiN, Ni, Zr, ZrN or Co and disposing a second coating over said first coating selected from the group consisting of Pt, Ir, Rh, Ru and Pd.
31. A method according to
claim 24
 further including disposing on said substrate a decoupling capacitor.
32. A method according to
claim 24
 wherein said elongated electrical conductors are ball bonded to electrical contact locations on said surface.
33. A method according to
claim 24
 wherein said substrate has another surface having a plurality of electrical contact locations thereon.
34. A method according to
claim 33
 wherein said contact locations on said another surface have elongated electrical conductor attached thereto.
35. A method according to
claim 24
 wherein said substrate has electrical conductor patterns therein.
36. An apparatus for making electrical contact with a plurality of solder balls on an integrated circuit device comprising:
first fan out substrate having a first surface; said first surface having a plurality of contact locations; a plurality of ball bonds attached to said plurality of contact locations; a plurality or short studs extending outward from said ball bonds, away from said first surface on fan out substrate.
37. An apparatus according to
claim 36
, further including an enlarged contact surface at the end of said studs.
38. An apparatus according to
claim 36
, wherein said plurality of ball bonds and short studs are surrounded by a layer of polymer material.
39. An apparatus according to
claim 38
, wherein said polymer material has a coefficient of thermal expansion that is matched to the first fan out substrate and has a glass transition temperature greater than 200 C.
40. An apparatus according to
claim 37
, wvberein said enlarged contact surface has a first metal layer deposited to inhibit oxidation and diffusion of the interface at temperatures up to 200 C; said first metal layer includes a material selected from the group consisting or Pt, Lr, Rh,. Ru and Pd.
41. An apparatus according to
claim 41
, wherein a second layer of metal is used between said enlarged contact surface and said first metal layer to prevent out-diffusion of the underlying material; said second metal layer includes a material selected from the group consisting of to TiN, Cr, Ni, and Co.
42. An apparatus according to
claim 39
, wherein said fan out substrate is selected from the group consisting of mullilayer ceramic substrates with thick film wiring; multilayer ceramic substrates with thin film wiring; metallized ceramic substrates with thin film wiring; epoxy glass laminate substrates with copper wiring; and, silicon substrates with thin film wiring
43. An apparatus according to
claim 38
, wherein a second layer of polymer material with enlarged holes corresponding to the said plurality of contact locations is placed over said first layer of polymer material and aligned with said enlarged contact surfaces to form a cup shaped geometry. Y0995-023 19
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050039330A1 (en) * 2002-08-02 2005-02-24 National Semiconductor Corporation Apparatus and method for force mounting semiconductor packages to printed circuit boards
US7944224B2 (en) 2005-12-07 2011-05-17 Microprobe, Inc. Low profile probe having improved mechanical scrub and reduced contact inductance
US7952377B2 (en) * 2007-04-10 2011-05-31 Microprobe, Inc. Vertical probe array arranged to provide space transformation
US8111080B2 (en) 2004-05-21 2012-02-07 Microprobe, Inc. Knee probe having reduced thickness section for control of scrub motion
US8203353B2 (en) 2004-07-09 2012-06-19 Microprobe, Inc. Probes with offset arm and suspension structure
USRE43503E1 (en) 2006-06-29 2012-07-10 Microprobe, Inc. Probe skates for electrical testing of convex pad topologies
US8230593B2 (en) 2008-05-29 2012-07-31 Microprobe, Inc. Probe bonding method having improved control of bonding material
USRE44407E1 (en) 2006-03-20 2013-08-06 Formfactor, Inc. Space transformers employing wire bonds for interconnections with fine pitch contacts
US8723546B2 (en) 2007-10-19 2014-05-13 Microprobe, Inc. Vertical guided layered probe
US8907689B2 (en) 2006-10-11 2014-12-09 Microprobe, Inc. Probe retention arrangement
US20150061713A1 (en) * 2013-08-29 2015-03-05 David Shia Anti-rotation for wire probes in a probe head of a die tester
US8988091B2 (en) 2004-05-21 2015-03-24 Microprobe, Inc. Multiple contact probes
US9097740B2 (en) 2004-05-21 2015-08-04 Formfactor, Inc. Layered probes with core
US9476911B2 (en) 2004-05-21 2016-10-25 Microprobe, Inc. Probes with high current carrying capability and laser machining methods
US20190098769A1 (en) * 2017-09-28 2019-03-28 Ngk Spark Plug Co., Ltd. Wiring substrate for electronic component inspection apparatus
US10998289B2 (en) * 2018-07-19 2021-05-04 Tongfu Microelectronics Co., Ltd. Packaging structure and forming method thereof

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914613A (en) 1996-08-08 1999-06-22 Cascade Microtech, Inc. Membrane probing system with local contact scrub
JPH11354561A (en) * 1998-06-09 1999-12-24 Advantest Corp Bump and method for forming the same
US6256882B1 (en) 1998-07-14 2001-07-10 Cascade Microtech, Inc. Membrane probing system
DE10143173A1 (en) 2000-12-04 2002-06-06 Cascade Microtech Inc Wafer probe has contact finger array with impedance matching network suitable for wide band
US20020173072A1 (en) * 2001-05-18 2002-11-21 Larson Thane M. Data capture plate for substrate components
AU2002327490A1 (en) 2001-08-21 2003-06-30 Cascade Microtech, Inc. Membrane probing system
US6744246B2 (en) * 2002-03-29 2004-06-01 Tektronix, Inc. Electrical probe
US6815963B2 (en) * 2002-05-23 2004-11-09 Cascade Microtech, Inc. Probe for testing a device under test
US7057404B2 (en) 2003-05-23 2006-06-06 Sharp Laboratories Of America, Inc. Shielded probe for testing a device under test
US6937039B2 (en) * 2003-05-28 2005-08-30 Hewlett-Packard Development Company, L.P. Tip and tip assembly for a signal probe
US20040249825A1 (en) * 2003-06-05 2004-12-09 International Business Machines Corporation Administering devices with dynamic action lists
TWI278950B (en) * 2003-07-10 2007-04-11 Toshiba Corp Contact sheet for testing of electronic parts, testing device for electronic parts, testing method for electronic parts, manufacturing method for electronic parts, and the electronic parts
US8641913B2 (en) * 2003-10-06 2014-02-04 Tessera, Inc. Fine pitch microcontacts and method for forming thereof
US7495179B2 (en) * 2003-10-06 2009-02-24 Tessera, Inc. Components with posts and pads
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7427868B2 (en) 2003-12-24 2008-09-23 Cascade Microtech, Inc. Active wafer probe
US8207604B2 (en) * 2003-12-30 2012-06-26 Tessera, Inc. Microelectronic package comprising offset conductive posts on compliant layer
US7176043B2 (en) * 2003-12-30 2007-02-13 Tessera, Inc. Microelectronic packages and methods therefor
US7709968B2 (en) 2003-12-30 2010-05-04 Tessera, Inc. Micro pin grid array with pin motion isolation
US7420381B2 (en) 2004-09-13 2008-09-02 Cascade Microtech, Inc. Double sided probing structures
WO2006031280A2 (en) * 2004-09-13 2006-03-23 Microfabrica Inc. Probe arrays and method for making
CN101053079A (en) 2004-11-03 2007-10-10 德塞拉股份有限公司 Stacked packaging improvements
JP4709535B2 (en) * 2004-11-19 2011-06-22 株式会社東芝 Semiconductor device manufacturing equipment
US7656172B2 (en) 2005-01-31 2010-02-02 Cascade Microtech, Inc. System for testing semiconductors
US7535247B2 (en) 2005-01-31 2009-05-19 Cascade Microtech, Inc. Interface for testing semiconductors
US20100104739A1 (en) * 2005-12-20 2010-04-29 Wen-Yu Lu Surface treating method for probe card in vacuum deposition device
US20070138017A1 (en) * 2005-12-20 2007-06-21 Chih-Chung Wang Treating method for probes positioned on a test card
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
US8067267B2 (en) * 2005-12-23 2011-11-29 Tessera, Inc. Microelectronic assemblies having very fine pitch stacking
US20070152685A1 (en) * 2006-01-03 2007-07-05 Formfactor, Inc. A probe array structure and a method of making a probe array structure
US7723999B2 (en) 2006-06-12 2010-05-25 Cascade Microtech, Inc. Calibration structures for differential signal probing
US7403028B2 (en) 2006-06-12 2008-07-22 Cascade Microtech, Inc. Test structure and probe for differential signals
US7764072B2 (en) 2006-06-12 2010-07-27 Cascade Microtech, Inc. Differential signal probing system
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
US7876114B2 (en) 2007-08-08 2011-01-25 Cascade Microtech, Inc. Differential waveguide probe
US8558379B2 (en) 2007-09-28 2013-10-15 Tessera, Inc. Flip chip interconnection with double post
US8212156B2 (en) * 2008-06-26 2012-07-03 International Business Machines Corporation Plastic land grid array (PLGA) module and printed wiring board (PWB) with enhanced contact metallurgy construction
US20100044860A1 (en) * 2008-08-21 2010-02-25 Tessera Interconnect Materials, Inc. Microelectronic substrate or element having conductive pads and metal posts joined thereto using bond layer
US7888957B2 (en) 2008-10-06 2011-02-15 Cascade Microtech, Inc. Probing apparatus with impedance optimized interface
US8410806B2 (en) 2008-11-21 2013-04-02 Cascade Microtech, Inc. Replaceable coupon for a probing apparatus
US8330272B2 (en) 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US8580607B2 (en) 2010-07-27 2013-11-12 Tessera, Inc. Microelectronic packages with nanoparticle joining
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US8853558B2 (en) 2010-12-10 2014-10-07 Tessera, Inc. Interconnect structure
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
JP2013206707A (en) * 2012-03-28 2013-10-07 Fujitsu Ltd Mounting adaptor, printed circuit board and manufacturing method therefor
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
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US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) * 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
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US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
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US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5914614A (en) * 1996-03-12 1999-06-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US5811982A (en) * 1995-11-27 1998-09-22 International Business Machines Corporation High density cantilevered probe for electronic devices
US5785538A (en) * 1995-11-27 1998-07-28 International Business Machines Corporation High density test probe with rigid surface structure
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7171745B2 (en) 2002-08-02 2007-02-06 National Semiconductor Corporation Apparatus and method for force mounting semiconductor packages to printed circuit boards
US20050039330A1 (en) * 2002-08-02 2005-02-24 National Semiconductor Corporation Apparatus and method for force mounting semiconductor packages to printed circuit boards
US8988091B2 (en) 2004-05-21 2015-03-24 Microprobe, Inc. Multiple contact probes
US9476911B2 (en) 2004-05-21 2016-10-25 Microprobe, Inc. Probes with high current carrying capability and laser machining methods
US9316670B2 (en) 2004-05-21 2016-04-19 Formfactor, Inc. Multiple contact probes
US8111080B2 (en) 2004-05-21 2012-02-07 Microprobe, Inc. Knee probe having reduced thickness section for control of scrub motion
US9097740B2 (en) 2004-05-21 2015-08-04 Formfactor, Inc. Layered probes with core
US8203353B2 (en) 2004-07-09 2012-06-19 Microprobe, Inc. Probes with offset arm and suspension structure
US8415963B2 (en) 2005-12-07 2013-04-09 Microprobe, Inc. Low profile probe having improved mechanical scrub and reduced contact inductance
US7944224B2 (en) 2005-12-07 2011-05-17 Microprobe, Inc. Low profile probe having improved mechanical scrub and reduced contact inductance
USRE44407E1 (en) 2006-03-20 2013-08-06 Formfactor, Inc. Space transformers employing wire bonds for interconnections with fine pitch contacts
USRE43503E1 (en) 2006-06-29 2012-07-10 Microprobe, Inc. Probe skates for electrical testing of convex pad topologies
US8907689B2 (en) 2006-10-11 2014-12-09 Microprobe, Inc. Probe retention arrangement
US9274143B2 (en) 2007-04-10 2016-03-01 Formfactor, Inc. Vertical probe array arranged to provide space transformation
US8324923B2 (en) 2007-04-10 2012-12-04 Microprobe, Inc. Vertical probe array arranged to provide space transformation
US7952377B2 (en) * 2007-04-10 2011-05-31 Microprobe, Inc. Vertical probe array arranged to provide space transformation
US8723546B2 (en) 2007-10-19 2014-05-13 Microprobe, Inc. Vertical guided layered probe
US8230593B2 (en) 2008-05-29 2012-07-31 Microprobe, Inc. Probe bonding method having improved control of bonding material
US20150061713A1 (en) * 2013-08-29 2015-03-05 David Shia Anti-rotation for wire probes in a probe head of a die tester
US9535095B2 (en) * 2013-08-29 2017-01-03 Intel Corporation Anti-rotation for wire probes in a probe head of a die tester
US20190098769A1 (en) * 2017-09-28 2019-03-28 Ngk Spark Plug Co., Ltd. Wiring substrate for electronic component inspection apparatus
US10674614B2 (en) * 2017-09-28 2020-06-02 Ngk Spark Plug Co., Ltd. Wiring substrate for electronic component inspection apparatus
US10998289B2 (en) * 2018-07-19 2021-05-04 Tongfu Microelectronics Co., Ltd. Packaging structure and forming method thereof

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