US20010052107A1 - Integrated verification and manufacturability tool - Google Patents
Integrated verification and manufacturability tool Download PDFInfo
- Publication number
- US20010052107A1 US20010052107A1 US09/747,190 US74719000A US2001052107A1 US 20010052107 A1 US20010052107 A1 US 20010052107A1 US 74719000 A US74719000 A US 74719000A US 2001052107 A1 US2001052107 A1 US 2001052107A1
- Authority
- US
- United States
- Prior art keywords
- layout
- verification
- operations
- integrated
- integrated device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
Definitions
- the invention relates to design tools for integrated device layouts. More particularly, the invention relates to an integrated tool for use in modifying and verifying integrated device layouts.
- FIG. 1 illustrates one approach to conversion of the netlist to a physical layout.
- the layout defines the specific dimensions of the gates, isolation regions, interconnects, contacts, and other device elements that form the physical devices, and usually represents these shapes with polygons defining their boundaries.
- the layout typically contains data layers that correspond to the actual layers to be fabricated in the circuit.
- the layout also contains cells, which define sets of particular devices within the circuit.
- Cells typically contain all the polygons on all the layers required for the fabrication of the devices it contains. Cells can be nested within other cells, often in very intricate arrangements.
- the structure of cells is often called a data hierarchy.
- Typical formats for the polygons of a physical layout are GDS II, or CIF.
- the layout is verified to ensure that the transformation from netlist to layout has been properly executed and that the final layout created adheres to certain geometric design rules.
- These layout verification operations are often called LVS (layout versus schematic) and DRC (design rule check), respectively.
- LVS layout versus schematic
- DRC design rule check
- DRACULATM from Cadence Design Systems of San Jose, Calif.
- HERCULESTM from Avant! Corporation of Fremont, Calif.
- CALIBRE® from Mentor Graphics of Wilsonville, Oreg.
- the designer must then repair the fault before the layout is sent to a mask shop for mask manufacturing and wafer fabrication.
- FIG. 2 illustrates an enhanced approach to conversion of the netlist to a physical layout. This provides a simulation based software engine that predicts what manufacturing distortions will occur during lithographic patterning. If the magnitude of these errors is determined to be significant, corrections are made using some form of Optical and Process Correction (OPC). OPC can correct for image distortions, optical proximity effects, photoresist kinetic effects, etch loading distortions, and other various process effects. Phase-shifting features can also be added to the layout at this point to enhance contrast.
- OPC Optical and Process Correction
- FIG. 3 is a conceptual illustration of an example of such a prior art process of integrated circuit (IC) design verification and correction. Each of the required process steps is executed by a stand-alone software tool.
- Original IC layout 300 describes the physical circuit layers from which masks and/or reticles are created to realize the circuit described by the design layout: the original IC layout 300 can be, for example, a GDS-II description of the circuit to be manufactured.
- Data import process 310 converts original IC layout 300 to a format for storage in database 315 .
- the data, as stored in verification database 315 is used by layout versus schematic (LVS) tool 320 and design rule checking (DRC) tool 325 to verify the design of original IC layout 300 .
- LVS layout versus schematic
- DRC design rule checking
- the data stored in verification database 315 is exported by data export process 330 .
- the data is then imported by a data import process 335 , which converts the exported data to a format used for a phase shift mask (PSM) database 340 .
- PSM tool 345 operates on the data stored in PSM database 340 to perform phase shifting where appropriate. Examples of stand alone PSM assignment tools are SEED, discussed in the reference by Barouch, above, and the IN-PhaseTM product available from Numerical Technologies of San Jose, Calif.
- the data describing the phase shifted layout(s) are exported from PSM database 340 by a data export process 350 .
- a data import process 355 imports the data generated by the PSM tool to an optical process correction (OPC) database 360 .
- OPC database 360 is typically a flat database, meaning that all the polygons of a layer of the circuit are contained within a single cell, with no hierarchical structure.
- Data import process 355 typically converts data from a hierarchical representation to a flat representation.
- OPC tool 365 performs OPC operations on the data stored in OPC database 360 . Examples of stand alone OPC tools are OPTIMASK, discussed in the reference by Barouch, above, and TaurusTM available from Avant! Corporation.
- a data export process 370 exports the data stored in OPC database 360 .
- the data generated by the OPC tool is then typically imported into a simulation tool, to confirm that the OPC will have the desired corrective effect. This is sometimes called an optical and process rule check, or ORC. Once this check is complete, the data is exported for use in IC manufacturing process 395 .
- LVS tool 320 and/or DRC tool 325 can also be used on the output of OPC database 360 . Performing another check with LVS tool 320 and/or DRC tool 325 requires another import and export by data import process 310 and data export process 330 , respectively.
- An integrated verification and manufacturability tool having a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical or flat manner, which is used not only for standard DRC and LVS verifications, but is also capable of performing optical and process correction (OPC) and other data manipulation techniques, including phase-shifting mask (PSM) assignment and silicon simulation for optical and process rule checking (ORC).
- OPC optical and process correction
- PSM phase-shifting mask
- ORC optical and process rule checking
- an integrated software tool exports the verified data in the database in a machine language that can be read by a mask writer to produce one or more photolithographic masks.
- FIG. 2 illustrates a modified flow, which accommodates additional process steps of OPC and PSM generation.
- FIG. 3 is a conceptual illustration of a prior art implementation of integrated circuit design verification incorporating these additional steps.
- FIG. 4 is a conceptual illustration of an integrated verification and manufacturability tool.
- FIG. 4A shows an alternative embodiment of the invention wherein the integrated verification and manufacturability tool includes a component that exports verified data in a machine language that can be read by a mask writer.
- FIG. 6 illustrates one embodiment of a computer system suitable for use in practicing the invention.
- FIG. 7 is a flow diagram of one embodiment of design verification with an integrated verification and manufacturability tool.
- Integrated devices include integrated circuits, micromachines, thin film structures such as disk drive heads, gene chips, microelectromechanical systems (MEMS), or any other article of manufacture that is manufactured using lithography techniques.
- MEMS microelectromechanical systems
- the integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools.
- the integrated verification and manufacturability tool includes a hierarchical database to store design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment).
- the hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Designs can include only a single layer; however, the hierarchical database can include one or more intermediate layers for a single layer original design. Use of a single hierarchical database for multiple verification steps streamlines the verification process, which provides an improved verification tool.
- FIG. 4 is a conceptual illustration of an integrated verification and manufacturability tool.
- the integrated verification and manufacturability tool of FIG. 4 includes a single hierarchical database that is used by each component within the tool.
- the integrated verification and manufacturability tool includes a database and multiple components.
- the components perform the core functionality of the individual stand alone tools of FIG. 3; however, because they are included in an integrated verification and manufacturability tool, the individual components are not referred to as tools.
- Use of a single database for multiple components reduces the time and effort required for the verification process.
- FIG. 4 illustrates an LVS component, a DRC component, an optical rule checking (ORC) component, a PSM component, an OPC component, and an “other” component 470 indicating that additional components can be added to the integrated verification and manufacturability.
- ORC optical rule checking
- PSM component
- OPC OPC component
- other component 470 indicating that additional components can be added to the integrated verification and manufacturability.
- fewer components can be used, for example, only a DRC and an OPC component might be used.
- the tool scans a listing of desired operations to be performed, sometimes called a “ruledeck,” to determine the required inputs and outputs.
- the tool then reads in the required input layers from the input database and creates empty output layers, to be filled during computation.
- several intermediate or “working” layers may be created to hold temporary computation results.
- all inputs, outputs and intermediate results are geometry collections called “layers,” defined as a collection of geometry in one or more cells of the layout. This definition is the same as a definition of a layer in the well known GDS II database standard format for representing layouts. Layers also allow hierarchical data representation.
- Hierarchical database 410 is formed and the list of required layers compiled, computations are carried out to fill the desired output layers.
- the information stored in hierarchical database 410 is exported by data export process 480 .
- the exported data can be used by IC manufacturing process 395 to manufacture the IC design.
- LVS component 440 , DRC component 450 , ORC component 460 , PSM component 420 , OPC component 430 , and any other component(s), as indicated by “other” 470 operate on hierarchical data representing original IC layout 300 as stored in hierarchical database 410 .
- LVS component 440 , DRC component 450 , ORC component 460 , PSM component 420 , and OPC component 430 operate on a hierarchical representation of edges that describe original IC layout 300 .
- the various components use the edge representations and the structures in the intermediate layers included in hierarchical database 410 to perform the respective operations.
- an integrated verification and manufacturability tool includes a component that can add arrays of regular features, such as small squares to the layout in order to help with the planarization, or physical flatness, of the fabricated silicon. These features are sometimes called “dummy fill” or “planarization fill.” By analyzing the density of the features in the layout, low-density areas are identified and filled in with new features.
- FIG. 5 illustrates operation of one embodiment of an integrated verification and manufacturability tool.
- the integrated verification and manufacturability tool can be executed by one or more computer systems.
- integrated verification and manufacturability tool 500 imports data from original database 520 into modified database 510 .
- Original database 520 can store the design to be verified in a relatively standard format, for example, GDS-II, while modified database 510 can store the design in a modified standard format, or in an independent format.
- importation includes executing hierarchical injection and/or bin injection.
- the integrated verification and manufacturability tool 500 receives the data in the modified/independent format.
- Hierarchical injection is a technique in which recurring patterns of cell placements are recognized and replaced with new cells that contain the patterns.
- Hierarchical injection creates a more efficient representation of original database 520 by reducing the number of redundant patterns of cell placements, or contexts.
- specially designed heuristics are used to recognize the patterns and to determine the correct representation by the new cells.
- the heuristics include, for example, the injection of hierarchy into arrays and the selective flattening of densely overlapping structures. In many layouts, arrays of a cell are described inefficiently from a verification perspective. The hierarchical injection heuristics recognize arrays and redefine rows, columns or small sub-arrays as new cells.
- This added hierarchy reduces the amount of geometry promoted during the computation phase by greatly reducing the number of redundant interactions between placements in the array.
- circuits for example FPGAs
- two large cells or arrays of cells will overlap each other to a large extent. This configuration is called a “dense overlap.”
- Hierarchical injection recognizes such instances and first flattens selected cells that overlap, and then re-introduces new, less interaction-prone cell structures.
- Bin injection is a process of dividing flat layout geometry into cells. Bin injection can also be applied to a random collection of cells, to reconfigure the cell structure more efficiently. In one embodiment, bin injection is accomplished by dividing a layout not by cell names, but by geometric grid. Bin injection is one technique for converting a flat layout into a hierarchical layout.
- each component e.g., LVS, DRC, PSM, OPC, ORC
- each component operates on groups of geometric figures that represent portions of the layout of the integrated device design. These groups are generally referred to as an “edge collection.”
- An edge collection contains edges from a design that may be organized into polygons, depending on the nature of the operations. Typical edge collections may contain only the edges of a single cell, others may contain the edges of a cell and nearby elements, while others might contain all edges within an arbitrary boundary. Edges may be retrieved from the edge collection either as whole polygons, if the data they represent consists of polygons, or as free edges. Once retrieved and manipulated, new edges representing the output of the operation are stored in a layer from which the edges are retrieved and/or a previously unused intermediate layer in modified database 510 .
- Selective promotion is a technique in which certain geometries in cells that have an effect on nearby cells are “promoted” to another level of the hierarchy. This promotion prevents the geometry in a cell from having conflicting behavior depending on the placement of the cell. For example, for a cell that has geometry very close to its own border, one placement of this cell may be isolated, but another placement may be close to another cell. In this case, the computed result for the geometry near the border may be different in each placement due to interaction with the nearby cell.
- the conflicting geometry close to the border is “promoted,” or flattened, to the next level of the hierarchy. This creates two versions of the geometry, one for each placement of the cell, each of which will produce different computational results. By reducing the number of unique interactions and conflicting geometries, the amount of promoted geometry is minimized, resulting in less computation and smaller file size. Promotion can be accomplished recursively.
- modified database 510 provides several performance advantages. For example, previous verification tools typically used a cell cloning scheme to eliminate redundant contexts. However, some designs resulted in a very large number of clones which slowed the verification process. Selective promotion and hierarchical injection reduces, or even eliminates, redundant contexts in a more efficient manner, which allows the verification process to be completed more quickly than using a cloning-based technique.
- cloning techniques are based on the assumption that all inter-cell interactions are local. That is, interaction distances are bounded.
- interaction distances are potentially unbounded. This requires a potentially unbounded number of cell clones, which would make hierarchical phase assignment impractical.
- the integrated verification and manufacturability tool includes an LVS component 440 and a DRC component 450 that perform both LVS verification operations and DRC verification operations on the edge collection stored in modified database 510 .
- LVS verification operations and DRC verification operations are performed by separate components.
- the LVS verification operations analyze the edge collection to determine whether the layout accurately corresponds to the schematic design.
- the edge collection is compared to a netlist corresponding to the design to determine whether the layout accurately represents the netlist representation. Errors identified by the LVS component can be flagged, identified and possibly corrected.
- data generated by the LVS component and/or the corrected layout are stored in one or more intermediate layers in modified database 510 .
- the DRC verification operations analyze the edge collection to determine whether any design rule violations exist.
- Design rules can include, for example, minimum line spacings, minimum line widths, minimum gate widths, or other geometric layout parameters.
- the design rules are based on, for example, the manufacturing process to be used to manufacture the resulting design layout.
- errors identified by the DRC component can be flagged, identified and possibly corrected.
- data generated by the DRC component and/or the corrected layout are stored in one or more intermediate layers in modified database 510 .
- ORC component 460 analyzes the edge collection by simulating the performance expected on the wafer, and determining whether the wafer structures will violate a set of fabrication tolerances. ORC component 460 can also operate on the edge collection that represents the original layout, for example, prior to LVS and DRC being performed on the layout. As with the LVS and DRC components, errors identified by the ORC component can be flagged and identified and possibly corrected.
- PSM component 420 operates on an edge collection as modified by ORC component 460 ; however PSM component 420 can operate on other edge collections also.
- PSM component 420 creates phase shifting assignments for reticles of the design stored in modified database 510 . Phase shifting assignments can be made, for example, to enable extremely small gate widths and/or line widths. The resulting layers and/or reticle layers are stored in intermediate layers in modified database 510 .
- OPC component 430 operates on the edge collection as modified by PSM component 420 and stored in one or more intermediate layers in modified database 510 .
- OPC component 430 can also operate on the edge collection that represents the original layout, for example, if PSM is not performed on the layout.
- rule-based OPC Two general categories of OPC are currently in use: rule-based OPC and model based OPC; one or both of which can be applied.
- rule-based OPC a reticle layout is modified according to a set of fixed rules for geometric manipulation.
- model-based OPC an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated result generated based on the model used.
- OPC component 460 modifies the placement of one or more edges to provide improved optical performance of one or more reticles.
- One example of rule-based OPC that can be applied to a layout is the addition of assist features, for example, sub-resolution bars along an interconnection line, hammer head shapes at line ends, or serifs at a line corner. Other assist features can also be provided.
- OPC component 460 can also modify placement of one or more edges based on models that predict the structures that will be produced using specific reticle layouts.
- the reticle layouts can be modified based on the results of the prediction to compensate for deficiencies that are identified by the modeling results.
- the results Generated by OPC component 460 are stored in one or more intermediate layers in modified database 510 .
- the other component 470 of the integrated verification and manufacturability tool shown in FIG. 4A converts the optimized, shared data within the database into a format that can be supplied directly to a mask creating tool.
- Most mask creating tools use layout data in machine specific formats, such as MEBES for E-Beam and laser rasterizing writing tools, such as those from ETEC systems (an applied Materials Company), Hitachi format for Hitachi vector scan E-beam mask writers, .MIC format for hierarchical processing in mask writers from Micronic Corporation. Preparation of data for these mask writers typically involves importing layout data (typically GDS II) into a stand-alone translation tool to convert the standard format to the machine specific format.
- layout data typically GDS II
- Mask writing tools include raster scanning mask writing tools, vector scan mask writing tools, tools that utilize a parallel array of mask writing elements including arrays of microscopic mirrors, independently modulated laser beams, scanning probe microscope elements or other mechanisms that create photolithographic masks or reticles.
- the component 470 therefore executes computer code that determines the form in which the data is to be exported, either by prompting a user for such a selection or based on a default etc.
- the component converts a desired portion, such as an individual data layer, of the shared data within the database into the selected mask writing language. Data may also be called and translated as subsets of the data layer, to be processed independently or in parallel, to increase translation precision or speed.
- the conversion of the database to the desired mask writing language includes the steps of reading a portion of the data layer into temporary memory, processing the portion according to the machine specific translation specifications, and writing the translated portion into an output file. This is repeated until the entire layer has been converted, portion by portion.
- another embodiment that may have advantages in some circumstances comprises moving the entire data layer to be converted into a flattened data layer, then converting the entire flattened layer into the specified machine language.
- the term “mask” is intended to cover both conventional photolithographic contact printing masks as well as reticles or other devices on which patterns are formed that determine whether illumination light is allowed to reach a wafer.
- FIG. 6 is a block diagram of one embodiment of a computer system.
- the computer system illustrated in FIG. 6 is intended to represent a range of computer systems.
- Alternative computer systems can include more, fewer and/or different components.
- Computer system 600 includes a bus 601 or other communication device to communicate information, and a processor 602 coupled to the bus 601 to process information. While the computer system 600 is illustrated with a single processor, the computer system 600 can include multiple processors and/or co-processors. In a multiprocessor embodiment, operations performed by the various verification and manufacturability tools are divided by cells, bins or other techniques for dividing work between processors. For example, a single cell is operated upon by a processor while another cell is operated upon by a different processor. When the cell operations are complete, the processor can perform verification operations on another cell.
- Computer system 600 further includes random access memory (RAM) or another dynamic storage device 604 (referred to as main memory), coupled to a bus 601 to store information and instructions to be executed by a processor 602 .
- Main memory 604 also can be used to store temporary variables or other intermediate information during execution of instructions by a processor 602 .
- Computer system 600 also includes read only memory (ROM) and/or other static storage device 606 coupled to a bus 601 to store static information and instructions for a processor 602 .
- Data storage device 607 is coupled to a bus 601 to store information and instructions.
- Data storage device 607 such as a magnetic disk or optical disc and corresponding drive can be coupled to a computer system 600 .
- Computer system 600 can also be coupled via a bus 601 to a display device 621 , such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a computer user.
- a display device 621 such as a cathode ray tube (CRT) or liquid crystal display (LCD)
- Alphanumeric input device 622 is typically coupled to a bus 601 to communicate information and command selections to a processor 602 .
- a cursor control 623 such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to a processor 602 and to control cursor movement on a display 621 .
- Computer system 600 further includes a network interface 630 to provide access to a network, such as a local area network.
- a network such as a local area network.
- an integrated verification and manufacturability tool is provided by one or more computer systems, such as a computer system 600 , or other electronic device in response to one or more processors, such as a processor 602 , executing sequences of instructions contained in memory, such as a main memory 604 .
- Instructions are provided to memory from a storage device, such as magnetic disk, a read only memory (ROM) integrated circuit, CD-ROM or DVD, via a remote connection (e.g., over a network via network interface 630 ) that is either wired or wireless, etc.
- a storage device such as magnetic disk, a read only memory (ROM) integrated circuit, CD-ROM or DVD
- a remote connection e.g., over a network via network interface 630
- a remote connection e.g., over a network via network interface 630
- hard-wired circuitry can be used in place of, or in combination with, software instructions to implement the present invention.
- the present invention is not limited to any specific combination of hardware circuitry and software instructions.
- a machine-readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer).
- a machine-readable medium includes read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).
- FIG. 7 is a flow diagram of one embodiment of design verification with an integrated verification and manufacturability tool.
- FIG. 7 illustrates a specific sequence through a specific set of verification procedures. The specific verification procedures and the sequence in which verification is performed can be modified based on, for example, the type of design being verified.
- Data describing the integrated device design is imported at 710 .
- the data is imported from a GDS-II file; however, other formats can also be used.
- conversion of data from one format to another is known in the art.
- intermediate layers are added to the imported data to be stored in a hierarchical database.
- the number of intermediate layers added is determined based on the verification procedures to be performed, and possibly on the sequence in which the verification procedures are performed. One or more intermediate layers are added for each of the verification procedures to be performed.
- a job description is analyzed in association with importation of an integrated device design. The job description indicates the verification procedures to be performed and the portions of the design that are to be verified.
- LVS verification compares the original design layout to a netlist that described the interconnections of components within the design.
- the intermediate layer(s) associated with LVS verification stores the results of the LVS verification.
- the intermediate layer(s) can store, for example, a description of errors found during LVS verification, or a modified design based on the results of the LVS verification process.
- Design rule checking is performed at 720 .
- DRC searches the design for violations of a predetermined set of conditions (e.g., minimum line widths, minimum separations) and returns a result indicating whether design rule violations were found.
- the intermediate layer(s) associated with DRC can store, for example, a list of design rule errors found, or a modified design that satisfies the design rules.
- Optical rule checking is performed at 740 . In one embodiment, the ORC is performed on one or more simulated integrated device layers.
- ORC includes “flagging” edges in a layout that are predicted to result in silicon printability errors.
- simulated silicon shapes are generated from the layout, then DRC is performed on the simulated silicon shapes. This can be thought of as “silicon DRC” or another application ORC.
- Phase shift mask assignments are made at 750 and an optical process correction is performed at 760 .
- Data may be exported at 770 in the format in which it is stored in the database.
- the integrated verification and manufacturability tool includes an integrated component that converts the shared data into a mask writing machine language, the data may be exported in a form that can be read by a mask writing tool directly.
Abstract
Description
- The present application is a continuation-in-part of U.S. patent application Ser. No. 09/593,923, filed Jun. 13, 2000, the benefit of which is claimed under 35 U.S.C. §120 and which is herein incorporated by reference.
- The invention relates to design tools for integrated device layouts. More particularly, the invention relates to an integrated tool for use in modifying and verifying integrated device layouts.
- Large scale integrated circuits or other integrated devices are designed through a complex sequence of transformations that convert an original performance specification into a specific circuit structure. Automated software tools are currently used for many of these design transformations. A common high level description of the circuit occurs in languages such as VHDL and Verilog®. One embodiment of VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, Published Jun. 6, 1994. One embodiment of Verilog® is described in greater detail in IEEE Standard 1364-1995. The description of the circuit at this stage is often called a “netlist”.
- Automated tools exist to convert this netlist into a physical layout for the circuit. FIG. 1 illustrates one approach to conversion of the netlist to a physical layout. The layout defines the specific dimensions of the gates, isolation regions, interconnects, contacts, and other device elements that form the physical devices, and usually represents these shapes with polygons defining their boundaries.
- The layout typically contains data layers that correspond to the actual layers to be fabricated in the circuit. The layout also contains cells, which define sets of particular devices within the circuit. Cells typically contain all the polygons on all the layers required for the fabrication of the devices it contains. Cells can be nested within other cells, often in very intricate arrangements. The structure of cells is often called a data hierarchy. Typical formats for the polygons of a physical layout are GDS II, or CIF.
- Once the layout is created, the layout is verified to ensure that the transformation from netlist to layout has been properly executed and that the final layout created adheres to certain geometric design rules. These layout verification operations are often called LVS (layout versus schematic) and DRC (design rule check), respectively. To perform this verification step, several products have been created, including DRACULA™ from Cadence Design Systems of San Jose, Calif., HERCULES™ from Avant! Corporation of Fremont, Calif., and CALIBRE® from Mentor Graphics of Wilsonville, Oreg. When anomalies or errors are discovered by these checking tools, the designer must then repair the fault before the layout is sent to a mask shop for mask manufacturing and wafer fabrication.
- An additional checking step can also be used for layout verification. FIG. 2 illustrates an enhanced approach to conversion of the netlist to a physical layout. This provides a simulation based software engine that predicts what manufacturing distortions will occur during lithographic patterning. If the magnitude of these errors is determined to be significant, corrections are made using some form of Optical and Process Correction (OPC). OPC can correct for image distortions, optical proximity effects, photoresist kinetic effects, etch loading distortions, and other various process effects. Phase-shifting features can also be added to the layout at this point to enhance contrast.
- Examples of this kind of checking and correction can be found in “Automated Determination of CAD Layout Failures Through Focus: Experiment and Simulation,” by C. Spence et. al, in Optical/Laser Microlithography VII, Proc. SPIE 2197, p. 302 ff. (1994), and “OPTIMASK: An OPC Algorithm for Chrome and Phase-shift Mask Design” by E. Barouch et al. in Optical/Laser Microlithography VIII, Proc. SPIE 2440, p. 192 ff. (1995). The prior art techniques mentioned above comprise operating on the layout with a series of distinct software tools that execute all the required steps in sequence.
- FIG. 3 is a conceptual illustration of an example of such a prior art process of integrated circuit (IC) design verification and correction. Each of the required process steps is executed by a stand-alone software tool.
Original IC layout 300 describes the physical circuit layers from which masks and/or reticles are created to realize the circuit described by the design layout: theoriginal IC layout 300 can be, for example, a GDS-II description of the circuit to be manufactured. -
Data import process 310 convertsoriginal IC layout 300 to a format for storage indatabase 315. The data, as stored inverification database 315, is used by layout versus schematic (LVS)tool 320 and design rule checking (DRC)tool 325 to verify the design oforiginal IC layout 300. Upon completion of LVS and DRC verification, the data stored inverification database 315 is exported bydata export process 330. - The data is then imported by a data import process335, which converts the exported data to a format used for a phase shift mask (PSM) database 340. PSM
tool 345 operates on the data stored in PSM database 340 to perform phase shifting where appropriate. Examples of stand alone PSM assignment tools are SEED, discussed in the reference by Barouch, above, and the IN-Phase™ product available from Numerical Technologies of San Jose, Calif. The data describing the phase shifted layout(s) are exported from PSM database 340 by a data export process 350. - A
data import process 355 imports the data generated by the PSM tool to an optical process correction (OPC)database 360. OPCdatabase 360 is typically a flat database, meaning that all the polygons of a layer of the circuit are contained within a single cell, with no hierarchical structure.Data import process 355 typically converts data from a hierarchical representation to a flat representation. OPC tool 365 performs OPC operations on the data stored in OPCdatabase 360. Examples of stand alone OPC tools are OPTIMASK, discussed in the reference by Barouch, above, and Taurus™ available from Avant! Corporation. Adata export process 370 exports the data stored inOPC database 360. - The data generated by the OPC tool is then typically imported into a simulation tool, to confirm that the OPC will have the desired corrective effect. This is sometimes called an optical and process rule check, or ORC. Once this check is complete, the data is exported for use in
IC manufacturing process 395. As a final verification step,LVS tool 320 and/orDRC tool 325 can also be used on the output ofOPC database 360. Performing another check withLVS tool 320 and/orDRC tool 325 requires another import and export bydata import process 310 anddata export process 330, respectively. - Several problems exist with respect to the process illustrated in FIG. 3. For example, the importation and exportation of data to and from each tool provides an opportunity for error in the form of loss, or inaccurate translation, of data. The importation and the exportation of large datasets, now common for VLSI Ics, is also time consuming, where a single import or export step can last several hours. The more complex an integrated circuit design, the more time consuming the importation and exportation steps become. It is therefore desirable to have an new verification tool in which all the required operations can be preformed, but where the risk of inaccurate translation is eliminated, and the many time consuming import and export steps are not required.
- An integrated verification and manufacturability tool having a hierarchical database to represent at least a portion of an integrated device layout in a hierarchical or flat manner, which is used not only for standard DRC and LVS verifications, but is also capable of performing optical and process correction (OPC) and other data manipulation techniques, including phase-shifting mask (PSM) assignment and silicon simulation for optical and process rule checking (ORC). In addition, an integrated software tool exports the verified data in the database in a machine language that can be read by a mask writer to produce one or more photolithographic masks.
- The invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
- FIG. 1 is representation of standard IC layout design sequence used for verification.
- FIG. 2 illustrates a modified flow, which accommodates additional process steps of OPC and PSM generation.
- FIG. 3 is a conceptual illustration of a prior art implementation of integrated circuit design verification incorporating these additional steps.
- FIG. 4 is a conceptual illustration of an integrated verification and manufacturability tool.
- FIG. 4A shows an alternative embodiment of the invention wherein the integrated verification and manufacturability tool includes a component that exports verified data in a machine language that can be read by a mask writer.
- FIG. 5 illustrates operation of one embodiment of an integrated verification and manufacturability tool.
- FIG. 6 illustrates one embodiment of a computer system suitable for use in practicing the invention.
- FIG. 7 is a flow diagram of one embodiment of design verification with an integrated verification and manufacturability tool.
- An integrated verification and manufacturability tool is described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.
- Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
- Methods and apparatuses are described herein with respect to integrated circuit manufacturing; however, the techniques described can be applied to the manufacturing and/or design process of any integrated device. Integrated devices include integrated circuits, micromachines, thin film structures such as disk drive heads, gene chips, microelectromechanical systems (MEMS), or any other article of manufacture that is manufactured using lithography techniques.
- An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability tool includes a hierarchical database to store design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Designs can include only a single layer; however, the hierarchical database can include one or more intermediate layers for a single layer original design. Use of a single hierarchical database for multiple verification steps streamlines the verification process, which provides an improved verification tool.
- FIG. 4 is a conceptual illustration of an integrated verification and manufacturability tool. The integrated verification and manufacturability tool of FIG. 4 includes a single hierarchical database that is used by each component within the tool. For purposes of description, the integrated verification and manufacturability tool includes a database and multiple components. The components perform the core functionality of the individual stand alone tools of FIG. 3; however, because they are included in an integrated verification and manufacturability tool, the individual components are not referred to as tools. Use of a single database for multiple components reduces the time and effort required for the verification process.
- FIG. 4 illustrates an LVS component, a DRC component, an optical rule checking (ORC) component, a PSM component, an OPC component, and an “other”
component 470 indicating that additional components can be added to the integrated verification and manufacturability. In alternate embodiments, fewer components can be used, for example, only a DRC and an OPC component might be used. - In one embodiment, the tool scans a listing of desired operations to be performed, sometimes called a “ruledeck,” to determine the required inputs and outputs. The tool then reads in the required input layers from the input database and creates empty output layers, to be filled during computation. In addition, several intermediate or “working” layers may be created to hold temporary computation results. In one embodiment, all inputs, outputs and intermediate results are geometry collections called “layers,” defined as a collection of geometry in one or more cells of the layout. This definition is the same as a definition of a layer in the well known GDS II database standard format for representing layouts. Layers also allow hierarchical data representation.
- Once the hierarchical database is formed and the list of required layers compiled, computations are carried out to fill the desired output layers. After the verification process is complete, the information stored in hierarchical database410 is exported by
data export process 480. The exported data can be used byIC manufacturing process 395 to manufacture the IC design. -
LVS component 440,DRC component 450,ORC component 460,PSM component 420,OPC component 430, and any other component(s), as indicated by “other” 470, operate on hierarchical data representingoriginal IC layout 300 as stored in hierarchical database 410. In one embodiment,LVS component 440,DRC component 450,ORC component 460,PSM component 420, andOPC component 430 operate on a hierarchical representation of edges that describeoriginal IC layout 300. The various components use the edge representations and the structures in the intermediate layers included in hierarchical database 410 to perform the respective operations. - Another embodiment of an integrated verification and manufacturability tool includes a component that can add arrays of regular features, such as small squares to the layout in order to help with the planarization, or physical flatness, of the fabricated silicon. These features are sometimes called “dummy fill” or “planarization fill.” By analyzing the density of the features in the layout, low-density areas are identified and filled in with new features.
- FIG. 5 illustrates operation of one embodiment of an integrated verification and manufacturability tool. As described in greater detail below, the integrated verification and manufacturability tool can be executed by one or more computer systems.
- In one embodiment, integrated verification and
manufacturability tool 500 imports data from original database 520 into modified database 510. Original database 520 can store the design to be verified in a relatively standard format, for example, GDS-II, while modified database 510 can store the design in a modified standard format, or in an independent format. In one embodiment, importation includes executing hierarchical injection and/or bin injection. In an alternate embodiment, the integrated verification andmanufacturability tool 500 receives the data in the modified/independent format. - In general, hierarchical injection is a technique in which recurring patterns of cell placements are recognized and replaced with new cells that contain the patterns. Hierarchical injection creates a more efficient representation of original database520 by reducing the number of redundant patterns of cell placements, or contexts. In one embodiment, specially designed heuristics are used to recognize the patterns and to determine the correct representation by the new cells.
- The heuristics include, for example, the injection of hierarchy into arrays and the selective flattening of densely overlapping structures. In many layouts, arrays of a cell are described inefficiently from a verification perspective. The hierarchical injection heuristics recognize arrays and redefine rows, columns or small sub-arrays as new cells.
- This added hierarchy reduces the amount of geometry promoted during the computation phase by greatly reducing the number of redundant interactions between placements in the array. In particular types of circuits, for example FPGAs, two large cells or arrays of cells will overlap each other to a large extent. This configuration is called a “dense overlap.” Hierarchical injection recognizes such instances and first flattens selected cells that overlap, and then re-introduces new, less interaction-prone cell structures.
- Bin injection is a process of dividing flat layout geometry into cells. Bin injection can also be applied to a random collection of cells, to reconfigure the cell structure more efficiently. In one embodiment, bin injection is accomplished by dividing a layout not by cell names, but by geometric grid. Bin injection is one technique for converting a flat layout into a hierarchical layout.
- Various importation techniques are described in greater detail in U.S. patent application Ser. No. 09/234,030 filed Jan. 19, 1999 entitled “PLACEMENT BASED DESIGN CELLS INJECTION INTO AN INTEGRATED CIRCUIT DESIGN,” by Laurence W. Grodd, which is incorporated by reference herein.
- Once modified database510 is generated by hierarchical injection and/or bin injection, each component (e.g., LVS, DRC, PSM, OPC, ORC) operates on groups of geometric figures that represent portions of the layout of the integrated device design. These groups are generally referred to as an “edge collection.” An edge collection contains edges from a design that may be organized into polygons, depending on the nature of the operations. Typical edge collections may contain only the edges of a single cell, others may contain the edges of a cell and nearby elements, while others might contain all edges within an arbitrary boundary. Edges may be retrieved from the edge collection either as whole polygons, if the data they represent consists of polygons, or as free edges. Once retrieved and manipulated, new edges representing the output of the operation are stored in a layer from which the edges are retrieved and/or a previously unused intermediate layer in modified database 510.
- Selective promotion is a technique in which certain geometries in cells that have an effect on nearby cells are “promoted” to another level of the hierarchy. This promotion prevents the geometry in a cell from having conflicting behavior depending on the placement of the cell. For example, for a cell that has geometry very close to its own border, one placement of this cell may be isolated, but another placement may be close to another cell. In this case, the computed result for the geometry near the border may be different in each placement due to interaction with the nearby cell.
- To resolve this conflict, the conflicting geometry close to the border is “promoted,” or flattened, to the next level of the hierarchy. This creates two versions of the geometry, one for each placement of the cell, each of which will produce different computational results. By reducing the number of unique interactions and conflicting geometries, the amount of promoted geometry is minimized, resulting in less computation and smaller file size. Promotion can be accomplished recursively.
- Manipulation of edge collections, as well as the use of selective promotion facilitates sharing of data between multiple verification tool components without importation and exportation of data between databases. Previous verification tools typically represent IC designs in formats that are optimized for the specific tool without regard for sharing the design database. Sharing of data was accomplished through an importation/exportation process.
- The hierarchical representation provided by modified database510 provides several performance advantages. For example, previous verification tools typically used a cell cloning scheme to eliminate redundant contexts. However, some designs resulted in a very large number of clones which slowed the verification process. Selective promotion and hierarchical injection reduces, or even eliminates, redundant contexts in a more efficient manner, which allows the verification process to be completed more quickly than using a cloning-based technique.
- Additionally, cloning techniques are based on the assumption that all inter-cell interactions are local. That is, interaction distances are bounded. However, for phase-shift mask (or reticle) assignment techniques, interaction distances are potentially unbounded. This requires a potentially unbounded number of cell clones, which would make hierarchical phase assignment impractical.
- In one embodiment, the integrated verification and manufacturability tool includes an
LVS component 440 and aDRC component 450 that perform both LVS verification operations and DRC verification operations on the edge collection stored in modified database 510. In an alternate embodiment, LVS verification operations and DRC verification operations are performed by separate components. - The LVS verification operations analyze the edge collection to determine whether the layout accurately corresponds to the schematic design. In one embodiment, the edge collection is compared to a netlist corresponding to the design to determine whether the layout accurately represents the netlist representation. Errors identified by the LVS component can be flagged, identified and possibly corrected. In one embodiment, data generated by the LVS component and/or the corrected layout are stored in one or more intermediate layers in modified database510.
- The DRC verification operations analyze the edge collection to determine whether any design rule violations exist. Design rules can include, for example, minimum line spacings, minimum line widths, minimum gate widths, or other geometric layout parameters. The design rules are based on, for example, the manufacturing process to be used to manufacture the resulting design layout. As with the LVS component, errors identified by the DRC component can be flagged, identified and possibly corrected. In one embodiment, data generated by the DRC component and/or the corrected layout are stored in one or more intermediate layers in modified database510.
- In one embodiment,
ORC component 460 analyzes the edge collection by simulating the performance expected on the wafer, and determining whether the wafer structures will violate a set of fabrication tolerances.ORC component 460 can also operate on the edge collection that represents the original layout, for example, prior to LVS and DRC being performed on the layout. As with the LVS and DRC components, errors identified by the ORC component can be flagged and identified and possibly corrected. - In one embodiment,
PSM component 420 operates on an edge collection as modified byORC component 460; howeverPSM component 420 can operate on other edge collections also.PSM component 420 creates phase shifting assignments for reticles of the design stored in modified database 510. Phase shifting assignments can be made, for example, to enable extremely small gate widths and/or line widths. The resulting layers and/or reticle layers are stored in intermediate layers in modified database 510. - In one embodiment,
OPC component 430 operates on the edge collection as modified byPSM component 420 and stored in one or more intermediate layers in modified database 510.OPC component 430 can also operate on the edge collection that represents the original layout, for example, if PSM is not performed on the layout. - Two general categories of OPC are currently in use: rule-based OPC and model based OPC; one or both of which can be applied. In rule-based OPC, a reticle layout is modified according to a set of fixed rules for geometric manipulation. In model-based OPC, an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated result generated based on the model used.
- Certain aspects of model-based OPC are described in greater detail in the following publications: Cobb et al., “Mathematical and CAD Framework for Proximity Correction,”Optical Microlithography IX, Proc. SPIE 2726, pp. 208-222 (1996); Cobb et al., “Experimental Results in Optical Proximity Correction with Variable Threshold Resist Model,” Optical Microlithography X, SPIE 3051, pp. 458-468 (1998); and Nicholas B. Cobb, “Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing,” Ph.D. dissertation, Univ. Cal. Berkeley (1998).
-
OPC component 460 modifies the placement of one or more edges to provide improved optical performance of one or more reticles. One example of rule-based OPC that can be applied to a layout is the addition of assist features, for example, sub-resolution bars along an interconnection line, hammer head shapes at line ends, or serifs at a line corner. Other assist features can also be provided. -
OPC component 460 can also modify placement of one or more edges based on models that predict the structures that will be produced using specific reticle layouts. The reticle layouts can be modified based on the results of the prediction to compensate for deficiencies that are identified by the modeling results. In one embodiment, the results Generated byOPC component 460 are stored in one or more intermediate layers in modified database 510. - In yet another embodiment of the invention, the
other component 470 of the integrated verification and manufacturability tool shown in FIG. 4A converts the optimized, shared data within the database into a format that can be supplied directly to a mask creating tool. Most mask creating tools use layout data in machine specific formats, such as MEBES for E-Beam and laser rasterizing writing tools, such as those from ETEC systems (an applied Materials Company), Hitachi format for Hitachi vector scan E-beam mask writers, .MIC format for hierarchical processing in mask writers from Micronic Corporation. Preparation of data for these mask writers typically involves importing layout data (typically GDS II) into a stand-alone translation tool to convert the standard format to the machine specific format. - Mask writing tools include raster scanning mask writing tools, vector scan mask writing tools, tools that utilize a parallel array of mask writing elements including arrays of microscopic mirrors, independently modulated laser beams, scanning probe microscope elements or other mechanisms that create photolithographic masks or reticles.
- The
component 470 therefore executes computer code that determines the form in which the data is to be exported, either by prompting a user for such a selection or based on a default etc. Next, the component converts a desired portion, such as an individual data layer, of the shared data within the database into the selected mask writing language. Data may also be called and translated as subsets of the data layer, to be processed independently or in parallel, to increase translation precision or speed. - In the presently preferred embodiment of the invention in which the database is hierarchical, the conversion of the database to the desired mask writing language includes the steps of reading a portion of the data layer into temporary memory, processing the portion according to the machine specific translation specifications, and writing the translated portion into an output file. This is repeated until the entire layer has been converted, portion by portion. Although it will be appreciated that the job can be more manageable when divided by portions or other subsets of the data layer, another embodiment that may have advantages in some circumstances comprises moving the entire data layer to be converted into a flattened data layer, then converting the entire flattened layer into the specified machine language.
- As will be appreciated, by including a
component 470 that can export the verified and optimized design data directly in the mask writing machine language, there is less chance of error due to compatibility problems between software systems. In addition, the time required to process the layout data and produce a mask is also reduced. - For the purpose of the present specification and claims, the term “mask” is intended to cover both conventional photolithographic contact printing masks as well as reticles or other devices on which patterns are formed that determine whether illumination light is allowed to reach a wafer.
- FIG. 6 is a block diagram of one embodiment of a computer system. The computer system illustrated in FIG. 6 is intended to represent a range of computer systems. Alternative computer systems can include more, fewer and/or different components.
- Computer system600 includes a
bus 601 or other communication device to communicate information, and aprocessor 602 coupled to thebus 601 to process information. While the computer system 600 is illustrated with a single processor, the computer system 600 can include multiple processors and/or co-processors. In a multiprocessor embodiment, operations performed by the various verification and manufacturability tools are divided by cells, bins or other techniques for dividing work between processors. For example, a single cell is operated upon by a processor while another cell is operated upon by a different processor. When the cell operations are complete, the processor can perform verification operations on another cell. - Computer system600 further includes random access memory (RAM) or another dynamic storage device 604 (referred to as main memory), coupled to a
bus 601 to store information and instructions to be executed by aprocessor 602.Main memory 604 also can be used to store temporary variables or other intermediate information during execution of instructions by aprocessor 602. - Computer system600 also includes read only memory (ROM) and/or other static storage device 606 coupled to a
bus 601 to store static information and instructions for aprocessor 602. Data storage device 607 is coupled to abus 601 to store information and instructions. Data storage device 607 such as a magnetic disk or optical disc and corresponding drive can be coupled to a computer system 600. - Computer system600 can also be coupled via a
bus 601 to adisplay device 621, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a computer user.Alphanumeric input device 622, including alphanumeric and other keys, is typically coupled to abus 601 to communicate information and command selections to aprocessor 602. Another type of user input device is acursor control 623, such as a mouse, a trackball, or cursor direction keys to communicate direction information and command selections to aprocessor 602 and to control cursor movement on adisplay 621. - Computer system600 further includes a network interface 630 to provide access to a network, such as a local area network. According to one embodiment, an integrated verification and manufacturability tool is provided by one or more computer systems, such as a computer system 600, or other electronic device in response to one or more processors, such as a
processor 602, executing sequences of instructions contained in memory, such as amain memory 604. - Instructions are provided to memory from a storage device, such as magnetic disk, a read only memory (ROM) integrated circuit, CD-ROM or DVD, via a remote connection (e.g., over a network via network interface630) that is either wired or wireless, etc. In alternative embodiments, hard-wired circuitry can be used in place of, or in combination with, software instructions to implement the present invention. Thus, the present invention is not limited to any specific combination of hardware circuitry and software instructions.
- A machine-readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).
- FIG. 7 is a flow diagram of one embodiment of design verification with an integrated verification and manufacturability tool. FIG. 7 illustrates a specific sequence through a specific set of verification procedures. The specific verification procedures and the sequence in which verification is performed can be modified based on, for example, the type of design being verified.
- Data describing the integrated device design is imported at710. In one embodiment, the data is imported from a GDS-II file; however, other formats can also be used. In general, conversion of data from one format to another is known in the art. As mentioned above, during importation, intermediate layers are added to the imported data to be stored in a hierarchical database.
- In one embodiment, the number of intermediate layers added is determined based on the verification procedures to be performed, and possibly on the sequence in which the verification procedures are performed. One or more intermediate layers are added for each of the verification procedures to be performed. In one embodiment, a job description is analyzed in association with importation of an integrated device design. The job description indicates the verification procedures to be performed and the portions of the design that are to be verified.
- Layout versus schematic (LVS) verification is performed at720. In general, LVS verification compares the original design layout to a netlist that described the interconnections of components within the design. The intermediate layer(s) associated with LVS verification stores the results of the LVS verification. The intermediate layer(s) can store, for example, a description of errors found during LVS verification, or a modified design based on the results of the LVS verification process.
- Design rule checking (DRC) is performed at720. DRC searches the design for violations of a predetermined set of conditions (e.g., minimum line widths, minimum separations) and returns a result indicating whether design rule violations were found. The intermediate layer(s) associated with DRC can store, for example, a list of design rule errors found, or a modified design that satisfies the design rules. Optical rule checking (ORC) is performed at 740. In one embodiment, the ORC is performed on one or more simulated integrated device layers.
- In one embodiment, ORC includes “flagging” edges in a layout that are predicted to result in silicon printability errors. In another embodiment, simulated silicon shapes are generated from the layout, then DRC is performed on the simulated silicon shapes. This can be thought of as “silicon DRC” or another application ORC.
- Phase shift mask assignments are made at750 and an optical process correction is performed at 760. Data may be exported at 770 in the format in which it is stored in the database. Alternatively, if the integrated verification and manufacturability tool includes an integrated component that converts the shared data into a mask writing machine language, the data may be exported in a form that can be read by a mask writing tool directly.
- In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
- While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.
Claims (48)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/747,190 US6415421B2 (en) | 2000-06-13 | 2000-12-22 | Integrated verification and manufacturability tool |
PCT/US2001/017210 WO2001097096A1 (en) | 2000-06-13 | 2001-05-25 | Integrated verification and manufacturability tool |
EP01984021.4A EP1330742B1 (en) | 2000-06-13 | 2001-05-25 | Integrated verification and manufacturability tool |
JP2002511227A JP2004503879A (en) | 2000-06-13 | 2001-05-25 | Integrated verification and manufacturing adaptation tools |
US10/112,223 US7017141B2 (en) | 2000-06-13 | 2002-03-27 | Integrated verification and manufacturability tool |
US11/209,252 US7412676B2 (en) | 2000-06-13 | 2005-08-22 | Integrated OPC verification tool |
JP2006004195A JP2006134356A (en) | 2000-06-13 | 2006-01-11 | Integrated verification and manufacturability tool |
JP2006161662A JP4822330B2 (en) | 2000-06-13 | 2006-06-09 | Integrated verification and manufacturing adaptation tools |
US12/145,433 US7945871B2 (en) | 2000-06-13 | 2008-06-24 | Integrated OPC verification tool |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/593,923 US6425113B1 (en) | 2000-06-13 | 2000-06-13 | Integrated verification and manufacturability tool |
US09/747,190 US6415421B2 (en) | 2000-06-13 | 2000-12-22 | Integrated verification and manufacturability tool |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/593,923 Continuation-In-Part US6425113B1 (en) | 2000-06-13 | 2000-06-13 | Integrated verification and manufacturability tool |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/112,223 Division US7017141B2 (en) | 2000-06-13 | 2002-03-27 | Integrated verification and manufacturability tool |
Publications (2)
Publication Number | Publication Date |
---|---|
US20010052107A1 true US20010052107A1 (en) | 2001-12-13 |
US6415421B2 US6415421B2 (en) | 2002-07-02 |
Family
ID=24376772
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/593,923 Expired - Lifetime US6425113B1 (en) | 2000-06-13 | 2000-06-13 | Integrated verification and manufacturability tool |
US09/747,190 Expired - Lifetime US6415421B2 (en) | 2000-06-13 | 2000-12-22 | Integrated verification and manufacturability tool |
US12/145,433 Expired - Lifetime US7945871B2 (en) | 2000-06-13 | 2008-06-24 | Integrated OPC verification tool |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/593,923 Expired - Lifetime US6425113B1 (en) | 2000-06-13 | 2000-06-13 | Integrated verification and manufacturability tool |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/145,433 Expired - Lifetime US7945871B2 (en) | 2000-06-13 | 2008-06-24 | Integrated OPC verification tool |
Country Status (2)
Country | Link |
---|---|
US (3) | US6425113B1 (en) |
WO (1) | WO2001097048A1 (en) |
Cited By (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030229412A1 (en) * | 2002-06-07 | 2003-12-11 | David White | Electronic design for integrated circuits based on process related variations |
US20030229479A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US20030228714A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US20030226757A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US20030229875A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
US20040015796A1 (en) * | 2002-07-19 | 2004-01-22 | Frank Mark D. | Verifying proximity of ground vias to signal vias in an integrated circuit |
US20040015795A1 (en) * | 2002-07-19 | 2004-01-22 | Frank Mark D. | Verifying proximity of ground metal to signal traces in an integrated circuit |
EP1391844A2 (en) * | 2002-08-21 | 2004-02-25 | Lsi Logic Corporation | Automatic recognition of an optically periodic structure in an integrated circuit design |
US6709793B1 (en) | 2002-10-31 | 2004-03-23 | Motorola, Inc. | Method of manufacturing reticles using subresolution test patterns |
US6711730B2 (en) | 2002-05-13 | 2004-03-23 | Hewlett-Packard Development Company, L.P. | Synthesizing signal net information from multiple integrated circuit package models |
US20040181458A1 (en) * | 2003-03-14 | 2004-09-16 | Danchai Kochpatcharin | System, apparatus and method for reticle grade and pricing management |
US20040181769A1 (en) * | 2003-03-14 | 2004-09-16 | Danchai Kochpatcharin | System, apparatus and method for automated tapeout support |
US6807657B2 (en) | 2002-07-19 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Inter-signal proximity verification in an integrated circuit |
US20050132306A1 (en) * | 2002-06-07 | 2005-06-16 | Praesagus, Inc., A Massachusetts Corporation | Characterization and reduction of variation for integrated circuits |
US6996797B1 (en) | 2004-11-18 | 2006-02-07 | International Business Machines Corporation | Method for verification of resolution enhancement techniques and optical proximity correction in lithography |
US20060123364A1 (en) * | 2004-12-07 | 2006-06-08 | International Business Machines Corporation | Method, system and program product for evaluating a circuit |
US20060217916A1 (en) * | 2005-03-24 | 2006-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for integrally checking chip and package substrate layouts for errors |
US20060246362A1 (en) * | 2005-05-02 | 2006-11-02 | Elpida Memory, Inc. | Mask data creation method |
US20070079269A1 (en) * | 2005-10-05 | 2007-04-05 | Corbeil John D Jr | Method for performing design rule check of integrated circuit |
US20070157139A1 (en) * | 2002-06-07 | 2007-07-05 | David White | Characterization and verification for integrated circuit designs |
US20070256039A1 (en) * | 2002-06-07 | 2007-11-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US20080027698A1 (en) * | 2002-06-07 | 2008-01-31 | Cadence Design Systems, Inc. | Method and System for Handling Process Related Variations for Integrated Circuits Based Upon Reflections |
WO2008045900A1 (en) * | 2006-10-09 | 2008-04-17 | Mentor Graphics Corporation | Properties in electronic design automation |
US20090125867A1 (en) * | 2000-07-05 | 2009-05-14 | Synopsys, Inc. | Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters |
US20110320990A1 (en) * | 2010-05-25 | 2011-12-29 | Srinivasan Sridhar G | Logic-driven layout verification |
CN103839782A (en) * | 2012-11-27 | 2014-06-04 | 瑞萨电子株式会社 | Mask and method for manufacturing the same, and semicondutor device |
US20140337810A1 (en) * | 2009-05-14 | 2014-11-13 | Mentor Graphics Corporation | Modular platform for integrated circuit design analysis and verification |
US9323882B2 (en) | 2014-03-28 | 2016-04-26 | Globalfoundries Inc. | Metrology pattern layout and method of use thereof |
CN113010421A (en) * | 2021-03-16 | 2021-06-22 | 北京奇艺世纪科技有限公司 | Data processing method and device, electronic equipment and storage medium |
US20220058836A1 (en) * | 2019-02-25 | 2022-02-24 | Center For Deep Learning In Electronics Manufacturing, Inc. | Methods and systems for compressing shape data for electronic designs |
Families Citing this family (153)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6449757B1 (en) * | 1998-02-26 | 2002-09-10 | Micron Technology, Inc. | Hierarchical semiconductor design |
US6922659B2 (en) * | 1998-02-26 | 2005-07-26 | Micron Technology, Inc. | Parameter population of cells of a hierarchical semiconductor structure via file relation |
US6760323B1 (en) * | 1999-02-04 | 2004-07-06 | Concerto Software, Inc. | System and method for providing audio communication over a computer network using differing communication formats |
US6611946B1 (en) * | 1999-10-14 | 2003-08-26 | Synopsys, Inc. | Method and system for automatic generation of DRC rules with just in time definition of derived layers |
US6487696B1 (en) * | 2000-03-03 | 2002-11-26 | Voyan Technology | Compensator design optimization through efficient utilization of subcompensators |
US7412676B2 (en) * | 2000-06-13 | 2008-08-12 | Nicolas B Cobb | Integrated OPC verification tool |
US6425113B1 (en) * | 2000-06-13 | 2002-07-23 | Leigh C. Anderson | Integrated verification and manufacturability tool |
US6523162B1 (en) * | 2000-08-02 | 2003-02-18 | Numerical Technologies, Inc. | General purpose shape-based layout processing scheme for IC layout modifications |
JP4480255B2 (en) * | 2000-11-09 | 2010-06-16 | 株式会社ルネサステクノロジ | Parasitic element extraction apparatus and parasitic element extraction method for semiconductor circuit |
US6857116B1 (en) * | 2000-11-15 | 2005-02-15 | Reshape, Inc. | Optimization of abutted-pin hierarchical physical design |
US7392168B2 (en) * | 2001-03-13 | 2008-06-24 | Yuri Granik | Method of compensating for etch effects in photolithographic processing |
US6574779B2 (en) * | 2001-04-12 | 2003-06-03 | International Business Machines Corporation | Hierarchical layout method for integrated circuits |
TW569295B (en) * | 2001-09-29 | 2004-01-01 | Toshiba Corp | Producing method for mask pattern and manufacturing method for semiconductor device |
US7085698B2 (en) * | 2001-12-18 | 2006-08-01 | Synopsys, Inc. | Method for providing flexible and dynamic reporting capability using simulation tools |
US6725435B2 (en) | 2002-01-25 | 2004-04-20 | Logicvision, Inc. | Method and program product for completing a circuit design having embedded test structures |
US7103860B2 (en) * | 2002-01-25 | 2006-09-05 | Logicvision, Inc. | Verification of embedded test structures in circuit designs |
US6993733B2 (en) * | 2002-04-09 | 2006-01-31 | Atrenta, Inc. | Apparatus and method for handling of multi-level circuit design data |
US6904575B2 (en) * | 2002-06-11 | 2005-06-07 | International Business Machines Corporation | Method for improving chip yields in the presence of via flaring |
US6931613B2 (en) * | 2002-06-24 | 2005-08-16 | Thomas H. Kauth | Hierarchical feature extraction for electrical interaction calculations |
US6769103B2 (en) | 2002-07-19 | 2004-07-27 | Micron Technology, Inc. | Line width check in layout database |
US6792592B2 (en) * | 2002-08-30 | 2004-09-14 | Numerical Technologies, Inc. | Considering mask writer properties during the optical proximity correction process |
US20040083475A1 (en) * | 2002-10-25 | 2004-04-29 | Mentor Graphics Corp. | Distribution of operations to remote computers |
US7289658B2 (en) * | 2003-06-24 | 2007-10-30 | International Business Machines Corporation | Removal of relatively unimportant shapes from a set of shapes |
US7135344B2 (en) * | 2003-07-11 | 2006-11-14 | Applied Materials, Israel, Ltd. | Design-based monitoring |
US7100134B2 (en) * | 2003-08-18 | 2006-08-29 | Aprio Technologies, Inc. | Method and platform for integrated physical verifications and manufacturing enhancements |
US6978438B1 (en) | 2003-10-01 | 2005-12-20 | Advanced Micro Devices, Inc. | Optical proximity correction (OPC) technique using generalized figure of merit for photolithograhic processing |
US7366342B2 (en) * | 2003-10-27 | 2008-04-29 | International Business Machines Corporation | Simultaneous computation of multiple points on one or multiple cut lines |
US7010776B2 (en) * | 2003-10-27 | 2006-03-07 | International Business Machines Corporation | Extending the range of lithographic simulation integrals |
US7343271B2 (en) * | 2003-10-27 | 2008-03-11 | International Business Machines Corporation | Incorporation of a phase map into fast model-based optical proximity correction simulation kernels to account for near and mid-range flare |
US7055126B2 (en) * | 2003-10-27 | 2006-05-30 | International Business Machines Corporation | Renesting interaction map into design for efficient long range calculations |
US7287239B2 (en) * | 2003-10-27 | 2007-10-23 | International Business Machines Corporation | Performance in model-based OPC engine utilizing efficient polygon pinning method |
US7069534B2 (en) * | 2003-12-17 | 2006-06-27 | Sahouria Emile Y | Mask creation with hierarchy management using cover cells |
JP2005181523A (en) | 2003-12-17 | 2005-07-07 | Toshiba Corp | Design pattern correcting method, mask pattern forming method, method for manufacturing semiconductor device, design pattern correction system, and design pattern correcting program |
JP4357287B2 (en) | 2003-12-18 | 2009-11-04 | 株式会社東芝 | Correction guide generation method, pattern creation method, mask manufacturing method, semiconductor device manufacturing method, and program |
US7315990B2 (en) * | 2004-01-12 | 2008-01-01 | International Business Machines Corporation | Method and system for creating, viewing, editing, and sharing output from a design checking system |
JP4758358B2 (en) | 2004-01-29 | 2011-08-24 | ケーエルエー−テンカー コーポレイション | Computer-implemented method for detecting defects in reticle design data |
US9188974B1 (en) | 2004-02-13 | 2015-11-17 | Kla-Tencor Technologies Corp. | Methods for improved monitor and control of lithography processes |
US7861207B2 (en) * | 2004-02-25 | 2010-12-28 | Mentor Graphics Corporation | Fragmentation point and simulation site adjustment for resolution enhancement techniques |
FR2866963A1 (en) * | 2004-02-27 | 2005-09-02 | Bull Sa | Dummy surface inserting method for e.g. very large scale integrated circuit, involves processing circuit design by insertion of surface patterns based on insertion hierarchy estimating design hierarchy by processing blocks and units |
US7313769B1 (en) * | 2004-03-01 | 2007-12-25 | Advanced Micro Devices, Inc. | Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin |
US7543256B1 (en) | 2004-03-01 | 2009-06-02 | Advanced Micro Devices, Inc. | System and method for designing an integrated circuit device |
US7269804B2 (en) * | 2004-04-02 | 2007-09-11 | Advanced Micro Devices, Inc. | System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques |
US7194725B1 (en) | 2004-04-02 | 2007-03-20 | Advanced Micro Devices, Inc. | System and method for design rule creation and selection |
US7080349B1 (en) | 2004-04-05 | 2006-07-18 | Advanced Micro Devices, Inc. | Method of developing optimized optical proximity correction (OPC) fragmentation script for photolithographic processing |
US7065738B1 (en) | 2004-05-04 | 2006-06-20 | Advanced Micro Devices, Inc. | Method of verifying an optical proximity correction (OPC) model |
EP1747520B1 (en) * | 2004-05-07 | 2018-10-24 | Mentor Graphics Corporation | Integrated circuit layout design methodology with process variation bands |
US7207017B1 (en) | 2004-06-10 | 2007-04-17 | Advanced Micro Devices, Inc. | Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results |
JP2006024004A (en) * | 2004-07-08 | 2006-01-26 | Matsushita Electric Ind Co Ltd | Operation verification system and method for semiconductor integrated circuit |
JP4904034B2 (en) * | 2004-09-14 | 2012-03-28 | ケーエルエー−テンカー コーポレイション | Method, system and carrier medium for evaluating reticle layout data |
US7337421B2 (en) * | 2004-09-30 | 2008-02-26 | Cadence Design Systems, Inc. | Method and system for managing design corrections for optical and process effects based on feature tolerances |
US7284214B2 (en) * | 2004-10-22 | 2007-10-16 | Mentor Graphics Corporation | In-line XOR checking of master cells during integrated circuit design rule checking |
US7401319B2 (en) * | 2004-12-23 | 2008-07-15 | Invarium, Inc. | Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design |
US20060253813A1 (en) * | 2005-05-03 | 2006-11-09 | Dan Rittman | Design rule violations check (DRC) of IC's (integrated circuits) mask layout database, via the internet method and computer software |
JP4686257B2 (en) * | 2005-05-25 | 2011-05-25 | 株式会社東芝 | Mask manufacturing system, mask data creation method, and semiconductor device manufacturing method |
US7269808B2 (en) * | 2005-05-26 | 2007-09-11 | International Business Machines Corporation | Design verification |
US7769225B2 (en) * | 2005-08-02 | 2010-08-03 | Kla-Tencor Technologies Corp. | Methods and systems for detecting defects in a reticle design pattern |
JP2007080965A (en) * | 2005-09-12 | 2007-03-29 | Matsushita Electric Ind Co Ltd | Manufacturing method of semiconductor device, library used for manufacture thereof, recording medium, and semiconductor manufacturing apparatus |
KR100673014B1 (en) | 2005-10-28 | 2007-01-24 | 삼성전자주식회사 | Method of fabricating photomask |
US7934184B2 (en) * | 2005-11-14 | 2011-04-26 | Takumi Technology Corporation | Integrated circuit design using modified cells |
US8041103B2 (en) | 2005-11-18 | 2011-10-18 | Kla-Tencor Technologies Corp. | Methods and systems for determining a position of inspection data in design data space |
US7570796B2 (en) | 2005-11-18 | 2009-08-04 | Kla-Tencor Technologies Corp. | Methods and systems for utilizing design data in combination with inspection data |
US7676077B2 (en) | 2005-11-18 | 2010-03-09 | Kla-Tencor Technologies Corp. | Methods and systems for utilizing design data in combination with inspection data |
US7712068B2 (en) * | 2006-02-17 | 2010-05-04 | Zhuoxiang Ren | Computation of electrical properties of an IC layout |
US8225261B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining contact grid in dynamic array architecture |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US7943967B2 (en) | 2006-03-09 | 2011-05-17 | Tela Innovations, Inc. | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US7932545B2 (en) | 2006-03-09 | 2011-04-26 | Tela Innovations, Inc. | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
JP2008009964A (en) * | 2006-05-31 | 2008-01-17 | Toshiba Corp | Layout making equipment and method of making layout of semiconductor integrated circuit |
US7448018B2 (en) * | 2006-09-12 | 2008-11-04 | International Business Machines Corporation | System and method for employing patterning process statistics for ground rules waivers and optimization |
US7434185B2 (en) * | 2006-09-27 | 2008-10-07 | International Business Machines Corporation | Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data |
US7823103B2 (en) * | 2006-10-24 | 2010-10-26 | International Business Machines Corporation | Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data |
US8056022B2 (en) | 2006-11-09 | 2011-11-08 | Mentor Graphics Corporation | Analysis optimizer |
US7966585B2 (en) * | 2006-12-13 | 2011-06-21 | Mentor Graphics Corporation | Selective shielding for multiple exposure masks |
US7877722B2 (en) * | 2006-12-19 | 2011-01-25 | Kla-Tencor Corp. | Systems and methods for creating inspection recipes |
US7698666B2 (en) * | 2006-12-29 | 2010-04-13 | Cadence Design Systems, Inc. | Method and system for model-based design and layout of an integrated circuit |
US7861203B2 (en) * | 2006-12-29 | 2010-12-28 | Cadence Design Systems, Inc. | Method and system for model-based routing of an integrated circuit |
US8194968B2 (en) | 2007-01-05 | 2012-06-05 | Kla-Tencor Corp. | Methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions |
US7802226B2 (en) * | 2007-01-08 | 2010-09-21 | Mentor Graphics Corporation | Data preparation for multiple mask printing |
US7799487B2 (en) * | 2007-02-09 | 2010-09-21 | Ayman Yehia Hamouda | Dual metric OPC |
US7739650B2 (en) * | 2007-02-09 | 2010-06-15 | Juan Andres Torres Robles | Pre-bias optical proximity correction |
US7979829B2 (en) | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
CN105426567B (en) * | 2007-03-09 | 2018-12-07 | 明导公司 | Incremental analysis of layout design data |
TWI417894B (en) * | 2007-03-21 | 2013-12-01 | Ibm | Structure and method of implementing power savings during addressing of dram architectures |
US7791978B2 (en) * | 2008-02-01 | 2010-09-07 | International Business Machines Corporation | Design structure of implementing power savings during addressing of DRAM architectures |
US7962863B2 (en) | 2007-05-07 | 2011-06-14 | Kla-Tencor Corp. | Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer |
US7738093B2 (en) | 2007-05-07 | 2010-06-15 | Kla-Tencor Corp. | Methods for detecting and classifying defects on a reticle |
US8213704B2 (en) | 2007-05-09 | 2012-07-03 | Kla-Tencor Corp. | Methods and systems for detecting defects in a reticle design pattern |
US8713483B2 (en) | 2007-06-05 | 2014-04-29 | Mentor Graphics Corporation | IC layout parsing for multiple masks |
US7796804B2 (en) | 2007-07-20 | 2010-09-14 | Kla-Tencor Corp. | Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer |
US7711514B2 (en) | 2007-08-10 | 2010-05-04 | Kla-Tencor Technologies Corp. | Computer-implemented methods, carrier media, and systems for generating a metrology sampling plan |
JP5425779B2 (en) | 2007-08-20 | 2014-02-26 | ケーエルエー−テンカー・コーポレーション | A computer-implemented method for determining whether an actual defect is a potential systematic defect or a potentially random defect |
US7765021B2 (en) * | 2008-01-16 | 2010-07-27 | International Business Machines Corporation | Method to check model accuracy during wafer patterning simulation |
JP5252932B2 (en) * | 2008-01-18 | 2013-07-31 | 株式会社東芝 | Manufacturing method of semiconductor device |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
JP5309623B2 (en) * | 2008-03-10 | 2013-10-09 | 富士通セミコンダクター株式会社 | Photomask data processing method, photomask data processing system, and manufacturing method using hierarchical structure |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
US8139844B2 (en) | 2008-04-14 | 2012-03-20 | Kla-Tencor Corp. | Methods and systems for determining a defect criticality index for defects on wafers |
US8060843B2 (en) * | 2008-06-18 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verification of 3D integrated circuits |
KR101749351B1 (en) | 2008-07-16 | 2017-06-20 | 텔라 이노베이션스, 인코포레이티드 | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
KR101623747B1 (en) | 2008-07-28 | 2016-05-26 | 케이엘에이-텐코어 코오포레이션 | Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US20100218159A1 (en) * | 2008-11-19 | 2010-08-26 | Emile Sahouria | Data Flow Branching in Mask Data Preparation |
US8775101B2 (en) | 2009-02-13 | 2014-07-08 | Kla-Tencor Corp. | Detecting defects on a wafer |
US8204297B1 (en) | 2009-02-27 | 2012-06-19 | Kla-Tencor Corp. | Methods and systems for classifying defects detected on a reticle |
JP2010211046A (en) * | 2009-03-11 | 2010-09-24 | Toshiba Corp | Method and program for verifying pattern |
US8112241B2 (en) | 2009-03-13 | 2012-02-07 | Kla-Tencor Corp. | Methods and systems for generating an inspection process for a wafer |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US8539416B1 (en) | 2009-12-30 | 2013-09-17 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design |
US8510685B1 (en) * | 2009-12-30 | 2013-08-13 | Cadence Design Systems, Inc. | Methods, systems, and articles of manufacture for creating a hierarchical output for an operation in an electronic design |
US8156456B1 (en) * | 2010-07-01 | 2012-04-10 | Xilinx, Inc. | Unified design methodology for multi-die integrated circuits |
US8781781B2 (en) | 2010-07-30 | 2014-07-15 | Kla-Tencor Corp. | Dynamic care areas |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8619236B2 (en) | 2010-11-24 | 2013-12-31 | International Business Machines Corporation | Determining lithographic set point using optical proximity correction verification simulation |
US8499260B2 (en) | 2011-01-26 | 2013-07-30 | International Business Machines Corporation | Optical proximity correction verification accounting for mask deviations |
US8577489B2 (en) | 2011-01-26 | 2013-11-05 | International Business Machines Corporation | Diagnosing in-line critical dimension control adjustments using optical proximity correction verification |
US9170211B2 (en) | 2011-03-25 | 2015-10-27 | Kla-Tencor Corp. | Design-based inspection using repeating structures |
US8453075B2 (en) | 2011-09-02 | 2013-05-28 | International Business Machines Corporation | Automated lithographic hot spot detection employing unsupervised topological image categorization |
US9087367B2 (en) | 2011-09-13 | 2015-07-21 | Kla-Tencor Corp. | Determining design coordinates for wafer defects |
CN103186034A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
US8831334B2 (en) | 2012-01-20 | 2014-09-09 | Kla-Tencor Corp. | Segmentation for wafer inspection |
US8826200B2 (en) | 2012-05-25 | 2014-09-02 | Kla-Tencor Corp. | Alteration for wafer inspection |
US8745553B2 (en) * | 2012-08-23 | 2014-06-03 | Globalfoundries Inc. | Method and apparatus for applying post graphic data system stream enhancements |
US9189844B2 (en) | 2012-10-15 | 2015-11-17 | Kla-Tencor Corp. | Detecting defects on a wafer using defect-specific information |
US9053527B2 (en) | 2013-01-02 | 2015-06-09 | Kla-Tencor Corp. | Detecting defects on a wafer |
US9134254B2 (en) | 2013-01-07 | 2015-09-15 | Kla-Tencor Corp. | Determining a position of inspection system output in design data space |
US9311698B2 (en) | 2013-01-09 | 2016-04-12 | Kla-Tencor Corp. | Detecting defects on a wafer using template image matching |
US8826196B2 (en) * | 2013-01-30 | 2014-09-02 | Mentor Graphics Corporation | Integration of optical proximity correction and mask data preparation |
WO2014149197A1 (en) | 2013-02-01 | 2014-09-25 | Kla-Tencor Corporation | Detecting defects on a wafer using defect-specific and multi-channel information |
US8975195B2 (en) * | 2013-02-01 | 2015-03-10 | GlobalFoundries, Inc. | Methods for optical proximity correction in the design and fabrication of integrated circuits |
US8751985B1 (en) * | 2013-03-12 | 2014-06-10 | Globalfoundries Inc. | Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination |
US9865512B2 (en) | 2013-04-08 | 2018-01-09 | Kla-Tencor Corp. | Dynamic design attributes for wafer inspection |
US9310320B2 (en) | 2013-04-15 | 2016-04-12 | Kla-Tencor Corp. | Based sampling and binning for yield critical defects |
US8745547B1 (en) | 2013-07-11 | 2014-06-03 | United Microelectronics Corp. | Method for making photomask layout |
US10360328B2 (en) * | 2015-02-26 | 2019-07-23 | Texas Instruments Incorporated | Methods for converting circuits in circuit simulation programs |
KR102441582B1 (en) | 2015-07-23 | 2022-09-07 | 삼성전자주식회사 | MPC(Mask Process Correction) verification method, and method for fabricating mask comprising the MPC verification method |
US10769331B2 (en) * | 2018-07-12 | 2020-09-08 | International Business Machines Corporation | Verification algorithm engine selection |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4532650A (en) | 1983-05-12 | 1985-07-30 | Kla Instruments Corporation | Photomask inspection apparatus and method using corner comparator defect detection algorithm |
JPS6246518A (en) | 1985-08-23 | 1987-02-28 | Toshiba Corp | Charged beam patterning method |
FR2590376A1 (en) | 1985-11-21 | 1987-05-22 | Dumant Jean Marc | MASKING METHOD AND MASK USED |
US5031111C1 (en) | 1988-08-08 | 2001-03-27 | Trw Inc | Automated circuit design method |
US5182718A (en) * | 1989-04-04 | 1993-01-26 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for writing a pattern on a semiconductor sample based on a resist pattern corrected for proximity effects resulting from direct exposure of the sample by a charged-particle beam or light |
IL99823A0 (en) | 1990-11-16 | 1992-08-18 | Orbot Instr Ltd | Optical inspection method and apparatus |
JP2531114B2 (en) | 1993-10-29 | 1996-09-04 | 日本電気株式会社 | Light intensity distribution analysis method |
US5646870A (en) | 1995-02-13 | 1997-07-08 | Advanced Micro Devices, Inc. | Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers |
US5682323A (en) | 1995-03-06 | 1997-10-28 | Lsi Logic Corporation | System and method for performing optical proximity correction on macrocell libraries |
JP3409493B2 (en) | 1995-03-13 | 2003-05-26 | ソニー株式会社 | Mask pattern correction method and correction device |
US5663893A (en) * | 1995-05-03 | 1997-09-02 | Microunity Systems Engineering, Inc. | Method for generating proximity correction features for a lithographic mask pattern |
JP3934719B2 (en) | 1995-12-22 | 2007-06-20 | 株式会社東芝 | Optical proximity correction method |
US6269472B1 (en) | 1996-02-27 | 2001-07-31 | Lsi Logic Corporation | Optical proximity correction method and apparatus |
US5723233A (en) | 1996-02-27 | 1998-03-03 | Lsi Logic Corporation | Optical proximity correction method and apparatus |
KR100257710B1 (en) | 1996-12-27 | 2000-06-01 | 김영환 | Simulation method of lithography process |
US6016357A (en) | 1997-06-16 | 2000-01-18 | International Business Machines Corporation | Feedback method to repair phase shift masks |
US6370679B1 (en) | 1997-09-17 | 2002-04-09 | Numerical Technologies, Inc. | Data hierarchy layout correction and verification method and apparatus |
AU9775198A (en) | 1997-09-17 | 1999-04-05 | Numerical Technologies, Inc. | Design rule checking system and method |
US6453452B1 (en) | 1997-12-12 | 2002-09-17 | Numerical Technologies, Inc. | Method and apparatus for data hierarchy maintenance in a system for mask description |
WO1999014637A1 (en) | 1997-09-17 | 1999-03-25 | Numerical Technologies, Inc. | Data hierarchy layout correction and verification method and apparatus |
KR20010024116A (en) | 1997-09-17 | 2001-03-26 | 뉴메리컬 테크날러쥐스 인코포레이티드 | Data hierarchy layout correction and verification method and apparatus |
JPH11102380A (en) | 1997-09-26 | 1999-04-13 | Fujitsu Ltd | Graphic processing method, graphic processor and recording medium |
US6009250A (en) * | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Selective flattening in layout areas in computer implemented integrated circuit design |
US6243855B1 (en) * | 1997-09-30 | 2001-06-05 | Kabushiki Kaisha Toshiba | Mask data design method |
US6009251A (en) | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Method and system for layout verification of an integrated circuit design with reusable subdesigns |
US6499003B2 (en) | 1998-03-03 | 2002-12-24 | Lsi Logic Corporation | Method and apparatus for application of proximity correction with unitary segmentation |
US6128067A (en) | 1998-04-28 | 2000-10-03 | Kabushiki Kaisha Toshiba | Correcting method and correcting system for mask pattern |
DE19822147A1 (en) * | 1998-05-16 | 1999-11-18 | Schloemann Siemag Ag | Method and device for sorting out short lengths in fine steel alignment |
US6226781B1 (en) * | 1998-08-12 | 2001-05-01 | Advanced Micro Devices, Inc. | Modifying a design layer of an integrated circuit using overlying and underlying design layers |
US6120952A (en) | 1998-10-01 | 2000-09-19 | Micron Technology, Inc. | Methods of reducing proximity effects in lithographic processes |
US6263299B1 (en) | 1999-01-19 | 2001-07-17 | Lsi Logic Corporation | Geometric aerial image simulation |
US6467076B1 (en) | 1999-04-30 | 2002-10-15 | Nicolas Bailey Cobb | Method and apparatus for submicron IC design |
US6301697B1 (en) | 1999-04-30 | 2001-10-09 | Nicolas B. Cobb | Streamlined IC mask layout optical and process correction through correction reuse |
US6249904B1 (en) | 1999-04-30 | 2001-06-19 | Nicolas Bailey Cobb | Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion |
US6187483B1 (en) | 1999-05-28 | 2001-02-13 | Advanced Micro Devices, Inc. | Mask quality measurements by fourier space analysis |
US6317859B1 (en) | 1999-06-09 | 2001-11-13 | International Business Machines Corporation | Method and system for determining critical area for circuit layouts |
US6643616B1 (en) | 1999-12-07 | 2003-11-04 | Yuri Granik | Integrated device structure prediction based on model curvature |
US6792159B1 (en) | 1999-12-29 | 2004-09-14 | Ge Medical Systems Global Technology Company, Llc | Correction of defective pixels in a detector using temporal gradients |
US6665845B1 (en) | 2000-02-25 | 2003-12-16 | Sun Microsystems, Inc. | System and method for topology based noise estimation of submicron integrated circuit designs |
US6584609B1 (en) | 2000-02-28 | 2003-06-24 | Numerical Technologies, Inc. | Method and apparatus for mixed-mode optical proximity correction |
US6416907B1 (en) | 2000-04-27 | 2002-07-09 | Micron Technology, Inc. | Method for designing photolithographic reticle layout, reticle, and photolithographic process |
US6425113B1 (en) * | 2000-06-13 | 2002-07-23 | Leigh C. Anderson | Integrated verification and manufacturability tool |
EP1330742B1 (en) | 2000-06-13 | 2015-03-25 | Mentor Graphics Corporation | Integrated verification and manufacturability tool |
US7412676B2 (en) * | 2000-06-13 | 2008-08-12 | Nicolas B Cobb | Integrated OPC verification tool |
US6815129B1 (en) | 2000-09-26 | 2004-11-09 | Euv Llc | Compensation of flare-induced CD changes EUVL |
US6453457B1 (en) | 2000-09-29 | 2002-09-17 | Numerical Technologies, Inc. | Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout |
US6792590B1 (en) | 2000-09-29 | 2004-09-14 | Numerical Technologies, Inc. | Dissection of edges with projection points in a fabrication layout for correcting proximity effects |
US6536021B2 (en) * | 2001-02-12 | 2003-03-18 | Hewlett-Packard Company | Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model |
US6668367B2 (en) | 2002-01-24 | 2003-12-23 | Nicolas B. Cobb | Selective promotion for resolution enhancement techniques |
US7013439B2 (en) | 2002-01-31 | 2006-03-14 | Juan Andres Torres Robles | Contrast based resolution enhancing technology |
JP4152647B2 (en) | 2002-03-06 | 2008-09-17 | 富士通株式会社 | Proximity effect correction method and program |
US7172838B2 (en) | 2002-09-27 | 2007-02-06 | Wilhelm Maurer | Chromeless phase mask layout generation |
US6928634B2 (en) | 2003-01-02 | 2005-08-09 | Yuri Granik | Matrix optical process correction |
JP4202214B2 (en) | 2003-09-01 | 2008-12-24 | 富士通マイクロエレクトロニクス株式会社 | Simulation method and apparatus |
-
2000
- 2000-06-13 US US09/593,923 patent/US6425113B1/en not_active Expired - Lifetime
- 2000-12-22 US US09/747,190 patent/US6415421B2/en not_active Expired - Lifetime
-
2001
- 2001-06-05 WO PCT/US2001/018217 patent/WO2001097048A1/en active Application Filing
-
2008
- 2008-06-24 US US12/145,433 patent/US7945871B2/en not_active Expired - Lifetime
Cited By (77)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8977989B2 (en) * | 2000-07-05 | 2015-03-10 | Synopsys, Inc. | Handling of flat data for phase processing including growing shapes within bins to identify clusters |
US20090125867A1 (en) * | 2000-07-05 | 2009-05-14 | Synopsys, Inc. | Handling Of Flat Data For Phase Processing Including Growing Shapes Within Bins To Identify Clusters |
US6711730B2 (en) | 2002-05-13 | 2004-03-23 | Hewlett-Packard Development Company, L.P. | Synthesizing signal net information from multiple integrated circuit package models |
US20040143531A1 (en) * | 2002-05-13 | 2004-07-22 | Frank Mark D. | Synthesizing signal net information from multiple integrated circuit package models |
US20070256039A1 (en) * | 2002-06-07 | 2007-11-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7774726B2 (en) | 2002-06-07 | 2010-08-10 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US20030229875A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Use of models in integrated circuit fabrication |
US20030229410A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Integrated circuit metrology |
US20030237064A1 (en) * | 2002-06-07 | 2003-12-25 | David White | Characterization and verification for integrated circuit designs |
US7325206B2 (en) | 2002-06-07 | 2008-01-29 | Cadence Design Systems, Inc. | Electronic design for integrated circuits based process related variations |
US20080027698A1 (en) * | 2002-06-07 | 2008-01-31 | Cadence Design Systems, Inc. | Method and System for Handling Process Related Variations for Integrated Circuits Based Upon Reflections |
US20030229880A1 (en) * | 2002-06-07 | 2003-12-11 | David White | Test masks for lithographic and etch processes |
US8001516B2 (en) | 2002-06-07 | 2011-08-16 | Cadence Design Systems, Inc. | Characterization and reduction of variation for integrated circuits |
US20030229868A1 (en) * | 2002-06-07 | 2003-12-11 | David White | Electronic design for integrated circuits based process related variations |
US20030228714A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US7962867B2 (en) | 2002-06-07 | 2011-06-14 | Cadence Design Systems, Inc. | Electronic design for integrated circuits based on process related variations |
US7853904B2 (en) | 2002-06-07 | 2010-12-14 | Cadence Design Systems, Inc. | Method and system for handling process related variations for integrated circuits based upon reflections |
US20030226757A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US7757195B2 (en) | 2002-06-07 | 2010-07-13 | Cadence Design Systems, Inc. | Methods and systems for implementing dummy fill for integrated circuits |
US20050037522A1 (en) * | 2002-06-07 | 2005-02-17 | Praesagus Inc., A Massachusetts Corporation | Dummy fill for integrated circuits |
US20050051809A1 (en) * | 2002-06-07 | 2005-03-10 | Praesagus, Inc., A Massachusetts Corporation | Dummy fill for integrated circuits |
US20050132306A1 (en) * | 2002-06-07 | 2005-06-16 | Praesagus, Inc., A Massachusetts Corporation | Characterization and reduction of variation for integrated circuits |
US7712056B2 (en) | 2002-06-07 | 2010-05-04 | Cadence Design Systems, Inc. | Characterization and verification for integrated circuit designs |
US20050196964A1 (en) * | 2002-06-07 | 2005-09-08 | Praesagus, Inc. | Dummy fill for integrated circuits |
US20050235246A1 (en) * | 2002-06-07 | 2005-10-20 | Praesagus, Inc., A Massachusetts Corporation | Use of models in integrated circuit fabrication |
US20030229479A1 (en) * | 2002-06-07 | 2003-12-11 | Smith Taber H. | Dummy fill for integrated circuits |
US20080216027A1 (en) * | 2002-06-07 | 2008-09-04 | Cadence Design Systems, Inc. | Electronic Design for Integrated Circuits Based on Process Related Variations |
US7393755B2 (en) | 2002-06-07 | 2008-07-01 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7383521B2 (en) | 2002-06-07 | 2008-06-03 | Cadence Design Systems, Inc. | Characterization and reduction of variation for integrated circuits |
US7124386B2 (en) | 2002-06-07 | 2006-10-17 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7380220B2 (en) | 2002-06-07 | 2008-05-27 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US7152215B2 (en) | 2002-06-07 | 2006-12-19 | Praesagus, Inc. | Dummy fill for integrated circuits |
US7174520B2 (en) | 2002-06-07 | 2007-02-06 | Praesagus, Inc. | Characterization and verification for integrated circuit designs |
US7367008B2 (en) | 2002-06-07 | 2008-04-29 | Cadence Design Systems, Inc. | Adjustment of masks for integrated circuit fabrication |
US20070101305A1 (en) * | 2002-06-07 | 2007-05-03 | Praesagus, Inc. | Methods and systems for implementing dummy fill for integrated circuits |
US7363099B2 (en) | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Integrated circuit metrology |
US20070157139A1 (en) * | 2002-06-07 | 2007-07-05 | David White | Characterization and verification for integrated circuit designs |
US7243316B2 (en) | 2002-06-07 | 2007-07-10 | Praesagus, Inc. | Test masks for lithographic and etch processes |
US7363598B2 (en) | 2002-06-07 | 2008-04-22 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US20030229412A1 (en) * | 2002-06-07 | 2003-12-11 | David White | Electronic design for integrated circuits based on process related variations |
US7353475B2 (en) | 2002-06-07 | 2008-04-01 | Cadence Design Systems, Inc. | Electronic design for integrated circuits based on process related variations |
US7360179B2 (en) | 2002-06-07 | 2008-04-15 | Cadence Design Systems, Inc. | Use of models in integrated circuit fabrication |
US7356783B2 (en) | 2002-06-07 | 2008-04-08 | Cadence Design Systems, Inc. | Dummy fill for integrated circuits |
US6922822B2 (en) | 2002-07-19 | 2005-07-26 | Hewlett-Packard Development Company, L.P. | Verifying proximity of ground vias to signal vias in an integrated circuit |
US6807657B2 (en) | 2002-07-19 | 2004-10-19 | Hewlett-Packard Development Company, L.P. | Inter-signal proximity verification in an integrated circuit |
US20040015795A1 (en) * | 2002-07-19 | 2004-01-22 | Frank Mark D. | Verifying proximity of ground metal to signal traces in an integrated circuit |
US6769102B2 (en) | 2002-07-19 | 2004-07-27 | Hewlett-Packard Development Company | Verifying proximity of ground metal to signal traces in an integrated circuit |
US20040015796A1 (en) * | 2002-07-19 | 2004-01-22 | Frank Mark D. | Verifying proximity of ground vias to signal vias in an integrated circuit |
EP1391844A2 (en) * | 2002-08-21 | 2004-02-25 | Lsi Logic Corporation | Automatic recognition of an optically periodic structure in an integrated circuit design |
EP1391844A3 (en) * | 2002-08-21 | 2011-12-07 | LSI Logic Corporation | Automatic recognition of an optically periodic structure in an integrated circuit design |
US6709793B1 (en) | 2002-10-31 | 2004-03-23 | Motorola, Inc. | Method of manufacturing reticles using subresolution test patterns |
US7363236B2 (en) | 2003-03-14 | 2008-04-22 | Chartered Semiconductor Manufacturing Ltd. | System, apparatus and method for reticle grade and pricing management |
US20040181769A1 (en) * | 2003-03-14 | 2004-09-16 | Danchai Kochpatcharin | System, apparatus and method for automated tapeout support |
US7069533B2 (en) * | 2003-03-14 | 2006-06-27 | Chatered Semiconductor Manufacturing, Ltd | System, apparatus and method for automated tapeout support |
US20040181458A1 (en) * | 2003-03-14 | 2004-09-16 | Danchai Kochpatcharin | System, apparatus and method for reticle grade and pricing management |
US6996797B1 (en) | 2004-11-18 | 2006-02-07 | International Business Machines Corporation | Method for verification of resolution enhancement techniques and optical proximity correction in lithography |
US20060123364A1 (en) * | 2004-12-07 | 2006-06-08 | International Business Machines Corporation | Method, system and program product for evaluating a circuit |
US7240310B2 (en) * | 2004-12-07 | 2007-07-03 | International Business Machines Corporation | Method, system and program product for evaluating a circuit |
US20060217916A1 (en) * | 2005-03-24 | 2006-09-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for integrally checking chip and package substrate layouts for errors |
US7257784B2 (en) * | 2005-03-24 | 2007-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for integrally checking chip and package substrate layouts for errors |
US7691543B2 (en) * | 2005-05-02 | 2010-04-06 | Elpida Memory, Inc. | Mask data creation method |
US20060246362A1 (en) * | 2005-05-02 | 2006-11-02 | Elpida Memory, Inc. | Mask data creation method |
US20070079269A1 (en) * | 2005-10-05 | 2007-04-05 | Corbeil John D Jr | Method for performing design rule check of integrated circuit |
US7406671B2 (en) * | 2005-10-05 | 2008-07-29 | Lsi Corporation | Method for performing design rule check of integrated circuit |
US10643015B2 (en) | 2006-10-09 | 2020-05-05 | Mentor Graphics Corporation | Properties in electronic design automation |
WO2008045900A1 (en) * | 2006-10-09 | 2008-04-17 | Mentor Graphics Corporation | Properties in electronic design automation |
US20140337810A1 (en) * | 2009-05-14 | 2014-11-13 | Mentor Graphics Corporation | Modular platform for integrated circuit design analysis and verification |
US10596219B2 (en) * | 2010-05-25 | 2020-03-24 | Mentor Graphics Corporation | Logic-driven layout verification |
US20110320990A1 (en) * | 2010-05-25 | 2011-12-29 | Srinivasan Sridhar G | Logic-driven layout verification |
CN103839782A (en) * | 2012-11-27 | 2014-06-04 | 瑞萨电子株式会社 | Mask and method for manufacturing the same, and semicondutor device |
US10199425B2 (en) | 2012-11-27 | 2019-02-05 | Renesas Electronics Corporation | Semiconductor device |
US9825084B2 (en) | 2012-11-27 | 2017-11-21 | Renesas Electronics Corporation | Semiconductor device |
US9864831B2 (en) | 2014-03-28 | 2018-01-09 | Globalfoundries Inc. | Metrology pattern layout and method of use thereof |
US9323882B2 (en) | 2014-03-28 | 2016-04-26 | Globalfoundries Inc. | Metrology pattern layout and method of use thereof |
US20220058836A1 (en) * | 2019-02-25 | 2022-02-24 | Center For Deep Learning In Electronics Manufacturing, Inc. | Methods and systems for compressing shape data for electronic designs |
US11823423B2 (en) * | 2019-02-25 | 2023-11-21 | Center For Deep Learning In Electronics Manufacturing, Inc. | Methods and systems for compressing shape data for electronic designs |
CN113010421A (en) * | 2021-03-16 | 2021-06-22 | 北京奇艺世纪科技有限公司 | Data processing method and device, electronic equipment and storage medium |
Also Published As
Publication number | Publication date |
---|---|
US7945871B2 (en) | 2011-05-17 |
US20080256500A1 (en) | 2008-10-16 |
WO2001097048A1 (en) | 2001-12-20 |
US6425113B1 (en) | 2002-07-23 |
US6415421B2 (en) | 2002-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6415421B2 (en) | Integrated verification and manufacturability tool | |
US7017141B2 (en) | Integrated verification and manufacturability tool | |
US7412676B2 (en) | Integrated OPC verification tool | |
US7337421B2 (en) | Method and system for managing design corrections for optical and process effects based on feature tolerances | |
US6470489B1 (en) | Design rule checking system and method | |
US6370679B1 (en) | Data hierarchy layout correction and verification method and apparatus | |
US6453452B1 (en) | Method and apparatus for data hierarchy maintenance in a system for mask description | |
US7401319B2 (en) | Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design | |
EP1023640B1 (en) | Data hierarchy layout correction and verification method and apparatus | |
US7194725B1 (en) | System and method for design rule creation and selection | |
WO1999014638A1 (en) | Design rule checking system and method | |
WO1999014636A1 (en) | Method and apparatus for data hierarchy maintenance in a system for mask description | |
KR20220050980A (en) | Neural Network-Based Mask Synthesis for Integrated Circuits | |
US11900042B2 (en) | Stochastic-aware lithographic models for mask synthesis | |
US20230205974A1 (en) | Semiconductor Process Technology Assessment | |
Liebmann et al. | Enabling alternating phase shifted mask designs for a full logic gate level | |
US11657207B2 (en) | Wafer sensitivity determination and communication | |
Rosenbusch et al. | New approach to optical proximity correction | |
JPH10240783A (en) | Device and method for desining photomask pattern |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MENTOR GRAPHICS CORPORATION, OREGON Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANDERSON, LEIGH C.;COBB, NICOLAS B.;GRODD, LAURENCE W.;AND OTHERS;REEL/FRAME:011572/0132;SIGNING DATES FROM 20010124 TO 20010126 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: SIEMENS INDUSTRY SOFTWARE INC., TEXAS Free format text: MERGER AND CHANGE OF NAME;ASSIGNORS:MENTOR GRAPHICS CORPORATION;SIEMENS INDUSTRY SOFTWARE INC.;REEL/FRAME:055468/0023 Effective date: 20201230 |