US20010055834A1 - Method of making semiconductor packages at wafer level - Google Patents
Method of making semiconductor packages at wafer level Download PDFInfo
- Publication number
- US20010055834A1 US20010055834A1 US09/925,688 US92568801A US2001055834A1 US 20010055834 A1 US20010055834 A1 US 20010055834A1 US 92568801 A US92568801 A US 92568801A US 2001055834 A1 US2001055834 A1 US 2001055834A1
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- Prior art keywords
- wafer
- dam
- chip scale
- scale packages
- molding compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Definitions
- the present invention generally relates to a chip scale package (CSP), and more particularly, to a method of manufacturing chip scale package at wafer level for accurately dividing the wafer into individual chips.
- CSP chip scale package
- CSP chip scale packages
- BGA ball grid array
- TSOP thin small outline package
- the chip scale package significantly increases the packaging efficiency and has several advantages.
- the CSP package is slightly larger than the chip, and typically, the CSP is about 20 percent larger than the chip itself.
- Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die(KGD) testing.
- CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and re-workability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
- SMT surface mount technology
- flip chip technology such as low inductance, high I/O count, and direct thermal path.
- CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit.
- this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.
- the methods substantially comprise the steps of: a) encapsulating an active surface of a wafer; b) grinding the encapsulated wafer to expose the bumps on the active surface of the wafer and to obtain the predetermined thickness; and c) dicing the encapsulated wafer according to the exposed bump as positioning reference marks.
- the exposed bumps are utilized as the positioning reference marks for dicing the encapsulated wafer.
- the exposed bumps of the individual chip or dice is too tiny to provide an obvious positioning reference mark which is easily detected by the positioning device of the dicing machine or apparatus.
- the positioning device of the dicing machine or apparatus is often positioned in error.
- U.S. Pat. No. 6,004,867 entitled “Chip-size Package Assembled Using Mass Production Techniques At The Wafer-Level” issued on Dec. 21, 1999 to Kim et al., discloses a chip-size package technique at wafer level, wherein a substrate is attached to an active surface of a packaged wafer, the substrate includes grooves or index patterns corresponding to the scribe lines, and the grooves or index patterns in the substrate will be exposed by grinding such that the exposed grooves or index patterns are utilized as positioning reference marks for dicing the wafer.
- Kim's 867 Patent the wafer requires additional attachment of the substrate for dicing, which fails to fulfill the requirements of chip scale package.
- the method of manufacturing chip scale packages at wafer level comprises the step of:
- the dam is form on the active surface of the wafer spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines such that the scribe lines will be exposed without removing the dam.
- the method of manufacturing chip scale packages at wafer level according to the present invention will expose the scribe lines during the manufacturing process, the wafer can be accurately diced according to the exposed scribe lines as positioning reference marks.
- FIG. 1 a is a plan view showing a wafer according to the present invention.
- FIG. 1 b is a partially enlarged sectional view of the chip shown in FIG. 1 a.
- FIG. 2 is a schematic view showing the step of forming the dam enclosing the perimeter of the wafer according to a first embodiment of the present invention.
- FIG. 3 is a schematic view showing the step of encapsulating the wafer with molding according to the first embodiment of the present invention.
- FIG. 4 is a schematic view showing the wafer after the dam being removed according to the first embodiment of the present invention.
- FIG. 5 is a schematic view showing the step of encapsulating the wafer with molding according to a second embodiment of the present invention.
- FIG. 6 is a schematic view showing the wafer after the dam being removed according to the second embodiment of the present invention.
- the present invention relates to a method of mass-producing chip scale package at wafer level so as to reduce the cost of manufacturing chip scale package.
- FIG. 1 a depicts a top plan view of a wafer 10 according to the present invention.
- the wafer 10 has a plurality of chips 11 and a plurality of scribe lines 13 located between the chips 11 .
- FIG. 1 b is a partially enlarged sectional view of the chip 11 shown in FIG. 1 a, in which each of the chips 11 is provided with a plurality of bumps or electrodes 12 on the active surface thereof.
- the electrodes 12 are formed by electroplating on the electrode terminals of the chips 11 , and the electrodes 12 is made of conductive metal material, such as solder or gold, which can be connected with a substrate by soldering.
- the area for effective chips of the wafer 10 is enclosed by dash lines 15 and a dispenser 17 is used to dispense the dam material along the perimeter 21 of the wafer 10 to form a dam 23 surrounding the perimeter 21 of the wafer 10 .
- the material of the dam 23 will be selected to provide substantial viscosity and thixotropic, such as high viscosity epoxy, so as to control the aspect ratio of the dam 23 .
- the typical aspect ratio of the dam 23 is 3:1.
- the molding compound 41 has lower viscosity and contains less filler particles so as to fill the area enclosed by the dam 23 and cover the electrodes 12 to encapsulate the wafer 10 .
- the molding compound 41 can be applied onto the active surface of the wafer 10 by other manners.
- the spin coating method can be used to dispense the molding compound 41 on the rotating wafer 10 and the active surface of the wafer 10 will be uniformly encapsulated with the molding compound 41 by means of the centrifugal force of the rotation of the wafer 10 .
- the cutting tools can accurately dice the wafer 10 to form individual chips 11 according to the exposed scribe lines 13 as positioning reference marks. It should be appreciated by those skilled in this art that before the wafer 10 is diced, the molding compound 41 and the back side surface of the wafer 10 shall be ground to expose the electrodes 12 and to make the thickness of the wafer 10 to be within a predetermined range.
- FIG. 5 and 6 depict a manufacturing process according to the second embodiment of the present invention which is generally similar to the first embodiment of the present invention and where the similar parts are indicated by similar reference characters.
- the difference between the first and the second embodiments lies in that the aspect ratio of the dam 23 a of the second embodiment is smaller than that of the dam 23 of the first embodiment, i.e., the ratio of the width to height on the cross section of the dam 23 a is smaller than that on the dam 23 .
- the width of the dam 23 a is smaller than that of the dam 23 while the height of the dam 23 and the height of the dam 23 a are the same (as shown in FIG. 5). Therefore, the dam 23 a will not fully cover the perimeter 21 of the wafer 10 and will encircle the wafer 10 with a distance spaced from the perimeter 21 .
- the wafer 10 is further encapsulated by the molding compound 41 a . Since the dam 23 a is spaced from the perimeter 21 of the wafer 10 , the scribe lines 13 will not be covered after encapsulated by molding compound 41 a, and thus the wafer 10 can be accurately diced to form individual chips 11 according to the scribe lines 13 as positioning reference marks.
- the wafer of this embodiment still shall be ground to expose the electrodes 12 and to make the thickness of the wafer 10 to be within a predetermined range.
- the present invention provides a method of manufacturing chip scale package at wafer level in which the scribe lines can still be keep visibly after the chip scale package at wafer level is encapsulated by the molding compound so as to accurately dice the wafer to form individual chips according to the scribe lines as positioning reference marks. Therefore, the method according to the present invention can be used to mass-produce chip scale package at wafer level to reduce the cost of manufacturing chip scale package.
Abstract
A method of manufacturing chip scale packages at wafer level, comprising the steps of: a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes; b) forming a dam enclosing the perimeter of the wafer; c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and e) dicing the wafer according to the exposed scribe lines as positioning reference marks.
Description
- 1. Field of the Invention
- The present invention generally relates to a chip scale package (CSP), and more particularly, to a method of manufacturing chip scale package at wafer level for accurately dividing the wafer into individual chips.
- 2. Description of the Related Art
- As electronic devices have become smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP). As compared to the ball grid array (BGA) package and thin small outline package (TSOP), the chip scale package significantly increases the packaging efficiency and has several advantages. For example, the CSP package is slightly larger than the chip, and typically, the CSP is about 20 percent larger than the chip itself. Another advantage of CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die(KGD) testing. In addition, CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and re-workability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
- However, CSP has at least one disadvantage compared to conventional BGA and TSOP, namely, high cost per unit. However, this problem could be eliminated if chip-sized packages could be mass produced more easily. Therefore, there is a need in the semiconductor packaging industry for CSP using mass production techniques at the wafer-level, as is illustrated in U.S. Pat. No. 5,323,051, U.S. Pat. No. 5,925,936 and U.S. Pat. No. 6,004,867.
- For the methods of making the chip scale package at the wafer level disclosed in U.S. Pat. No. 5,323,051 and the U.S. Pat. No. 5,925,936, the methods substantially comprise the steps of: a) encapsulating an active surface of a wafer; b) grinding the encapsulated wafer to expose the bumps on the active surface of the wafer and to obtain the predetermined thickness; and c) dicing the encapsulated wafer according to the exposed bump as positioning reference marks.
- In the above mentioned patents, because the scribe lines is covered by molding compound on the wafer surface after encapsulating, the exposed bumps are utilized as the positioning reference marks for dicing the encapsulated wafer. But the exposed bumps of the individual chip or dice is too tiny to provide an obvious positioning reference mark which is easily detected by the positioning device of the dicing machine or apparatus. Hence, the positioning device of the dicing machine or apparatus is often positioned in error.
- U.S. Pat. No. 6,004,867, entitled “Chip-size Package Assembled Using Mass Production Techniques At The Wafer-Level” issued on Dec. 21, 1999 to Kim et al., discloses a chip-size package technique at wafer level, wherein a substrate is attached to an active surface of a packaged wafer, the substrate includes grooves or index patterns corresponding to the scribe lines, and the grooves or index patterns in the substrate will be exposed by grinding such that the exposed grooves or index patterns are utilized as positioning reference marks for dicing the wafer. However, according to the process of Kim's 867 Patent, the wafer requires additional attachment of the substrate for dicing, which fails to fulfill the requirements of chip scale package.
- Hence, a need exists for a semiconductor package that provides a method of making the chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package so as to overcome the above mentioned drawback.
- It is a primary object of the present invention to provide a method of manufacturing chip scale package at the wafer level for mass production so as to reduce the cost of manufacturing chip scale package.
- It is another object of the present invention to provide a method of manufacturing chip scale package at the wafer level to retain obvious scribe lines after the wafer is encapsulated by molding compound such that the dicing machine can be easily and accurately positioned in dicing process of the chip scale package.
- In order to achieve the objects mentioned hereinabove, the method of manufacturing chip scale packages at wafer level according to an embodiment of the present invention comprises the step of:
- a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines to defining individual chips, and each chip having a plurality of electrodes;
- b) forming a dam enclosing the perimeter of the wafer;
- c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer;
- d) removing the dam to expose the covered scribe lines on the active surface of the wafer; and
- e) dicing the wafer according to the exposed scribe lines as positioning reference marks.
- According to another embodiment of the present invention, the dam is form on the active surface of the wafer spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines such that the scribe lines will be exposed without removing the dam.
- Therefore, since the method of manufacturing chip scale packages at wafer level according to the present invention will expose the scribe lines during the manufacturing process, the wafer can be accurately diced according to the exposed scribe lines as positioning reference marks.
- Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
- FIG. 1a is a plan view showing a wafer according to the present invention.
- FIG. 1b is a partially enlarged sectional view of the chip shown in FIG. 1a.
- FIG. 2 is a schematic view showing the step of forming the dam enclosing the perimeter of the wafer according to a first embodiment of the present invention.
- FIG. 3 is a schematic view showing the step of encapsulating the wafer with molding according to the first embodiment of the present invention.
- FIG. 4 is a schematic view showing the wafer after the dam being removed according to the first embodiment of the present invention.
- FIG. 5 is a schematic view showing the step of encapsulating the wafer with molding according to a second embodiment of the present invention.
- FIG. 6 is a schematic view showing the wafer after the dam being removed according to the second embodiment of the present invention.
- The present invention relates to a method of mass-producing chip scale package at wafer level so as to reduce the cost of manufacturing chip scale package. Now the preferable embodiments according to the present invention will be described in detail while taken in conjunction with the accompanying drawings. In the accompanying drawings, like reference numbers refer to corresponding parts throughout.
- FIG. 1a depicts a top plan view of a
wafer 10 according to the present invention. Thewafer 10 has a plurality ofchips 11 and a plurality ofscribe lines 13 located between thechips 11. FIG. 1b is a partially enlarged sectional view of thechip 11 shown in FIG. 1a, in which each of thechips 11 is provided with a plurality of bumps orelectrodes 12 on the active surface thereof. Theelectrodes 12 are formed by electroplating on the electrode terminals of thechips 11, and theelectrodes 12 is made of conductive metal material, such as solder or gold, which can be connected with a substrate by soldering. - Now referring to FIG. 2, the area for effective chips of the
wafer 10 is enclosed bydash lines 15 and adispenser 17 is used to dispense the dam material along theperimeter 21 of thewafer 10 to form adam 23 surrounding theperimeter 21 of thewafer 10. The material of thedam 23 will be selected to provide substantial viscosity and thixotropic, such as high viscosity epoxy, so as to control the aspect ratio of thedam 23. The typical aspect ratio of thedam 23 is 3:1. Once the material ofdam 23 is selected, the dispensing speed of thedispenser 17 can be optimum and the dispensing speed will have some influences on the dam's aspect ratio. - Referring to FIG. 3, after the
dam 23 encloses theentire perimeter 21 of thewafer 10, anotherdispenser 19 will be provided to dispense themolding compound 41. Themolding compound 41 has lower viscosity and contains less filler particles so as to fill the area enclosed by thedam 23 and cover theelectrodes 12 to encapsulate thewafer 10. It will be appreciated by those skilled in this art that themolding compound 41 can be applied onto the active surface of thewafer 10 by other manners. For example, the spin coating method can be used to dispense themolding compound 41 on the rotatingwafer 10 and the active surface of thewafer 10 will be uniformly encapsulated with themolding compound 41 by means of the centrifugal force of the rotation of thewafer 10. - It should be noted that, according to the embodiment of the present invention, after the
molding compound 41 and thedam 23 are cured, a separating interface will form therebetween, and thus thedam 23 can be removed easily from thewafer 10 and themolding compound 41 can retain its integrity for encapsulating the wafer 10 (as shown in FIG. 4). - Referring to FIG. 4, after the
dam 23 is removed, the scribe lines 13 covered by thedam 23 on theperimeter 21 of thewafer 10 will be exposed. Therefore, the cutting tools can accurately dice thewafer 10 to formindividual chips 11 according to the exposedscribe lines 13 as positioning reference marks. It should be appreciated by those skilled in this art that before thewafer 10 is diced, themolding compound 41 and the back side surface of thewafer 10 shall be ground to expose theelectrodes 12 and to make the thickness of thewafer 10 to be within a predetermined range. - Now referring to FIG. 5 and6, they depict a manufacturing process according to the second embodiment of the present invention which is generally similar to the first embodiment of the present invention and where the similar parts are indicated by similar reference characters. The difference between the first and the second embodiments lies in that the aspect ratio of the
dam 23 a of the second embodiment is smaller than that of thedam 23 of the first embodiment, i.e., the ratio of the width to height on the cross section of thedam 23 a is smaller than that on thedam 23. The width of thedam 23 a is smaller than that of thedam 23 while the height of thedam 23 and the height of thedam 23 a are the same (as shown in FIG. 5). Therefore, thedam 23 a will not fully cover theperimeter 21 of thewafer 10 and will encircle thewafer 10 with a distance spaced from theperimeter 21. - As shown in FIG. 6, the
wafer 10 is further encapsulated by themolding compound 41 a. Since thedam 23 a is spaced from theperimeter 21 of thewafer 10, the scribe lines 13 will not be covered after encapsulated by moldingcompound 41 a, and thus thewafer 10 can be accurately diced to formindividual chips 11 according to the scribe lines 13 as positioning reference marks. - Similarly, it also will be appreciated that the wafer of this embodiment still shall be ground to expose the
electrodes 12 and to make the thickness of thewafer 10 to be within a predetermined range. - As described hereinabove, the present invention provides a method of manufacturing chip scale package at wafer level in which the scribe lines can still be keep visibly after the chip scale package at wafer level is encapsulated by the molding compound so as to accurately dice the wafer to form individual chips according to the scribe lines as positioning reference marks. Therefore, the method according to the present invention can be used to mass-produce chip scale package at wafer level to reduce the cost of manufacturing chip scale package.
- Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.
Claims (12)
1. A method of manufacturing chip scale packages at wafer level, comprising the steps of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes;
b) forming a dam enclosing the perimeter of the wafer;
c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer;
d) removing the dam to expose the scribe lines covered by the dam on the active surface of the wafer; and
e) dicing the wafer to form individual chips according to the exposed scribe lines as positioning reference marks.
2. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the dam is made from a high viscosity and thixotropy material.
claim 1
3. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the ratio of the width to height on the cross section of the dam is 3:1.
claim 1
4. The method of manufacturing chip scale packages at wafer level as claimed in , further comprising a step of:
claim 1
grinding the molding compound on the wafer to expose the electrodes out of the molding compound.
5. The method of manufacturing chip scale packages at wafer level as claimed in , further comprising a step of:
claim 1
grinding the back side of the wafer to a thickness within a predetermined range.
6. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the molding compound is filled by spin coating process to encapsulate the active surface of the wafer.
claim 1
7. A method of manufacturing chip scale packages at wafer level, comprising the steps of:
a) providing a wafer having an active and a back side surface, the active surface of the wafer having a plurality of scribe lines defining individual chips, and each chip having a plurality of electrodes;
b) forming a dam spaced a predetermined distance from the perimeter of the wafer to expose the scribe lines;
c) filling the area enclosed by the dam with molding compound to encapsulate the active surface of the wafer; and
d) dicing the wafer according to the exposed scribe lines as positioning reference marks.
8. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the dam is made from a high viscosity and thixotropy material.
claim 7
9. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the ratio of the width to height on the cross section of the dam is 3:1.
claim 1
10. The method of manufacturing chip scale packages at wafer level as claimed in , further comprising a step of:
claim 7
grinding the molding compound on the wafer to expose the electrodes out of the molding compound.
11. The method of manufacturing chip scale packages at wafer level as claimed in , further comprising a step of:
claim 7
grinding the back side of the wafer to a thickness within a predetermined range.
12. The method of manufacturing chip scale packages at wafer level as claimed in , wherein the molding compound is filled by spin coating process to encapsulate the active surface of the wafer.
claim 7
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW089112245A TW452873B (en) | 2000-06-21 | 2000-06-21 | Manufacturing method of wafer scale semiconductor package structure |
TW89112245 | 2000-06-21 |
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US20010055834A1 true US20010055834A1 (en) | 2001-12-27 |
US6455353B2 US6455353B2 (en) | 2002-09-24 |
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US09/925,688 Expired - Lifetime US6455353B2 (en) | 2000-06-21 | 2001-08-10 | Method of making semiconductor packages at wafer level |
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US (1) | US6455353B2 (en) |
TW (1) | TW452873B (en) |
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US20060001139A1 (en) * | 2003-09-19 | 2006-01-05 | Wood Alan G | Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates |
US20060191475A1 (en) * | 2004-04-29 | 2006-08-31 | Benson Peter A | Apparatus for spin coating semiconductor substrates |
US20070158833A1 (en) * | 2006-01-04 | 2007-07-12 | Soo-San Park | Integrated circuit package system including stacked die |
US7687315B2 (en) | 2005-04-29 | 2010-03-30 | Stats Chippac Ltd. | Stacked integrated circuit package system and method of manufacture therefor |
US7750482B2 (en) | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
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US20100261315A1 (en) * | 2009-04-14 | 2010-10-14 | Wen-Jeng Fan | Wafer level packaging method |
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JP2001516145A (en) * | 1997-08-21 | 2001-09-25 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | Semiconductor wafer processing method |
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-
2001
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
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US6455353B2 (en) | 2002-09-24 |
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