US20020052063A1 - Method and apparatus for packaging a microelectronic die - Google Patents
Method and apparatus for packaging a microelectronic die Download PDFInfo
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- US20020052063A1 US20020052063A1 US09/955,897 US95589701A US2002052063A1 US 20020052063 A1 US20020052063 A1 US 20020052063A1 US 95589701 A US95589701 A US 95589701A US 2002052063 A1 US2002052063 A1 US 2002052063A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
Description
- This invention relates to methods and apparatuses for packaging microelectronic devices; more particularly, this invention relates to encapsulating microelectronic dies in the manufacturing of memory devices, microprocessors and other types of microelectronic devices.
- Many packaged microelectronic devices have a substrate, a microelectronic die attached to the substrate, and a protective covering encasing the die. The protective covering is generally a plastic or ceramic compound that can be molded to form a casing over the die. The microelectronic die can be a memory device, a microprocessor, or another type of microelectronic assembly having integrated circuitry. Several types of packaged devices also include bond pads on the substrate that are coupled to the integrated circuitry of the die. The bond pads may alternatively be coupled to pins or other types of terminals that are exposed on the exterior of the microelectronic device for connecting the die to buses, circuits and/or other microelectronic assemblies.
- A significant limiting factor for manufacturing packaged microelectronic devices is encapsulating the die with the protective covering. The dies are sensitive components that should be protected from physical contact and environmental conditions to avoid damaging the die. The protective casing encapsulating the die, therefore, should seal the die from the environmental factors (e.g., moisture) and shield the die from electrical and mechanical shocks.
- One conventional technique for encapsulating the die is known as “transfer-molding,” which involves placing the die and at least a portion of the substrate in a cavity of a mold and then injecting a thermosetting material into the cavity. The thermosetting material flows over the die on one side of the substrate until it fills the cavity, and then the thermosetting material is cured so that it hardens into a suitable protective casing for protecting the die. The protective casing should not have any voids over the die because contaminants from the molding process or environmental factors could damage the die. The thermosetting material, moreover, should not cover a ball-pad array on the substrate or damage any electrical connections between the die and the substrate. Therefore, it is important to control the flow of the thermosetting material in the cavity to avoid (a) producing voids in the protective casing over the die, (b) covering portions of the substrate with the thermosetting material that are not to be covered with the protective covering, and (c) displacing or otherwise damaging any wiring or solder joints between the die and the substrate.
- One drawback of transfer-molding is that it is difficult to avoid producing voids in the thermosetting material. In one particular transfer-molding technique, a first protective casing is formed over the die on a first surface of the substrate, and a second protective casing is formed over contacts on the die and wire-bond connections on a second surface of the substrate. The first casing is formed from a first flow of the thermosetting compound, and the second casing is formed from a second flow of the thermosetting compound. This transfer-molding technique may result in voids along either the first or second surface of the substrate because the first and second flows may counter one another as they flow through the mold. Other transfer-molding techniques may also produce voids in the protective casing over the die because the flow of the thermosetting material in the mold may produce a first flow section that moves in a direction counter to a second flow section. Therefore, it would be desirable to eliminate voids in the protective casing.
- The present invention is directed toward methods and apparatuses for encapsulating a microelectronic die or another type of microelectronic device. One aspect of the present invention is directed toward packaging a microelectronic die that is attached to either a first surface or a second surface of a substrate. The die can be encapsulated by positioning the die in a cavity of a mold and sealing the substrate to the mold. The method can further include injecting an encapsulation compound into the cavity at a first end of the substrate so that the compound moves along the first surface of the substrate. This portion of the compound defines a first flow of compound along the first surface that moves in a first direction from a first end of the mold toward a second end of the mold. The method can also include driving a portion of the compound through the substrate at a pass-through location or a secondary gate that is spaced apart from the first end of the substrate to generate a second flow of compound along the second surface of the substrate. The second flow of compound moves in a second direction toward the first end of the mold. As the first and second flows of compound move through the mold, the method includes inhibiting a third flow of compound from moving in the first direction along the second surface of the substrate between the first end of the substrate and the pass-through location.
- Another aspect of this invention is a microelectronic device comprising a substrate, a microelectronic die attached to substrate, and a cover encasing at least a portion of the die. The substrate can have a first surface, a second surface, and plurality of ball-pads on the second surface. The microelectronic die can have a first side attached to the first surface of the substrate, a plurality of contacts on the first side, and an integrated circuit coupled to the contacts. The contacts of the die can be electrically coupled to the ball-pads of the substrate by a plurality of connectors. The cover can further include a first casing encapsulating the die and a portion of the first surface of the substrate, and a second casing encapsulating the contacts on the first side of the die and the connectors. The first casing has a first end, a second end, a first gate section at the first end, and a second gate section also at the first end. The first and second gate sections are spaced apart from one another along the first end.
- FIG. 1 is a top cutaway isometric view of a microelectronic device before being packaged in accordance with a method of one embodiment of the invention.
- FIG. 2 is a side elevation view of the microelectronic device of FIG. 1.
- FIG. 3A is a top plan view of a first mold section for encapsulating a microelectronic device in accordance with an embodiment of the invention.
- FIG. 3B is a bottom plan view of a second mold section for use with the first mold section of FIG. 3A.
- FIG. 4 is a partial front cross-sectional view of the first and second mold sections of FIGS. 3A and 3B in an operating position in accordance with an embodiment of the invention.
- FIG. 5A is a partial front cross-sectional view of a microelectronic device being packaged using the first and second mold sections of FIG. 4 according to an embodiment of the invention.
- FIG. 5B is a side cross-sectional view of the microelectronic device of FIG. 5A being packaged using the first and second mold sections of FIG. 4 in accordance with an embodiment of the invention.
- FIG. 6 is a top isometric view of a packaged microelectronic device before singulation in accordance with an embodiment of the invention.
- The following disclosure is directed toward packaged microelectronic devices, and to methods for encapsulating a microelectronic die or another type of microelectronic device. Several embodiments of the invention are described with respect to memory devices, but the methods and apparatuses are also applicable to microprocessors and other types of devices. One skilled in the art will accordingly understand that the present invention may have additional embodiments, or that the invention may be practiced without several of the details described below.
- FIG. 1 is a top cutaway isometric view of a
microelectronic device 10 that is to be encapsulated using a method in accordance with one embodiment of the invention. Themicroelectronic device 10 can include asubstrate 20 and amicroelectronic die 40 attached to thesubstrate 20 by an adhesive 60. Themicroelectronic device 10 shown in FIG. 1 illustrates thesubstrate 20 and the die 40 before encapsulating thedie 40 with an encapsulation compound, such as a mold compound. The following description is directed toward encapsulating a microelectronic die on a flexible substrate, but it is expected that several embodiments of methods and molds in accordance with the present invention may be used to encapsulate a large variety of electrical and/or non-electrical articles. Therefore, the following description with respect to encapsulating themicroelectronic die 10 shown in FIGS. 1-6 is for purposes of illustration only, and is not intended to limit the scope of the invention. - The embodiment of the
substrate 20 shown in FIG. 1 can have afirst end 21, asecond end 22 opposite thefirst end 21, afirst surface 23, and asecond surface 24 opposite thefirst surface 23. Thesubstrate 20 can also include anelongated slot 25 between the first andsecond surfaces substrate 20. Additionally, anaperture 26 can extend through thesubstrate 20 at secondary gate location or a pass-through location that is generally proximate to thesecond end 22 of thesubstrate 20. Thesubstrate 20 is generally an interposing device that provides an array of ball-pads for coupling very small contacts on the microelectronic die to another type of device. In the embodiment shown in FIG. 1, thesubstrate 20 includes a first array of ball-pads 27, a second array ofterminal pads 28 proximate to theslot 25, and atrace 29 or other type of conductive line between each ball-pad 27 and correspondingterminal pad 28. Thesubstrate 20 can be a flexible material or a substantially rigid material, and thetraces 29 can be conductive lines that are printed on the substrate in a manner similar to printed circuit boards. - The embodiment of the microelectronic die40 shown in FIG. 1 includes a
first side 41 attached to thefirst surface 23 of thesubstrate 20 by the adhesive 60. The microelectronic die 40 can also include a plurality ofsmall contacts 42 and an integrated circuit 44 (shown schematically) coupled to thecontacts 42. Thecontacts 42 are arranged in an array along thefirst side 41 of the microelectronic die 40 so that thecontacts 42 are aligned with or otherwise accessible through theslot 25 in thesubstrate 20. A plurality of wire-bonds or other types ofconnectors 50 couple thecontacts 42 of the die 40 to correspondingterminal pads 28 on thesubstrate 20. As such, thesubstrate 20 distributes the verysmall contacts 42 to the larger array of ball-pads 27. - The adhesive60 can be a two-sided tape or a decal adhered to the
first surface 23 of thesubstrate 20 adjacent to the sides of theslot 25. In a typical application, the adhesive 60 creates asmall gap 61 at the end of theslot 25 toward thefirst end 21 of thesubstrate 20. Thegap 61 is defined by the distance between thefirst surface 23 of thesubstrate 20 and thefirst side 41 of the die 40, which is generally equal to the thickness of the adhesive 60. As explained in more detail below, thegap 61 can create several difficulties in encapsulating theterminal pads 28, theconnectors 50, and thecontacts 42. - FIG. 2 is a side elevation view of the
microelectronic device 10 after thedie 40 and a portion of thesubstrate 20 have been encapsulated by amold compound 70. Themold compound 70 can be injected into a mold (not shown in FIG. 2) to form afirst casing 72 that encapsulates thedie 40 and asecond casing 74 that fills the slot 25 (FIG. 1). Thefirst casing 72 also covers a portion of thefirst surface 23 of thesubstrate 20, and thesecond casing 74 also covers theterminal pads 28 on the substrate 20 (FIG. 1), the connectors 50 (FIG. 1), and thecontacts 42 on the die 40 (FIG. 1). - The
first casing 72 can be formed by injecting the mold compound through a gate of a mold at thefirst end 21 of thesubstrate 20 so that the mold compound flows along thefirst surface 23 of thesubstrate 20 in a first direction (shown by arrows A1-A3). Thesecond casing 74 is then formed by driving a portion of the mold compound through theaperture 26 and/or anotheropening 62 defined by another gap at the other end of theslot 25 toward thesecond end 22 of thesubstrate 20. Theaperture 26 and/or theopening 62 define a pass-through location or a secondary gate location that is spaced apart from thefirst end 21 of thesubstrate 20 to generate a second flow of compound along thesecond surface 24 of the substrate 20 (shown by arrows B1-B3). The second flow of mold compound moves in a second direction away from the second 22 end of thesubstrate 20 toward thefirst end 21. - The process of fabricating the first and
second casings gap 61 between the die 40 and thesubstrate 20 at the end of theslot 25 toward thefirst end 21 of the substrate 20 (arrow D1). Such a third flow of mold compound would move counter to the second flow of mold compound along thesecond surface 24 of thesubstrate 20. As a result, voids or other disparities may be created in thesecond casing 74 where the third flow of mold compound (arrow D1) meets the second flow of mold compound (arrows B1-B3). One aspect of the present invention is to inhibit creating the third flow of mold compound that moves in the first direction along thesecond surface 24 of thesubstrate 20 between the first end of thesubstrate 21 and the pass-through location toward thesecond end 22 of thesubstrate 20. - FIG. 3A is a top plan view of a
first mold section 100 and FIG. 3B is a bottom plan view of asecond mold section 200 for forming the first andsecond casings 72 and 74 (FIG. 2) in a manner that inhibits or eliminates a third flow of mold compound through the gap 61 (FIG. 1) between thesubstrate 20 and thedie 40. The embodiment of thefirst mold section 100 shown in FIG. 3A includes afirst end 102, asecond end 103, a bearingsurface 120 for contacting thefirst side 23 of the substrate 20 (FIG. 1), and afirst cavity 104 for receiving the die 40 (FIG. 1). Thecavity 104 can have afirst side 105, asecond side 106 opposite the first side, afirst end 107, and asecond end 108 opposite the first end. Thefirst mold section 100 can also include a plurality of gates including at least a first gate 110 a and asecond gate 110 b that are separated from one another by anisland 112. The first gate 110 a can open into thecavity 104 at a location proximate to thefirst side 105, and thesecond gate 110 b can open into thecavity 104 at a location proximate to thesecond side 106. The first andsecond gates 110 a and 110 b can meet at acommon feed port 114. The first andsecond gates 110 a and 110 b define a gate pair that is coupled to a commonfirst cavity 104 in the first mold section. Thefirst mold section 100 can further include aflow restrictor 115 at the end of each of the first andsecond gates 110 a and 110 b. In operation, an injection flow F of molding compound or encapsulating compound is injected through thefeed port 114 and thegates 110 a and 110 b. Theisland 112 splits the injection flow F into a first injection flow F1 passing through the first gate 110 a and a second injection flow F2 passing through thesecond gate 110 b. - FIG. 3B illustrates an embodiment of a
second mold section 200 for forming the second casing 74 (FIG. 2) over theslot 25 of the substrate 20 (FIG. 1). Thesecond mold section 200 can include abearing surface 220 for contacting thesecond side 24 of the substrate 20 (FIG. 1). Thesecond mold section 200 can also include asecond cavity 225 configured to be superimposed over theslot 25 of thesubstrate 20 when the bearingsurface 220 engages thefirst surface 24 of thesubstrate 20. - FIG. 4 is a partial cross-sectional view of a
mold assembly 400 including thefirst mold section 100 shown in FIG. 3A and thesecond mold section 200 shown in FIG. 3B. Thefirst mold section 100 is superimposed under thesecond mold section 200 so that thesecond cavity 225 of the second encapsulating section is over thefirst cavity 104 of thefirst mold section 100. Theisland 112 positions the opening of the first gate 110 a toward thefirst side 105 of thefirst cavity 104 and the opening of thesecond gate 110 b toward thesecond side 106 of thefirst cavity 104. Referring to FIGS. 3A and 4 together, the first injection flow F1 flows through the first gate 110 a and enters thecavity 104 proximate to thefirst side 105, and a second injection flow F2 flows through thesecond gate 110 b and enters thecavity 104 proximate to thesecond side 106. - The
first mold section 100 can have a plurality of individualfirst cavities 104, and thesecond mold section 200 can have a plurality of individualsecond cavities 225. Thefirst cavities 104 are arranged with respect to thesecond cavities 225 so that eachfirst cavity 104 is superimposed under a correspondingsecond cavity 225. Additionally, thefirst mold section 100 can have a plurality of gate pairs that each have a first gate 110 a and asecond gate 110 b. The openings of the first andsecond gates 110 a and 110 b of each gate pair are spaced apart from one another at thefirst end 107 of a correspondingfirst cavity 104. As such, thefirst mold section 100 can form afirst casing 72 and asecond casing 74 on a plurality of individual microelectronic devices in a single molding cycle in a manner that provides a bifurcated flow of mold compound into the first end of each of thefirst cavities 104. - FIGS. 5A and 5B illustrate an embodiment of a method for encapsulating the microelectronic die40 and the
slot 25 of thesubstrate 20. FIG. 5A, more specifically, is a partial front cross-sectional view illustrating themicroelectronic device 10 being encapsulated using the first andsecond mold sections surface 120 of thefirst mold section 100 presses against a perimeter portion of thefirst surface 23 of thesubstrate 20, and thebearing surface 220 of thesecond mold section 200 presses against thesecond surface 24 of thesubstrate 20. The bearingsurface 220 of thesecond mold section 200 can press against thesecond surface 24 of thesubstrate 20 by injecting a mold compound into thecavity 104, as explained in U.S. patent application Ser. No. 09/255,554, which is herein incorporated by reference. The first and second injection flows F1 and F2 of the mold compound pass through the first andsecond gates 110 a and 110 b to enter thecavity 104 along the side regions of themicroelectronic die 40. As a result, the high pressure flow of mold compound does not flow directly toward the gap 61 (FIG. 1) between thesubstrate 20 and the die 40 proximate to thefirst end 21 of thesubstrate 20. The first and second injection flows F1 and F2 of the mold compound accordingly fill thefirst cavity 104 in a manner that does not cause the mold compound to generate a flow in theslot 25 of thesubstrate 20 that flows toward thesecond end 22 of thesubstrate 20. Therefore, the first andsecond gates 110 a and 110 b provide a mold that inhibits voids or other asperities from forming in thesecond casing 74. Moreover, thefirst mold section 100 surprisingly does not create voids or asperities in thefirst casing 72 even though it produces a bifurcated flow of mold compound in thefirst cavity 104. - FIG. 5B is a side cross-sectional view illustrating the flow of mold compound through the first and
second mold sections island 112 and into thefirst end 107 of thefirst cavity 104 to create a first flow A1 heading in a first direction toward thesecond end 22 of thesubstrate 20. The first flow A1 of mold compound passes through theaperture 26 at the pass-through location toward thesecond end 22 of thesubstrate 20 to generate a second flow B1 of mold compound that flows through thesecond cavity 225 of thesecond mold section 200. The second flow B1 of mold compound fills theslot 25 of thesubstrate 20 and flows in a second direction until it reaches aterminal end 217 of thesecond cavity 225. - FIG. 6 is a top isometric view of an encapsulated
microelectronic device 10 having thefirst casing 72 over the die 40 on thefirst surface 23 of thesubstrate 20. FIG. 6 illustrates themicroelectronic device 10 before it has been “singulated” to remove unnecessary portions of thesubstrate 20 and molding compound. In this embodiment, the microelectronic die 40 (FIG. 1) and a portion of thesubstrate 20 are encapsulated by thefirst casing 72. Before singulating the device, themicroelectronic device 10 includes aflash section 80 of mold compound having afirst gate section 82 andsecond gate section 84. Thefirst gate section 82 corresponds to the portion of the mold compound in the first gate 110 a (FIG. 3A) at the end of the encapsulating process, and thesecond gate section 84 corresponds to the portion of the mold compound in thesecond gate 110 b. - FIG. 7 is a bottom isometric view of the
microelectronic device 10 having thesecond casing 74 over theslot 25 of thesubstrate 20. In this embodiment, thesecond casing 74 covers the terminal pads 28 (FIG. 1), the connectors 50 (FIG. 1), and thecontacts 42 on thefirst surface 41 of the die 40 (FIG. 1). Themicroelectronic device 10 is then singulated to remove the excess portion of theflash 80 and thesubstrate 20. - From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/955,897 US6683388B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/595,623 US6589820B1 (en) | 2000-06-16 | 2000-06-16 | Method and apparatus for packaging a microelectronic die |
US09/955,897 US6683388B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
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US09/595,623 Division US6589820B1 (en) | 2000-06-16 | 2000-06-16 | Method and apparatus for packaging a microelectronic die |
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US20020052063A1 true US20020052063A1 (en) | 2002-05-02 |
US6683388B2 US6683388B2 (en) | 2004-01-27 |
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Application Number | Title | Priority Date | Filing Date |
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US09/595,623 Expired - Lifetime US6589820B1 (en) | 2000-06-16 | 2000-06-16 | Method and apparatus for packaging a microelectronic die |
US09/955,897 Expired - Lifetime US6683388B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
US09/955,613 Expired - Lifetime US6664139B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
US09/955,612 Expired - Lifetime US6677675B2 (en) | 2000-06-16 | 2001-09-19 | Microelectronic devices and microelectronic die packages |
US09/955,620 Expired - Lifetime US6653173B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/595,623 Expired - Lifetime US6589820B1 (en) | 2000-06-16 | 2000-06-16 | Method and apparatus for packaging a microelectronic die |
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Application Number | Title | Priority Date | Filing Date |
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US09/955,613 Expired - Lifetime US6664139B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
US09/955,612 Expired - Lifetime US6677675B2 (en) | 2000-06-16 | 2001-09-19 | Microelectronic devices and microelectronic die packages |
US09/955,620 Expired - Lifetime US6653173B2 (en) | 2000-06-16 | 2001-09-19 | Method and apparatus for packaging a microelectronic die |
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US6589820B1 (en) | 2000-06-16 | 2003-07-08 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US6483044B1 (en) | 2000-08-23 | 2002-11-19 | Micron Technology, Inc. | Interconnecting substrates for electrical coupling of microelectronic components |
US6979595B1 (en) | 2000-08-24 | 2005-12-27 | Micron Technology, Inc. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
-
2000
- 2000-06-16 US US09/595,623 patent/US6589820B1/en not_active Expired - Lifetime
-
2001
- 2001-09-19 US US09/955,897 patent/US6683388B2/en not_active Expired - Lifetime
- 2001-09-19 US US09/955,613 patent/US6664139B2/en not_active Expired - Lifetime
- 2001-09-19 US US09/955,612 patent/US6677675B2/en not_active Expired - Lifetime
- 2001-09-19 US US09/955,620 patent/US6653173B2/en not_active Expired - Lifetime
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6653173B2 (en) | 2000-06-16 | 2003-11-25 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US6664139B2 (en) | 2000-06-16 | 2003-12-16 | Micron Technology, Inc. | Method and apparatus for packaging a microelectronic die |
US20030029633A1 (en) * | 2000-08-23 | 2003-02-13 | Ahmad Syed Sajid | Interconnecting substrates for electrical coupling of microelectronic components |
US20030109083A1 (en) * | 2000-08-23 | 2003-06-12 | Ahmad Syed Sajid | Interconnecting substrates for electrical coupling of microelectronic components |
US20030106709A1 (en) * | 2000-08-23 | 2003-06-12 | Ahmad Syed Sajid | Interconnecting substrates for electrical coupling of microelectronic components |
US6796028B2 (en) | 2000-08-23 | 2004-09-28 | Micron Technology, Inc. | Method of Interconnecting substrates for electrical coupling of microelectronic components |
US20020175399A1 (en) * | 2000-08-24 | 2002-11-28 | James Stephen L. | Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such packaged microelectronic devices |
US20050056919A1 (en) * | 2000-08-28 | 2005-03-17 | Cobbley Chad A. | Packaged microelectronic devices with interconnecting units and methods for manufacturing and using the interconnecting units |
US20070063335A1 (en) * | 2000-08-28 | 2007-03-22 | Micron Technology, Inc. | Packaged microelectronic devices with interconnecting units and methods for manufacturing and using the interconnecting units |
US6963142B2 (en) | 2001-10-26 | 2005-11-08 | Micron Technology, Inc. | Flip chip integrated package mount support |
US20070281077A1 (en) * | 2004-01-06 | 2007-12-06 | Hock Lin T | Method for packaging integrated circuit dies |
CN111391243A (en) * | 2020-03-24 | 2020-07-10 | 环维电子(上海)有限公司 | Plastic packaging mold based on one-time double-sided plastic packaging technology and plastic packaging method thereof |
Also Published As
Publication number | Publication date |
---|---|
US6683388B2 (en) | 2004-01-27 |
US20020016023A1 (en) | 2002-02-07 |
US6589820B1 (en) | 2003-07-08 |
US20020050654A1 (en) | 2002-05-02 |
US20020048843A1 (en) | 2002-04-25 |
US6653173B2 (en) | 2003-11-25 |
US6664139B2 (en) | 2003-12-16 |
US6677675B2 (en) | 2004-01-13 |
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