US20020110984A1 - Method of fabricating a trenched flash memory cell - Google Patents
Method of fabricating a trenched flash memory cell Download PDFInfo
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- US20020110984A1 US20020110984A1 US09/779,540 US77954001A US2002110984A1 US 20020110984 A1 US20020110984 A1 US 20020110984A1 US 77954001 A US77954001 A US 77954001A US 2002110984 A1 US2002110984 A1 US 2002110984A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a method of fabricating a trenched flash memory cell, and more particularly, to a method of fabricating a trenched flash memory cell to raise the coupling ratio (CR) and hence improve the electrical performance of the element.
- a stacked-gate flash memory cell comprises a floating gate for storing electric charges, a controlling gate for controlling the charging of the floating gate, and an ONO (oxide-nitride-oxide) dielectric layer positioned between the floating gate and the controlling gate. Similar to a capacitor, the flash memory stores electric charges in the floating gate to represent a digital data bit of “1”, and removes charge from the floating gate to represent a digital data bit of “0”.
- ONO oxide-nitride-oxide
- FIG. 1 is a cross-sectional diagram of a conventional stacked-gate flash memory cell 10 .
- the flash memory cell 10 comprises a stacked gate 14 positioned on the surface of a silicon substrate 12 , a source 24 and drain 26 positioned adjacent to each side of the stacked gate 14 .
- the stacked gate 14 is composed of a tunnel oxide layer 16 , a floating gate 18 , an ONO dielectric layer 20 and a controlling gate 22 , respectively.
- CHE channel hot electrons
- a Fowler Nordheim tunneling technique is used for data erase, which involves grounding of the controlling gate 22 or applying a negative voltage to the controlling gate 22 .
- the drain 26 is highly biased so as to expel the electrons trapped in the floating gate 18 .
- a coupling ratio (CR value) is used as an index to evaluate the performance of a flash memory cell.
- C 1 is the capacitance between the floating gate 18 and the controlling gate 22
- C 2 is the capacitance between the floating gate 18 and the source 24
- C 3 is the capacitance between the floating gate 18 and the silicon substrate 12
- C 4 is the capacitance between the floating gate 18 and the drain 26
- the CR value of the flash memory cell 10 is defined as:
- one method of increasing the CR value is to increase the capacitor surface between the floating gate 18 and the controlling gate 22 , as this surface is proportional to the capacitance C 1 .
- surface enlargement is limited as the line width of either the floating gate 18 or the controlling gate 22 is defined to increase the element integration.
- difficulty occurs in raising both the capacitance and accessing speed of the flash memory cell 10 through the increase of the surface area of the floating gate 18 or the controlling gate 22 .
- the stacked-gate flash memory cell 10 enhances integration, it is, however, prone to over-erasing.
- a plurality of shallow trench isolation (STI) structures are formed to enclose at least an active area in a silicon substrate.
- a first ion implantation process is performed on the silicon substrate to form a doped region, followed by the deposition of an isolation layer on the surface of the silicon substrate.
- a first photo and etching process is performed to form two trenches within the active area.
- a tunnel oxide layer, a floating gate, and an ONO dielectric layer are then formed, respectively, on the inner surface of the trenches.
- a doped polysilicon layer is formed on the silicon substrate to fill the trenches.
- a second PEP is performed to remove a portion of the doped polysilicon layer so as to form two controlling gates in the active area.
- a self-alignment source (SAS) etching process is then performed to form a common source between the two controlling gates.
- a plurality of spacers are then formed on the either side of each controlling gate.
- a self-alignment silicide (salicide) process is performed to form a silicide layer on the surfaces of both the controlling gates and the common source to finish the fabrication of the trenched flash memory cell of the present invention.
- the trench structure buried in the silicon substrate is used to form the stacked gate of the stacked-gate flash memory cell.
- the coupling surface area between the floating gate and the controlling gate is thus efficiently increased by increasing the depth or width of the stacked gate buried within the silicon substrate.
- integration of the elements formed thereafter on the silicon substrate is not sacrificed, and the accessing speed of the flash memory cell is raised.
- FIG. 1 is a cross-sectional diagram of a conventional flash memory cell.
- FIG. 2 is a cross-sectional diagram of a trenched flash memory cell according to the present invention.
- FIG. 3 is a top view of the trenched flash memory cell shown in FIG. 2.
- FIG. 4 to FIG. 11 are schematic diagrams of a method of fabricating a trenched flash memory cell according to the present invention.
- FIG. 2 is a cross-sectional diagram of a trenched flash memory cell 30 formed on a silicon substrate 32 according to the present invention.
- the silicon substrate 32 is a silicon-on-insulator (SOI) substrate or a single crystal silicon substrate, over which a memory array area and a periphery circuits region are predetermined.
- SOI silicon-on-insulator
- At least a P-well 34 and a N-well (not shown) are formed within the silicon substrate 32 in the memory array area.
- the trenched flash memory cell 30 comprises two stacked gates 42 buried in the P-well 34 within the silicon substrate 32 , a common source 36 positioned on the surface of the silicon substrate 32 between the two stacked gates 42 , two drains 38 positioned on the silicon substrate 32 at an opposing side of each stacked gate 42 , and a dielectric layer 40 positioned on the surfaces of the common source 36 and the drains 38 to isolate the stacked gate 42 from the common source 36 and the drains 38 .
- the stacked gate 42 is composed of a tunnel oxide layer 44 , a floating gate 46 , an ONO dielectric layer 48 , and a controlling gate 50 stacked, respectively, and partially buried in the silicon substrate 32 .
- a spacer 52 is formed on either side of each stacked gate 42 .
- a silicide layer 54 is also formed on the surfaces of the stacked gates 42 and the common source 36 to reduce resistance.
- FIG. 3 is a top view of the trenched flash memory cell 30 shown in FIG. 2.
- a plurality of shallow trench isolation structures 56 are formed to produce two active areas 58 within the silicon substrate 32 .
- the active areas 58 comprising a plurality of trenches 61 buried in the silicon substrate 32 , are perpendicular to a plurality of parallel word lines 60 .
- a bit line 62 is positioned between two word lines 60 .
- FIG. 4 to FIG. 11 are schematic diagrams of a method of fabricating the trenched flash memory cell 30 on the silicon substrate 32 according to the present invention.
- the present invention method first involves the use of a shallow trench isolation process. During this process, conventional photolithographic and etching methods are used to form a plurality of shallow trench isolation structures 56 in the silicon substrate 32 . An active area 58 , enclosed by the shallow trench isolation structures 56 , is then defined on the surface of the silicon substrate 32 . Thereafter, a chemical vapor deposition (CVD) process is performed to form an oxide layer 64 to fill each of the shallow trench isolation structures 56 .
- CVD chemical vapor deposition
- a photoresist layer (not shown) is formed to cover both the periphery circuits region and the N-well portion in the memory array area, followed by a first ion implantation process to form a buried N + doped region 35 on the surface of the P-well 34 within the active area 58 .
- An isolation layer 40 is then formed on the surface of the silicon substrate 32 .
- the isolation layer 40 may be a silicon dioxide layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method.
- FIG. 5 which is a sectional view along line BB′ of FIG. 3, a photoresist layer 66 is subsequently formed on the surface of the isolation layer 40 and patterned by a photolithographic process to predetermine the position of two trenches 61 .
- an etching process is performed using the photoresist layer 66 as a mask to both remove the isolation layer 40 to a predetermined depth within the P-well 34 and to form two trenches 61 within the P-well 34 .
- the two trenches 61 divide the doped region 35 into a common source 36 positioned between the two trenches 61 , and two drains 38 positioned an opposing side of each trench 61 .
- a thermal oxidation process is then performed to grow a silicon dioxide layer on the inner surface of the trenches 61 so as to function as a tunnel oxide layer 44 .
- a CVD process is used to deposit a doped polysilicon layer (not shown) on the surface of the silicon substrate 32 .
- the thickness of deposition of the doped polysilicon layer is controlled to be approximately half to three quarters of the radius of the trench 61 .
- the doped polysilicon layer is removed except in the region within the trenches 61 so as to form a floating gate 46 in the trenches 61 .
- an oxide-nitride-oxide (ONO) process is performed so as to form an ONO dielectric layer 48 on the silicon substrate 32 in the memory array area.
- a CVD process is then used to deposit another doped polysilicon layer 49 on the entire surface of the silicon substrate 32 , including the silicon substrate 32 in the periphery circuits region.
- the doped polysilicon layer 49 fills in the trenches 61 .
- a photo and etching process PEP
- PEP photo and etching process
- the PEP simultaneously forms a plurality of gates (not shown) in the periphery circuits region.
- a photoresist layer 68 is formed on the surface of the silicon substrate 32 , followed by a photolithographic process to form an opening in the photoresist layer 68 to expose the isolation layer 40 in the region between the two controlling gates 50 .
- a self-alignment source (SAS) etching process is performed using the patterned photoresist layer 68 as a mask to remove the isolation layer 40 positioned between the two controlling gates 50 down to the surface of the common source 36 .
- the method of removing the isolation layer 40 involves using a fluorocarbon plasma to selectively etch between silicon dioxide (the isolation layer 40 ) and doped polysilicon (the common source 36 ). And if necessary, a portion of the common source 36 is over etched to ensure the complete removal of the isolation layer 40 between the two controlling gates 50 .
- the silicon dioxide filled in the shallow trench isolation structures 56 adjacent to the common sources 36 is also selectively removed down to the surface of the silicon substrate 32 during this process.
- the photoresist layer 68 is again used as a mask to perform a second ion implantation process, using the N-type dopants such as arsenic atoms to heavily implant the common source 36 , to finish fabrication of the stacked gate 42 .
- the photoresist layer 68 is then removed, followed by the deposition of a silicon nitride layer (not shown).
- an anisotropic etching process is performed to etch back a portion of the silicon nitride layer so as to form a spacer 52 , using the remaining silicon nitride layer, on either vertical sidewall of each stacked gate 42 .
- a titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (W) metal layer (not shown) is formed on the surface of the silicon substrate 32 .
- a thermal processing is then used to induce a reaction between the metal layer and the silicon in the common source 36 , so that a self-alignment silicide (salicide) layer 54 is formed to function in reducing sheet resistance.
- the salicide layer 54 is also formed on the silicon substrate 32 between the common sources 36 , connecting with the salicide layer 54 positioned atop each of the common sources 36 to form the bit line 62 , as shown in FIG. 3, to complete the fabrication of the trenched flash memory cell 30 of the present invention.
- the present invention method uses the PEP of forming the trenches 61 to simultaneously form a self-alignment source 36 between the two trenches 61 . Furthermore, the active areas 58 not occupied by the stacked gate 42 and the common source 36 automatically form the drains 38 . As a result, subsequent photolithographic processes are unnecessary to define the drain 38 and source 36 . As well, the source 36 and drain 38 of the trenched flash memory cell 30 horizontally surround the floating gate 46 such that the channel length between the floating gate 46 and the source 36 /drain 38 is increased.
- the Fowler Nordheim tunneling technique facilitates both data storage and removal during operation of the trenched flash memory cell 30 by injecting electrons into the floating gate 46 or neutralizing the electrons in the floating gate 46 .
- the controlling gate 50 when the controlling gate 50 is applied a high voltage, the drain 38 is negatively biased and the source 36 is floated, electrons are emitted from the drain 38 into the floating gate 46 to be stored.
- the controlling gate 50 when the controlling gate 50 is grounded or negatively biased, the source 36 is applied a high voltage and the drain 38 is floated, electrons stored in the floating gate 46 are ejected.
- the method of the present invention uses a trench structure buried in the silicon substrate to form the stacked gate.
- the coupling surface area between the floating gate and the controlling gate is increased via the increase in depth or width of the stacked gate buried in the silicon substrate.
- the present invention uses a self-aligned technique to form the common source and the drains, and thus, prevents damage resulting from the conventional source/drain process.
- the present invention forms the salicide layer on the surface of both the gate and the source to reduce resistance to improve the electrical performance and the quality of the flash memory cell.
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a method of fabricating a trenched flash memory cell, and more particularly, to a method of fabricating a trenched flash memory cell to raise the coupling ratio (CR) and hence improve the electrical performance of the element.
- 2. Description of the Prior Art
- A stacked-gate flash memory cell comprises a floating gate for storing electric charges, a controlling gate for controlling the charging of the floating gate, and an ONO (oxide-nitride-oxide) dielectric layer positioned between the floating gate and the controlling gate. Similar to a capacitor, the flash memory stores electric charges in the floating gate to represent a digital data bit of “1”, and removes charge from the floating gate to represent a digital data bit of “0”.
- Please refer to FIG. 1. FIG. 1 is a cross-sectional diagram of a conventional stacked-gate
flash memory cell 10. As shown in FIG. 1, theflash memory cell 10 comprises a stackedgate 14 positioned on the surface of asilicon substrate 12, asource 24 and drain 26 positioned adjacent to each side of thestacked gate 14. The stackedgate 14 is composed of atunnel oxide layer 16, afloating gate 18, an ONOdielectric layer 20 and a controllinggate 22, respectively. By virtue of channel hot electrons (CHE) effects, the hot electrons are injected into thefloating gate 18 from thedrain 26 through thetunnel oxide layer 16 so as to achieve data storage. A Fowler Nordheim tunneling technique is used for data erase, which involves grounding of the controllinggate 22 or applying a negative voltage to the controllinggate 22. As a result, thedrain 26 is highly biased so as to expel the electrons trapped in thefloating gate 18. - In general, a coupling ratio (CR value) is used as an index to evaluate the performance of a flash memory cell. Assuming that C1 is the capacitance between the
floating gate 18 and the controllinggate 22, C2 is the capacitance between thefloating gate 18 and thesource 24, C3 is the capacitance between thefloating gate 18 and thesilicon substrate 12, and C4 is the capacitance between thefloating gate 18 and thedrain 26, the CR value of theflash memory cell 10 is defined as: - CR=C 1/(C 1 +C 2 +C 3 +C 4)
- Wherein, the higher the coupling ratio, the better the performance of the flash memory cell. According to the above equation, one method of increasing the CR value is to increase the capacitor surface between the
floating gate 18 and the controllinggate 22, as this surface is proportional to the capacitance C1. However, surface enlargement is limited as the line width of either thefloating gate 18 or the controllinggate 22 is defined to increase the element integration. Thus, difficulty occurs in raising both the capacitance and accessing speed of theflash memory cell 10 through the increase of the surface area of thefloating gate 18 or the controllinggate 22. In addition, although the stacked-gateflash memory cell 10 enhances integration, it is, however, prone to over-erasing. - It is therefore an objective of the present invention to provide a method of fabricating a trenched flash memory cell to efficiently increase the CR value and simultaneously improve the electrical performance of the elements.
- In a preferred embodiment of the present invention, a plurality of shallow trench isolation (STI) structures are formed to enclose at least an active area in a silicon substrate. Next, a first ion implantation process is performed on the silicon substrate to form a doped region, followed by the deposition of an isolation layer on the surface of the silicon substrate. A first photo and etching process (PEP) is performed to form two trenches within the active area. A tunnel oxide layer, a floating gate, and an ONO dielectric layer are then formed, respectively, on the inner surface of the trenches. Subsequently, a doped polysilicon layer is formed on the silicon substrate to fill the trenches. A second PEP is performed to remove a portion of the doped polysilicon layer so as to form two controlling gates in the active area. A self-alignment source (SAS) etching process is then performed to form a common source between the two controlling gates. A plurality of spacers are then formed on the either side of each controlling gate. At last, a self-alignment silicide (salicide) process is performed to form a silicide layer on the surfaces of both the controlling gates and the common source to finish the fabrication of the trenched flash memory cell of the present invention.
- It is an advantage of the present invention that the trench structure buried in the silicon substrate is used to form the stacked gate of the stacked-gate flash memory cell. The coupling surface area between the floating gate and the controlling gate is thus efficiently increased by increasing the depth or width of the stacked gate buried within the silicon substrate. As a result, integration of the elements formed thereafter on the silicon substrate is not sacrificed, and the accessing speed of the flash memory cell is raised.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
- FIG. 1 is a cross-sectional diagram of a conventional flash memory cell.
- FIG. 2 is a cross-sectional diagram of a trenched flash memory cell according to the present invention.
- FIG. 3 is a top view of the trenched flash memory cell shown in FIG. 2.
- FIG. 4 to FIG. 11 are schematic diagrams of a method of fabricating a trenched flash memory cell according to the present invention.
- Please refer to FIG. 2. FIG. 2 is a cross-sectional diagram of a trenched
flash memory cell 30 formed on asilicon substrate 32 according to the present invention. As shown in FIG. 2, thesilicon substrate 32 is a silicon-on-insulator (SOI) substrate or a single crystal silicon substrate, over which a memory array area and a periphery circuits region are predetermined. At least a P-well 34 and a N-well (not shown) are formed within thesilicon substrate 32 in the memory array area. - In a better embodiment of the present invention, the trenched
flash memory cell 30 comprises twostacked gates 42 buried in the P-well 34 within thesilicon substrate 32, acommon source 36 positioned on the surface of thesilicon substrate 32 between the two stackedgates 42, twodrains 38 positioned on thesilicon substrate 32 at an opposing side of each stackedgate 42, and adielectric layer 40 positioned on the surfaces of thecommon source 36 and thedrains 38 to isolate thestacked gate 42 from thecommon source 36 and thedrains 38. The stackedgate 42 is composed of atunnel oxide layer 44, afloating gate 46, an ONOdielectric layer 48, and a controllinggate 50 stacked, respectively, and partially buried in thesilicon substrate 32. In addition, aspacer 52 is formed on either side of eachstacked gate 42. Asilicide layer 54 is also formed on the surfaces of thestacked gates 42 and thecommon source 36 to reduce resistance. - Please refer to FIG. 3. FIG. 3 is a top view of the trenched
flash memory cell 30 shown in FIG. 2. As illustrated in FIG. 3, a plurality of shallowtrench isolation structures 56 are formed to produce twoactive areas 58 within thesilicon substrate 32. Theactive areas 58, comprising a plurality oftrenches 61 buried in thesilicon substrate 32, are perpendicular to a plurality ofparallel word lines 60. Furthermore, a bit line 62 is positioned between twoword lines 60. - Please refer to FIG. 4 to FIG. 11. FIG. 4 to FIG. 11 are schematic diagrams of a method of fabricating the trenched
flash memory cell 30 on thesilicon substrate 32 according to the present invention. As shown in FIG. 4, which is a sectional view along line AA′ of FIG. 3, the present invention method first involves the use of a shallow trench isolation process. During this process, conventional photolithographic and etching methods are used to form a plurality of shallowtrench isolation structures 56 in thesilicon substrate 32. Anactive area 58, enclosed by the shallowtrench isolation structures 56, is then defined on the surface of thesilicon substrate 32. Thereafter, a chemical vapor deposition (CVD) process is performed to form anoxide layer 64 to fill each of the shallowtrench isolation structures 56. A photoresist layer (not shown) is formed to cover both the periphery circuits region and the N-well portion in the memory array area, followed by a first ion implantation process to form a buried N+ dopedregion 35 on the surface of the P-well 34 within theactive area 58. Anisolation layer 40 is then formed on the surface of thesilicon substrate 32. Theisolation layer 40 may be a silicon dioxide layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method. - As shown in FIG. 5, which is a sectional view along line BB′ of FIG. 3, a
photoresist layer 66 is subsequently formed on the surface of theisolation layer 40 and patterned by a photolithographic process to predetermine the position of twotrenches 61. As shown in FIG. 6, an etching process is performed using thephotoresist layer 66 as a mask to both remove theisolation layer 40 to a predetermined depth within the P-well 34 and to form twotrenches 61 within the P-well 34. The twotrenches 61 divide the dopedregion 35 into acommon source 36 positioned between the twotrenches 61, and twodrains 38 positioned an opposing side of eachtrench 61. A thermal oxidation process is then performed to grow a silicon dioxide layer on the inner surface of thetrenches 61 so as to function as atunnel oxide layer 44. - Next, as shown in FIG. 7, a CVD process is used to deposit a doped polysilicon layer (not shown) on the surface of the
silicon substrate 32. To avoid completely filling thetrenches 61, the thickness of deposition of the doped polysilicon layer is controlled to be approximately half to three quarters of the radius of thetrench 61. Thereafter, the doped polysilicon layer is removed except in the region within thetrenches 61 so as to form a floatinggate 46 in thetrenches 61. - As shown in FIG. 8, an oxide-nitride-oxide (ONO) process is performed so as to form an
ONO dielectric layer 48 on thesilicon substrate 32 in the memory array area. A CVD process is then used to deposit another dopedpolysilicon layer 49 on the entire surface of thesilicon substrate 32, including thesilicon substrate 32 in the periphery circuits region. The dopedpolysilicon layer 49 fills in thetrenches 61. Thereafter, a photo and etching process (PEP) is performed to etch a portion of the dopedpolysilicon layer 49 as well as to form twocontrolling gates 50 above each of the twotrenches 61, as shown in FIG. 9. In other words, twoword lines 60 as shown in FIG. 3 are formed crossing theactive areas 58. As well, the PEP simultaneously forms a plurality of gates (not shown) in the periphery circuits region. Thereafter, aphotoresist layer 68 is formed on the surface of thesilicon substrate 32, followed by a photolithographic process to form an opening in thephotoresist layer 68 to expose theisolation layer 40 in the region between the twocontrolling gates 50. - Next, as shown in FIG. 10, a self-alignment source (SAS) etching process is performed using the patterned
photoresist layer 68 as a mask to remove theisolation layer 40 positioned between the twocontrolling gates 50 down to the surface of thecommon source 36. The method of removing theisolation layer 40 involves using a fluorocarbon plasma to selectively etch between silicon dioxide (the isolation layer 40) and doped polysilicon (the common source 36). And if necessary, a portion of thecommon source 36 is over etched to ensure the complete removal of theisolation layer 40 between the twocontrolling gates 50. In addition, the silicon dioxide filled in the shallowtrench isolation structures 56 adjacent to thecommon sources 36, as shown in FIG. 3, is also selectively removed down to the surface of thesilicon substrate 32 during this process. - Thereafter, the
photoresist layer 68 is again used as a mask to perform a second ion implantation process, using the N-type dopants such as arsenic atoms to heavily implant thecommon source 36, to finish fabrication of the stackedgate 42. Thephotoresist layer 68 is then removed, followed by the deposition of a silicon nitride layer (not shown). Next, an anisotropic etching process is performed to etch back a portion of the silicon nitride layer so as to form aspacer 52, using the remaining silicon nitride layer, on either vertical sidewall of eachstacked gate 42. - At last, as shown in FIG. 1, a titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (W) metal layer (not shown) is formed on the surface of the
silicon substrate 32. A thermal processing is then used to induce a reaction between the metal layer and the silicon in thecommon source 36, so that a self-alignment silicide (salicide)layer 54 is formed to function in reducing sheet resistance. Simultaneously, thesalicide layer 54 is also formed on thesilicon substrate 32 between thecommon sources 36, connecting with thesalicide layer 54 positioned atop each of thecommon sources 36 to form the bit line 62, as shown in FIG. 3, to complete the fabrication of the trenchedflash memory cell 30 of the present invention. - The present invention method uses the PEP of forming the
trenches 61 to simultaneously form a self-alignment source 36 between the twotrenches 61. Furthermore, theactive areas 58 not occupied by the stackedgate 42 and thecommon source 36 automatically form thedrains 38. As a result, subsequent photolithographic processes are unnecessary to define thedrain 38 andsource 36. As well, thesource 36 and drain 38 of the trenchedflash memory cell 30 horizontally surround the floatinggate 46 such that the channel length between the floatinggate 46 and thesource 36/drain 38 is increased. As a result, the Fowler Nordheim tunneling technique facilitates both data storage and removal during operation of the trenchedflash memory cell 30 by injecting electrons into the floatinggate 46 or neutralizing the electrons in the floatinggate 46. For example, when the controllinggate 50 is applied a high voltage, thedrain 38 is negatively biased and thesource 36 is floated, electrons are emitted from thedrain 38 into the floatinggate 46 to be stored. Conversely, when the controllinggate 50 is grounded or negatively biased, thesource 36 is applied a high voltage and thedrain 38 is floated, electrons stored in the floatinggate 46 are ejected. - In contrast to the prior art of fabricating the flash memory cell, the method of the present invention uses a trench structure buried in the silicon substrate to form the stacked gate. Hence, the coupling surface area between the floating gate and the controlling gate is increased via the increase in depth or width of the stacked gate buried in the silicon substrate. Most importantly, integration of the elements subsequently formed on the substrate is not affected and the accessing speed of the flash memory cell is increased. In addition, the present invention uses a self-aligned technique to form the common source and the drains, and thus, prevents damage resulting from the conventional source/drain process. Also, the present invention forms the salicide layer on the surface of both the gate and the source to reduce resistance to improve the electrical performance and the quality of the flash memory cell.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (16)
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US11903193B2 (en) * | 2020-08-24 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company Limited | Two dimensional structure to control flash operation and methods for forming the same |
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